1 | /* |
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2 | * $Id$ |
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3 | * |
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4 | * This file contains all assembly code for the |
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5 | * NIOS2 implementation of RTEMS. |
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6 | * |
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7 | * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de) |
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8 | * |
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9 | * Derived from no_cpu/cpu_asm.S, copyright (c) 1989-1999, |
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10 | * On-Line Applications Research Corporation (OAR). |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.com/license/LICENSE. |
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15 | * |
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16 | */ |
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17 | |
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18 | #ifdef HAVE_CONFIG_H |
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19 | #include "config.h" |
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20 | #endif |
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21 | |
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22 | #include <rtems/asm.h> |
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23 | #include <rtems/score/cpu_asm.h> |
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24 | |
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25 | .set noat |
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26 | |
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27 | .globl _exception_vector |
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28 | |
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29 | _exception_vector: |
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30 | |
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31 | /* |
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32 | * First, re-wind so we're pointed to the instruction where the exception |
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33 | * occurred. |
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34 | */ |
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35 | |
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36 | addi ea, ea, -4 |
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37 | |
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38 | /* |
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39 | * Now test to determine the cause of the exception. |
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40 | */ |
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41 | |
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42 | /* TODO: Look at [ea] if there was an unknown/trap instruction */ |
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43 | |
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44 | /* If interrupts are globally disabled, it certainly was no interrupt */ |
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45 | rdctl et, estatus |
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46 | andi et, et, 1 |
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47 | beq et, zero, _Exception_Handler |
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48 | |
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49 | /* If no interrupts are pending, it was a software exception */ |
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50 | rdctl et, ipending |
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51 | beq et, zero, _Exception_Handler |
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52 | |
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53 | /* |
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54 | * Falling through to here means that this was a hardware interrupt. |
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55 | */ |
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56 | |
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57 | br _ISR_Handler |
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58 | |
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59 | /* ===================================================================== |
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60 | * Exception handler: |
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61 | * Responsible for unimplemented instructions and other software |
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62 | * exceptions. Not responsible for hardware interrupts. Currently, |
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63 | * software exceptions are regarded as error conditions, and the |
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64 | * handling isn't perfect. */ |
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65 | |
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66 | _Exception_Handler: |
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67 | |
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68 | /* stw et, 108(sp') => stw et, -20(sp) */ |
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69 | stw et, -20(sp) |
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70 | mov et, sp |
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71 | addi sp, sp, -128 |
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72 | |
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73 | stw r1, 0(sp) |
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74 | stw r2, 4(sp) |
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75 | stw r3, 8(sp) |
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76 | |
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77 | rdctl r1, estatus |
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78 | rdctl r2, ienable |
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79 | rdctl r3, ipending |
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80 | |
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81 | stw r4, 12(sp) |
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82 | stw r5, 16(sp) |
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83 | stw r6, 20(sp) |
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84 | stw r7, 24(sp) |
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85 | stw r8, 28(sp) |
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86 | stw r9, 32(sp) |
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87 | stw r10, 36(sp) |
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88 | stw r11, 40(sp) |
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89 | stw r12, 44(sp) |
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90 | stw r13, 48(sp) |
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91 | stw r14, 52(sp) |
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92 | stw r15, 56(sp) |
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93 | stw r16, 60(sp) |
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94 | stw r17, 64(sp) |
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95 | stw r18, 68(sp) |
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96 | stw r19, 72(sp) |
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97 | stw r20, 76(sp) |
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98 | stw r21, 80(sp) |
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99 | stw r22, 84(sp) |
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100 | stw r23, 88(sp) |
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101 | stw gp, 92(sp) |
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102 | stw fp, 96(sp) |
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103 | /* sp */ |
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104 | stw et, 100(sp) |
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105 | stw ra, 104(sp) |
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106 | /* stw et, 108(sp) */ |
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107 | stw ea, 112(sp) |
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108 | |
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109 | /* status */ |
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110 | stw r1, 116(sp) |
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111 | /* ienable */ |
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112 | stw r2, 120(sp) |
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113 | /* ipending */ |
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114 | stw r3, 124(sp) |
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115 | |
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116 | /* |
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117 | * Restore the global pointer. |
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118 | */ |
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119 | |
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120 | movhi gp, %hiadj(_gp) |
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121 | addi gp, gp, %lo(_gp) |
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122 | |
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123 | /* |
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124 | * Pass a pointer to the stack frame as the input argument of the |
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125 | * exception handler (CPU_Exception_frame *). |
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126 | */ |
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127 | |
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128 | mov r4, sp |
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129 | |
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130 | /* |
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131 | * Call the exception handler. |
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132 | */ |
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133 | |
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134 | .extern __Exception_Handler |
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135 | call __Exception_Handler |
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136 | |
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137 | stuck_in_exception: |
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138 | br stuck_in_exception |
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139 | |
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140 | /* |
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141 | * Restore the saved registers, so that all general purpose registers |
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142 | * have been restored to their state at the time the interrupt occured. |
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143 | */ |
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144 | |
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145 | ldw r1, 0(sp) |
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146 | ldw r2, 4(sp) |
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147 | ldw r3, 8(sp) |
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148 | ldw r4, 12(sp) |
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149 | ldw r5, 16(sp) |
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150 | ldw r6, 20(sp) |
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151 | ldw r7, 24(sp) |
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152 | ldw r8, 28(sp) |
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153 | ldw r9, 32(sp) |
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154 | ldw r10, 36(sp) |
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155 | ldw r11, 40(sp) |
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156 | ldw r12, 44(sp) |
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157 | ldw r13, 48(sp) |
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158 | ldw r14, 52(sp) |
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159 | ldw r15, 56(sp) |
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160 | ldw r16, 60(sp) |
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161 | ldw r17, 64(sp) |
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162 | ldw r18, 68(sp) |
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163 | ldw r19, 72(sp) |
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164 | ldw r20, 76(sp) |
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165 | ldw r21, 80(sp) |
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166 | ldw r22, 84(sp) |
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167 | ldw r23, 88(sp) |
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168 | ldw gp, 92(sp) |
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169 | ldw fp, 96(sp) |
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170 | ldw ra, 104(sp) |
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171 | |
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172 | /* Disable interrupts */ |
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173 | wrctl status, r0 |
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174 | |
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175 | ldw ea, 112(sp) |
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176 | ldw et, 116(sp) |
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177 | |
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178 | /* FIXME: Enable interrupts after exception processing */ |
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179 | ori et, et, 1 |
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180 | wrctl estatus, et |
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181 | ldw et, 108(sp) |
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182 | |
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183 | /* Restore stack pointer */ |
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184 | ldw sp, 100(sp) |
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185 | |
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186 | eret |
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187 | |
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188 | /* ===================================================================== */ |
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189 | |
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190 | .section .text |
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191 | |
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192 | _ISR_Handler: |
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193 | |
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194 | /* |
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195 | * Process an external hardware interrupt. |
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196 | * |
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197 | * First, preserve all callee saved registers on |
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198 | * the stack. (See the Nios2 ABI documentation for details). |
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199 | * |
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200 | * Do we really need to save all? |
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201 | * |
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202 | * If this is interrupting a task (and not another interrupt), |
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203 | * everything is saved into the task's stack, thus putting us |
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204 | * in a situation similar to when the task calls a subroutine |
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205 | * (and only the CPU_Context_Control subset needs to be changed) |
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206 | */ |
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207 | |
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208 | rdctl et, estatus |
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209 | |
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210 | /* Keep this in the same order as CPU_Interrupt_frame: */ |
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211 | |
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212 | addi sp, sp, -76 |
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213 | stw r1, 0(sp) |
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214 | stw r2, 4(sp) |
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215 | stw r3, 8(sp) |
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216 | stw r4, 12(sp) |
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217 | stw r5, 16(sp) |
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218 | stw r6, 20(sp) |
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219 | stw r7, 24(sp) |
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220 | stw r8, 28(sp) |
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221 | stw r9, 32(sp) |
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222 | stw r10, 36(sp) |
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223 | stw r11, 40(sp) |
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224 | stw r12, 44(sp) |
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225 | stw r13, 48(sp) |
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226 | stw r14, 52(sp) |
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227 | stw r15, 56(sp) |
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228 | stw ra, 60(sp) |
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229 | stw gp, 64(sp) |
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230 | /* et contains status */ |
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231 | stw et, 68(sp) |
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232 | stw ea, 72(sp) |
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233 | |
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234 | /* |
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235 | * Obtain a bitlist of the pending interrupts. |
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236 | */ |
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237 | |
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238 | rdctl et, ipending |
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239 | |
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240 | /* |
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241 | * Restore the global pointer to the expected value. |
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242 | */ |
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243 | |
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244 | movhi gp, %hiadj(_gp) |
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245 | addi gp, gp, %lo(_gp) |
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246 | |
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247 | /* |
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248 | * Search through the bit list stored in r24(et) to find the first enabled |
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249 | * bit. The offset of this bit is the index of the interrupt that is |
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250 | * to be handled. |
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251 | */ |
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252 | |
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253 | mov r4, zero |
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254 | 6: |
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255 | andi r3, r24, 1 |
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256 | bne r3, zero, 7f |
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257 | addi r4, r4, 1 |
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258 | srli r24, r24, 1 |
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259 | br 6b |
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260 | 7: |
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261 | |
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262 | /* |
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263 | * Having located the interrupt source, r4 contains the index of the |
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264 | * interrupt to be handled. r5, the 2nd argument to the function, |
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265 | * will point to the CPU_Interrupt_frame. |
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266 | */ |
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267 | |
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268 | mov r5, sp |
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269 | |
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270 | .extern __ISR_Handler |
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271 | call __ISR_Handler |
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272 | |
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273 | /* |
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274 | * Now that the interrupt processing is complete, prepare to return to |
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275 | * the interrupted code. |
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276 | */ |
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277 | |
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278 | /* |
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279 | * Restore the saved registers, so that all general purpose registers |
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280 | * have been restored to their state at the time the interrupt occured. |
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281 | */ |
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282 | |
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283 | ldw r1, 0(sp) |
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284 | ldw r2, 4(sp) |
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285 | ldw r3, 8(sp) |
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286 | ldw r4, 12(sp) |
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287 | ldw r5, 16(sp) |
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288 | ldw r6, 20(sp) |
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289 | ldw r7, 24(sp) |
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290 | ldw r8, 28(sp) |
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291 | ldw r9, 32(sp) |
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292 | ldw r10, 36(sp) |
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293 | ldw r11, 40(sp) |
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294 | ldw r12, 44(sp) |
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295 | ldw r13, 48(sp) |
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296 | ldw r14, 52(sp) |
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297 | ldw r15, 56(sp) |
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298 | ldw ra, 60(sp) |
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299 | ldw gp, 64(sp) |
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300 | |
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301 | /* Disable interrupts */ |
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302 | wrctl status, r0 |
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303 | |
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304 | /* Restore the exception registers */ |
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305 | |
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306 | /* load saved ea into ea */ |
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307 | ldw ea, 72(sp) |
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308 | /* load saved estatus into et */ |
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309 | ldw et, 68(sp) |
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310 | /* Always have interrupts enabled when we return from interrupt */ |
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311 | ori et, et, 1 |
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312 | wrctl estatus, et |
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313 | /* Restore the stack pointer */ |
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314 | addi sp, sp, 76 |
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315 | |
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316 | /* |
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317 | * Return to the interrupted instruction. |
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318 | */ |
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319 | eret |
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320 | |
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321 | |
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