source: rtems/cpukit/score/cpu/nios2/nios2-iic-irq.c @ f82752a4

4.115
Last change on this file since f82752a4 was f82752a4, checked in by Daniel Hellstrom <daniel@…>, on Jun 4, 2014 at 9:23:34 AM

Let CPU/BSP Fatal handler have access to source

Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.

This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.

  • Property mode set to 100644
File size: 3.1 KB
Line 
1/**
2 * @file
3 *
4 * @brief NIOS2 Exception and Interrupt Handler
5 *
6 * @note Derived from c4x/irq.c
7 */
8
9/*
10 *  COPYRIGHT (c) 1989-2007.
11 *  On-Line Applications Research Corporation (OAR).
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.rtems.org/license/LICENSE.
16 */
17
18#ifdef HAVE_CONFIG_H
19#include "config.h"
20#endif
21
22#include <rtems/system.h>
23#include <rtems/score/cpu.h>
24#include <rtems/score/isr.h>
25#include <rtems/score/threaddispatch.h>
26#include <rtems/score/nios2-utility.h>
27
28/*
29 *  This routine provides the RTEMS interrupt management.
30 *
31 *  Upon entry, interrupts are disabled
32 */
33
34#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
35  unsigned long    *_old_stack_ptr;
36#endif
37
38register unsigned long  *stack_ptr __asm__ ("sp");
39
40RTEMS_INLINE_ROUTINE void __IIC_Handler(void)
41{
42  uint32_t active;
43  uint32_t mask;
44  uint32_t vector;
45
46  /*
47   * Obtain from the interrupt controller a bit list of pending interrupts,
48   * and then process the highest priority interrupt. This process loops,
49   * loading the active interrupt list on each pass until ipending
50   * return zero.
51   *
52   * The maximum interrupt latency for the highest priority interrupt is
53   * reduced by finding out which interrupts are pending as late as possible.
54   * Consider the case where the high priority interupt is asserted during
55   * the interrupt entry sequence for a lower priority interrupt to see why
56   * this is the case.
57   */
58
59  active = _Nios2_Get_ctlreg_ipending();
60
61  while (active)
62  {
63    vector = 0;
64    mask = 1;
65
66    /*
67     * Test each bit in turn looking for an active interrupt. Once one is
68     * found call it to clear the interrupt condition.
69     */
70
71    while (active)
72    {
73      if (active & mask)
74      {
75        if ( _ISR_Vector_table[ vector] )
76          (*_ISR_Vector_table[ vector ])(vector);
77        active &= ~mask;
78      }
79      mask <<= 1;
80      ++vector;
81    };
82
83    active = _Nios2_Get_ctlreg_ipending();
84  }
85
86}
87
88void __ISR_Handler(void)
89{
90  register uint32_t level;
91
92  /* Interrupts are disabled upon entry to this Handler */
93
94#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
95  if ( _ISR_Nest_level == 0 ) {
96    /* Install irq stack */
97    _old_stack_ptr = stack_ptr;
98    stack_ptr = _CPU_Interrupt_stack_high - 4;
99  }
100#endif
101
102  _ISR_Nest_level++;
103
104  _Thread_Dispatch_increment_disable_level();
105
106  __IIC_Handler();
107
108  /* Make sure that interrupts are disabled again */
109  _CPU_ISR_Disable( level );
110
111  _Thread_Dispatch_decrement_disable_level();
112
113  _ISR_Nest_level--;
114
115  if( _ISR_Nest_level == 0) {
116#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
117    stack_ptr = _old_stack_ptr;
118#endif
119
120    if( _Thread_Dispatch_is_enabled() )
121    {
122      if ( _Thread_Dispatch_necessary ) {
123        _CPU_ISR_Enable( level );
124        _Thread_Dispatch();
125        /* may have switched to another task and not return here immed. */
126        _CPU_ISR_Disable( level ); /* Keep _pairs_ of Enable/Disable */
127      }
128    }
129  }
130
131  _CPU_ISR_Enable( level );
132}
133
134void __Exception_Handler(CPU_Exception_frame *efr)
135{
136  _CPU_Fatal_halt(RTEMS_FATAL_SOURCE_EXCEPTION, 0xECC0); /* source ignored */
137}
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