1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief NIOS2 Exception and Interrupt Handler |
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5 | * |
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6 | * @note Derived from c4x/irq.c |
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7 | */ |
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8 | |
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9 | /* |
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10 | * COPYRIGHT (c) 1989-2007. |
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11 | * On-Line Applications Research Corporation (OAR). |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.org/license/LICENSE. |
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16 | */ |
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17 | |
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18 | #ifdef HAVE_CONFIG_H |
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19 | #include "config.h" |
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20 | #endif |
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21 | |
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22 | #include <rtems/system.h> |
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23 | #include <rtems/score/cpu.h> |
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24 | #include <rtems/score/isr.h> |
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25 | #include <rtems/score/threaddispatch.h> |
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26 | #include <rtems/score/nios2-utility.h> |
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27 | |
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28 | /* |
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29 | * This routine provides the RTEMS interrupt management. |
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30 | * |
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31 | * Upon entry, interrupts are disabled |
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32 | */ |
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33 | |
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34 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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35 | unsigned long *_old_stack_ptr; |
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36 | #endif |
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37 | |
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38 | register unsigned long *stack_ptr __asm__ ("sp"); |
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39 | |
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40 | RTEMS_INLINE_ROUTINE void __IIC_Handler(void) |
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41 | { |
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42 | uint32_t active; |
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43 | uint32_t mask; |
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44 | uint32_t vector; |
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45 | |
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46 | /* |
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47 | * Obtain from the interrupt controller a bit list of pending interrupts, |
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48 | * and then process the highest priority interrupt. This process loops, |
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49 | * loading the active interrupt list on each pass until ipending |
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50 | * return zero. |
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51 | * |
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52 | * The maximum interrupt latency for the highest priority interrupt is |
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53 | * reduced by finding out which interrupts are pending as late as possible. |
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54 | * Consider the case where the high priority interupt is asserted during |
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55 | * the interrupt entry sequence for a lower priority interrupt to see why |
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56 | * this is the case. |
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57 | */ |
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58 | |
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59 | active = _Nios2_Get_ctlreg_ipending(); |
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60 | |
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61 | while (active) |
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62 | { |
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63 | vector = 0; |
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64 | mask = 1; |
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65 | |
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66 | /* |
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67 | * Test each bit in turn looking for an active interrupt. Once one is |
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68 | * found call it to clear the interrupt condition. |
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69 | */ |
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70 | |
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71 | while (active) |
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72 | { |
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73 | if (active & mask) |
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74 | { |
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75 | if ( _ISR_Vector_table[ vector] ) |
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76 | (*_ISR_Vector_table[ vector ])(vector); |
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77 | active &= ~mask; |
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78 | } |
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79 | mask <<= 1; |
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80 | ++vector; |
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81 | }; |
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82 | |
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83 | active = _Nios2_Get_ctlreg_ipending(); |
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84 | } |
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85 | |
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86 | } |
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87 | |
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88 | void __ISR_Handler(void) |
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89 | { |
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90 | register uint32_t level; |
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91 | |
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92 | /* Interrupts are disabled upon entry to this Handler */ |
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93 | |
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94 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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95 | if ( _ISR_Nest_level == 0 ) { |
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96 | /* Install irq stack */ |
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97 | _old_stack_ptr = stack_ptr; |
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98 | stack_ptr = _CPU_Interrupt_stack_high - 4; |
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99 | } |
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100 | #endif |
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101 | |
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102 | _ISR_Nest_level++; |
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103 | |
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104 | _Thread_Dispatch_increment_disable_level(); |
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105 | |
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106 | __IIC_Handler(); |
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107 | |
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108 | /* Make sure that interrupts are disabled again */ |
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109 | _CPU_ISR_Disable( level ); |
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110 | |
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111 | _Thread_Dispatch_decrement_disable_level(); |
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112 | |
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113 | _ISR_Nest_level--; |
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114 | |
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115 | if( _ISR_Nest_level == 0) { |
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116 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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117 | stack_ptr = _old_stack_ptr; |
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118 | #endif |
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119 | |
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120 | if( _Thread_Dispatch_is_enabled() ) |
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121 | { |
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122 | if ( _Thread_Dispatch_necessary ) { |
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123 | _CPU_ISR_Enable( level ); |
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124 | _Thread_Dispatch(); |
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125 | /* may have switched to another task and not return here immed. */ |
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126 | _CPU_ISR_Disable( level ); /* Keep _pairs_ of Enable/Disable */ |
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127 | } |
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128 | } |
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129 | } |
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130 | |
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131 | _CPU_ISR_Enable( level ); |
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132 | } |
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133 | |
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134 | void __Exception_Handler(CPU_Exception_frame *efr) |
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135 | { |
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136 | _CPU_Fatal_halt(RTEMS_FATAL_SOURCE_EXCEPTION, 0xECC0); /* source ignored */ |
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137 | } |
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