source: rtems/cpukit/score/cpu/nios2/nios2-iic-irq.c @ 905b656c

4.115
Last change on this file since 905b656c was 905b656c, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 7, 2014 at 7:09:39 PM

nios2-iic-irq.c: Include <rtems/score/interr.h> so it builds

  • Property mode set to 100644
File size: 3.1 KB
Line 
1/**
2 * @file
3 *
4 * @brief NIOS2 Exception and Interrupt Handler
5 *
6 * @note Derived from c4x/irq.c
7 */
8
9/*
10 *  COPYRIGHT (c) 1989-2007.
11 *  On-Line Applications Research Corporation (OAR).
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.rtems.org/license/LICENSE.
16 */
17
18#ifdef HAVE_CONFIG_H
19#include "config.h"
20#endif
21
22#include <rtems/system.h>
23#include <rtems/score/cpu.h>
24#include <rtems/score/isr.h>
25#include <rtems/score/threaddispatch.h>
26#include <rtems/score/nios2-utility.h>
27#include <rtems/score/interr.h>
28
29/*
30 *  This routine provides the RTEMS interrupt management.
31 *
32 *  Upon entry, interrupts are disabled
33 */
34
35#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
36  unsigned long    *_old_stack_ptr;
37#endif
38
39register unsigned long  *stack_ptr __asm__ ("sp");
40
41RTEMS_INLINE_ROUTINE void __IIC_Handler(void)
42{
43  uint32_t active;
44  uint32_t mask;
45  uint32_t vector;
46
47  /*
48   * Obtain from the interrupt controller a bit list of pending interrupts,
49   * and then process the highest priority interrupt. This process loops,
50   * loading the active interrupt list on each pass until ipending
51   * return zero.
52   *
53   * The maximum interrupt latency for the highest priority interrupt is
54   * reduced by finding out which interrupts are pending as late as possible.
55   * Consider the case where the high priority interupt is asserted during
56   * the interrupt entry sequence for a lower priority interrupt to see why
57   * this is the case.
58   */
59
60  active = _Nios2_Get_ctlreg_ipending();
61
62  while (active)
63  {
64    vector = 0;
65    mask = 1;
66
67    /*
68     * Test each bit in turn looking for an active interrupt. Once one is
69     * found call it to clear the interrupt condition.
70     */
71
72    while (active)
73    {
74      if (active & mask)
75      {
76        if ( _ISR_Vector_table[ vector] )
77          (*_ISR_Vector_table[ vector ])(vector);
78        active &= ~mask;
79      }
80      mask <<= 1;
81      ++vector;
82    };
83
84    active = _Nios2_Get_ctlreg_ipending();
85  }
86
87}
88
89void __ISR_Handler(void)
90{
91  register uint32_t level;
92
93  /* Interrupts are disabled upon entry to this Handler */
94
95#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
96  if ( _ISR_Nest_level == 0 ) {
97    /* Install irq stack */
98    _old_stack_ptr = stack_ptr;
99    stack_ptr = _CPU_Interrupt_stack_high - 4;
100  }
101#endif
102
103  _ISR_Nest_level++;
104
105  _Thread_Dispatch_increment_disable_level();
106
107  __IIC_Handler();
108
109  /* Make sure that interrupts are disabled again */
110  _CPU_ISR_Disable( level );
111
112  _Thread_Dispatch_decrement_disable_level();
113
114  _ISR_Nest_level--;
115
116  if( _ISR_Nest_level == 0) {
117#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
118    stack_ptr = _old_stack_ptr;
119#endif
120
121    if( _Thread_Dispatch_is_enabled() )
122    {
123      if ( _Thread_Dispatch_necessary ) {
124        _CPU_ISR_Enable( level );
125        _Thread_Dispatch();
126        /* may have switched to another task and not return here immed. */
127        _CPU_ISR_Disable( level ); /* Keep _pairs_ of Enable/Disable */
128      }
129    }
130  }
131
132  _CPU_ISR_Enable( level );
133}
134
135void __Exception_Handler(CPU_Exception_frame *efr)
136{
137  _CPU_Fatal_halt(RTEMS_FATAL_SOURCE_EXCEPTION, 0xECC0); /* source ignored */
138}
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