| 1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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| 2 | |
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| 3 | /* |
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| 4 | * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved. |
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| 5 | * |
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| 6 | * Redistribution and use in source and binary forms, with or without |
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| 7 | * modification, are permitted provided that the following conditions |
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| 8 | * are met: |
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| 9 | * 1. Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * |
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| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 18 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 19 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 20 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 21 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 22 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 23 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 24 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 25 | * POSSIBILITY OF SUCH DAMAGE. |
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| 26 | */ |
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| 27 | |
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| 28 | #include <rtems/score/percpu.h> |
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| 29 | #include <rtems/score/nios2-utility.h> |
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| 30 | |
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| 31 | #define FRAME_OFFSET_RA 0 |
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| 32 | #define FRAME_OFFSET_AT 4 |
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| 33 | #define FRAME_OFFSET_R2 8 |
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| 34 | #define FRAME_OFFSET_R3 12 |
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| 35 | #define FRAME_OFFSET_R4 16 |
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| 36 | #define FRAME_OFFSET_R5 20 |
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| 37 | #define FRAME_OFFSET_R6 24 |
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| 38 | #define FRAME_OFFSET_R7 28 |
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| 39 | #define FRAME_OFFSET_R8 32 |
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| 40 | #define FRAME_OFFSET_R9 36 |
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| 41 | #define FRAME_OFFSET_R10 40 |
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| 42 | #define FRAME_OFFSET_R11 44 |
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| 43 | #define FRAME_OFFSET_R12 48 |
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| 44 | #define FRAME_OFFSET_R13 52 |
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| 45 | #define FRAME_OFFSET_R14 56 |
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| 46 | #define FRAME_OFFSET_R15 60 |
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| 47 | #define FRAME_OFFSET_STATUS 64 |
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| 48 | #define FRAME_OFFSET_EA 68 |
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| 49 | |
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| 50 | #define FRAME_SIZE (FRAME_OFFSET_EA + 4) |
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| 51 | |
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| 52 | .set noat |
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| 53 | .set nobreak |
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| 54 | .section .text |
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| 55 | |
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| 56 | .extern _Per_CPU_Information |
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| 57 | .extern _Nios2_ISR_Status_interrupts_disabled |
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| 58 | |
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| 59 | .globl _Nios2_ISR_Dispatch_with_shadow_register_set |
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| 60 | |
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| 61 | _Nios2_ISR_Dispatch_with_shadow_register_set: |
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| 62 | |
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| 63 | /* Load thread dispatch disable level */ |
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| 64 | ldw r16, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp) |
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| 65 | |
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| 66 | /* Read status */ |
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| 67 | rdctl r18, status |
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| 68 | |
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| 69 | /* Load high level handler address and argument */ |
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| 70 | ldw r8, 4(et) |
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| 71 | ldw r4, 8(et) |
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| 72 | |
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| 73 | /* Increment and store thread dispatch disable level */ |
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| 74 | addi r17, r16, 1 |
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| 75 | stw r17, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp) |
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| 76 | |
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| 77 | /* |
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| 78 | * Enable higher level interrupts. This is safe since status.RSIE is |
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| 79 | * always 0 and thread dispatching is disabled right above. Higher |
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| 80 | * priority interrupts shall not share shadow register sets with lower |
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| 81 | * priority interrupts. |
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| 82 | */ |
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| 83 | ori r5, r18, 1 |
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| 84 | wrctl status, r5 |
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| 85 | |
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| 86 | /* Call high level handler with argument */ |
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| 87 | callr r8 |
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| 88 | |
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| 89 | /* Load the thread dispatch necessary indicator */ |
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| 90 | ldb r12, %gprel(_Per_CPU_Information + PER_CPU_DISPATCH_NEEDED)(gp) |
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| 91 | |
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| 92 | /* Load the thread dispatch after ISR disable indicator */ |
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| 93 | ldw r13, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp) |
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| 94 | |
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| 95 | /* Fix return address */ |
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| 96 | subi ea, ea, 4 |
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| 97 | |
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| 98 | /* |
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| 99 | * If the current thread dispatch disable level (r17) is one, then |
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| 100 | * negate the thread dispatch necessary indicator, otherwise the value |
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| 101 | * is irrelevant. Or it with the previous thread dispatch disable |
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| 102 | * level value (r16). The r15 which will be used as a status to |
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| 103 | * determine if a thread dispatch is necessary and allowed. |
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| 104 | */ |
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| 105 | xor r12, r17, r12 |
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| 106 | or r15, r12, r16 |
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| 107 | |
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| 108 | /* |
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| 109 | * Get the previous register set from r18. If it is zero, then this is |
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| 110 | * the outermost interrupt. Or it to the thread dispatch status (r15). |
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| 111 | */ |
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| 112 | andhi r12, r18, 0x3f |
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| 113 | or r15, r12, r15 |
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| 114 | |
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| 115 | /* |
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| 116 | * Or the thread dispatch after ISR disable indicator (r13) to the |
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| 117 | * thread dispatch status (r15). |
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| 118 | */ |
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| 119 | or r15, r13, r15 |
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| 120 | |
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| 121 | /* Is a thread dispatch necessary and allowed? */ |
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| 122 | bne r15, zero, no_thread_dispatch |
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| 123 | |
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| 124 | /* Obtain stack frame in normal register set */ |
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| 125 | rdprs r15, sp, -FRAME_SIZE |
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| 126 | |
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| 127 | /* Disable thread dispatch after ISR */ |
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| 128 | stw r17, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp) |
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| 129 | |
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| 130 | /* Save context */ |
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| 131 | stw sstatus, FRAME_OFFSET_STATUS(r15) |
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| 132 | stw ea, FRAME_OFFSET_EA(r15) |
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| 133 | |
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| 134 | /* Set thread dispatch helper address */ |
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| 135 | movhi ea, %hiadj(thread_dispatch_helper) |
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| 136 | addi ea, ea, %lo(thread_dispatch_helper) |
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| 137 | |
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| 138 | /* Update stack pointer in normal register set */ |
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| 139 | wrprs sp, r15 |
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| 140 | |
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| 141 | /* Jump to thread dispatch helper */ |
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| 142 | eret |
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| 143 | |
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| 144 | no_thread_dispatch: |
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| 145 | |
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| 146 | /* Restore the thread dispatch disable level */ |
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| 147 | stw r16, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp) |
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| 148 | |
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| 149 | /* Return to interrupted context */ |
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| 150 | eret |
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| 151 | |
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| 152 | thread_dispatch_helper: |
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| 153 | |
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| 154 | /* This code executes in the context of the interrupted thread */ |
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| 155 | |
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| 156 | /* Save volatile registers */ |
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| 157 | stw ra, FRAME_OFFSET_RA(sp) |
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| 158 | stw at, FRAME_OFFSET_AT(sp) |
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| 159 | stw r2, FRAME_OFFSET_R2(sp) |
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| 160 | stw r3, FRAME_OFFSET_R3(sp) |
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| 161 | stw r4, FRAME_OFFSET_R4(sp) |
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| 162 | stw r5, FRAME_OFFSET_R5(sp) |
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| 163 | stw r6, FRAME_OFFSET_R6(sp) |
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| 164 | stw r7, FRAME_OFFSET_R7(sp) |
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| 165 | stw r8, FRAME_OFFSET_R8(sp) |
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| 166 | stw r9, FRAME_OFFSET_R9(sp) |
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| 167 | stw r10, FRAME_OFFSET_R10(sp) |
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| 168 | stw r11, FRAME_OFFSET_R11(sp) |
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| 169 | stw r12, FRAME_OFFSET_R12(sp) |
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| 170 | stw r13, FRAME_OFFSET_R13(sp) |
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| 171 | stw r14, FRAME_OFFSET_R14(sp) |
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| 172 | stw r15, FRAME_OFFSET_R15(sp) |
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| 173 | |
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| 174 | /* |
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| 175 | * Disable interrupts (1). |
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| 176 | * |
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| 177 | * We have the following invariants: |
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| 178 | * 1. status.RSIE == 0: thread context initialization |
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| 179 | * 2. status.CRS == 0: thread context initialization |
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| 180 | * 3. status.PRS: arbitrary |
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| 181 | * 4. status.IL < interrupt disable IL: else we would not be here |
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| 182 | * 5. status.IH == 0: thread context initialization |
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| 183 | * 6. status.U == 0: thread context initialization |
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| 184 | * 7. status.PIE == 1: thread context initialization |
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| 185 | * Thus we can use a constant to disable interrupts. |
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| 186 | */ |
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| 187 | movi r5, %lo(_Nios2_ISR_Status_interrupts_disabled) |
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| 188 | wrctl status, r5 |
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| 189 | |
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| 190 | do_thread_dispatch: |
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| 191 | |
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| 192 | addi r4, gp, %gprel(_Per_CPU_Information) |
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| 193 | call _Thread_Do_dispatch |
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| 194 | |
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| 195 | /* Restore some volatile registers */ |
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| 196 | ldw ra, FRAME_OFFSET_RA(sp) |
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| 197 | ldw at, FRAME_OFFSET_AT(sp) |
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| 198 | ldw r2, FRAME_OFFSET_R2(sp) |
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| 199 | ldw r3, FRAME_OFFSET_R3(sp) |
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| 200 | ldw r4, FRAME_OFFSET_R4(sp) |
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| 201 | ldw r5, FRAME_OFFSET_R5(sp) |
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| 202 | ldw r6, FRAME_OFFSET_R6(sp) |
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| 203 | ldw r7, FRAME_OFFSET_R7(sp) |
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| 204 | ldw r8, FRAME_OFFSET_R8(sp) |
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| 205 | ldw r9, FRAME_OFFSET_R9(sp) |
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| 206 | ldw r10, FRAME_OFFSET_R10(sp) |
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| 207 | ldw r11, FRAME_OFFSET_R11(sp) |
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| 208 | ldw r12, FRAME_OFFSET_R12(sp) |
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| 209 | |
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| 210 | /* Disable interrupts, see (1) */ |
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| 211 | rdctl r14, status |
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| 212 | movi r15, %lo(_Nios2_ISR_Status_interrupts_disabled) |
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| 213 | wrctl status, r15 |
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| 214 | |
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| 215 | /* Load thread dispatch necessary */ |
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| 216 | ldb r13, %gprel(_Per_CPU_Information + PER_CPU_DISPATCH_NEEDED)(gp) |
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| 217 | |
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| 218 | /* Is thread dispatch necessary? */ |
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| 219 | bne r13, zero, prepare_thread_dispatch |
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| 220 | |
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| 221 | /* Enable thread dispatch after ISR */ |
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| 222 | stw zero, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp) |
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| 223 | |
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| 224 | /* Restore remaining volatile register */ |
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| 225 | ldw r13, FRAME_OFFSET_R13(sp) |
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| 226 | ldw r14, FRAME_OFFSET_R14(sp) |
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| 227 | ldw r15, FRAME_OFFSET_R15(sp) |
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| 228 | |
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| 229 | /* Restore context */ |
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| 230 | ldw et, FRAME_OFFSET_STATUS(sp) |
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| 231 | ldw ea, FRAME_OFFSET_EA(sp) |
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| 232 | |
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| 233 | /* Release stack frame */ |
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| 234 | addi sp, sp, FRAME_SIZE |
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| 235 | |
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| 236 | /* Restore context */ |
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| 237 | wrctl estatus, et |
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| 238 | |
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| 239 | /* Return to interrupted thread */ |
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| 240 | eret |
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| 241 | |
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| 242 | prepare_thread_dispatch: |
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| 243 | |
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| 244 | /* Disable thread dispatching */ |
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| 245 | movi r4, 1 |
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| 246 | stw r4, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp) |
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| 247 | stw r4, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp) |
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| 248 | |
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| 249 | /* Set interrupt level argument for _Thread_Do_dispatch() */ |
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| 250 | mov r5, r15 |
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| 251 | |
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| 252 | br do_thread_dispatch |
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