[9f1412b9] | 1 | /* |
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[99a1f122] | 2 | * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved. |
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[9f1412b9] | 3 | * |
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| 4 | * embedded brains GmbH |
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[99a1f122] | 5 | * Dornierstr. 4 |
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[9f1412b9] | 6 | * 82178 Puchheim |
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| 7 | * Germany |
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| 8 | * <rtems@embedded-brains.de> |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[c499856] | 12 | * http://www.rtems.org/license/LICENSE. |
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[9f1412b9] | 13 | */ |
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| 14 | |
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| 15 | #include <rtems/score/percpu.h> |
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| 16 | #include <rtems/score/nios2-utility.h> |
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| 17 | |
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| 18 | #define FRAME_OFFSET_RA 0 |
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| 19 | #define FRAME_OFFSET_AT 4 |
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| 20 | #define FRAME_OFFSET_R2 8 |
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| 21 | #define FRAME_OFFSET_R3 12 |
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| 22 | #define FRAME_OFFSET_R4 16 |
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| 23 | #define FRAME_OFFSET_R5 20 |
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| 24 | #define FRAME_OFFSET_R6 24 |
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| 25 | #define FRAME_OFFSET_R7 28 |
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| 26 | #define FRAME_OFFSET_R8 32 |
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| 27 | #define FRAME_OFFSET_R9 36 |
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| 28 | #define FRAME_OFFSET_R10 40 |
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| 29 | #define FRAME_OFFSET_R11 44 |
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| 30 | #define FRAME_OFFSET_R12 48 |
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| 31 | #define FRAME_OFFSET_R13 52 |
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| 32 | #define FRAME_OFFSET_R14 56 |
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| 33 | #define FRAME_OFFSET_R15 60 |
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| 34 | #define FRAME_OFFSET_STATUS 64 |
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| 35 | #define FRAME_OFFSET_EA 68 |
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| 36 | |
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| 37 | #define FRAME_SIZE (FRAME_OFFSET_EA + 4) |
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| 38 | |
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| 39 | .set noat |
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[99a1f122] | 40 | .set nobreak |
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[9f1412b9] | 41 | .section .text |
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| 42 | |
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| 43 | .extern _Per_CPU_Information |
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| 44 | .extern _Nios2_ISR_Status_interrupts_disabled |
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| 45 | |
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| 46 | .globl _Nios2_ISR_Dispatch_with_shadow_non_preemptive |
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| 47 | |
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| 48 | _Nios2_ISR_Dispatch_with_shadow_non_preemptive: |
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| 49 | |
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| 50 | /* Load thread dispatch disable level */ |
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[98c95d1] | 51 | ldw r16, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp) |
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[9f1412b9] | 52 | |
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| 53 | /* Load high level handler address and argument */ |
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| 54 | ldw r8, 4(et) |
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| 55 | ldw r4, 8(et) |
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| 56 | |
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| 57 | /* Increment and store thread dispatch disable level */ |
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| 58 | addi r9, r16, 1 |
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[98c95d1] | 59 | stw r9, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp) |
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[9f1412b9] | 60 | |
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| 61 | /* Call high level handler with argument */ |
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| 62 | callr r8 |
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| 63 | |
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| 64 | /* Load thread dispatch necessary */ |
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| 65 | ldb r12, %gprel(_Per_CPU_Information + PER_CPU_DISPATCH_NEEDED)(gp) |
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| 66 | |
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[9165349d] | 67 | /* Load thread dispatch after ISR disable indicator */ |
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| 68 | ldw r13, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp) |
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[9f1412b9] | 69 | |
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[64d2c8ad] | 70 | /* Read status */ |
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| 71 | rdctl r14, status |
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| 72 | |
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[9f1412b9] | 73 | /* Fix return address */ |
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| 74 | subi ea, ea, 4 |
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| 75 | |
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| 76 | /* |
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| 77 | * Restore the thread dispatch disable level. We must do this before |
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| 78 | * we return to the normal register set, because otherwise we have |
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| 79 | * problems if someone deletes or restarts the interrupted thread while |
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| 80 | * we are in the thread dispatch helper. |
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| 81 | */ |
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[98c95d1] | 82 | stw r16, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp) |
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[9f1412b9] | 83 | |
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| 84 | /* Is thread dispatch allowed? */ |
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| 85 | bne r16, zero, no_thread_dispatch |
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| 86 | |
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| 87 | /* Is thread dispatch necessary? */ |
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| 88 | beq r12, zero, no_thread_dispatch |
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| 89 | |
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| 90 | /* Is outermost interrupt? */ |
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[64d2c8ad] | 91 | andhi r14, r14, 0x3f |
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[9f1412b9] | 92 | bne r14, zero, no_thread_dispatch |
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| 93 | |
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[9165349d] | 94 | /* Is thread dispatch after ISR allowed? */ |
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[9f1412b9] | 95 | bne r13, zero, no_thread_dispatch |
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| 96 | |
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| 97 | /* Obtain stack frame in normal register set */ |
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| 98 | rdprs r15, sp, -FRAME_SIZE |
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| 99 | |
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[9165349d] | 100 | /* Disable thread dispatch after ISR */ |
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| 101 | stw r12, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp) |
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[9f1412b9] | 102 | |
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| 103 | /* Save context */ |
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| 104 | stw sstatus, FRAME_OFFSET_STATUS(r15) |
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| 105 | stw ea, FRAME_OFFSET_EA(r15) |
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| 106 | |
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| 107 | /* Set thread dispatch helper address */ |
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| 108 | movhi ea, %hiadj(thread_dispatch_helper) |
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| 109 | addi ea, ea, %lo(thread_dispatch_helper) |
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| 110 | |
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| 111 | /* Update stack pointer in normal register set */ |
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| 112 | wrprs sp, r15 |
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| 113 | |
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| 114 | no_thread_dispatch: |
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| 115 | |
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| 116 | /* |
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| 117 | * Return to thread dispatch helper, interrupted thread or interrupted |
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| 118 | * lower level interrupt service routine. |
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| 119 | */ |
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| 120 | eret |
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| 121 | |
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| 122 | thread_dispatch_helper: |
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| 123 | |
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| 124 | /* This code executes in the context of the interrupted thread */ |
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| 125 | |
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| 126 | /* Save volatile registers */ |
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| 127 | stw ra, FRAME_OFFSET_RA(sp) |
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| 128 | stw at, FRAME_OFFSET_AT(sp) |
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| 129 | stw r2, FRAME_OFFSET_R2(sp) |
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| 130 | stw r3, FRAME_OFFSET_R3(sp) |
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| 131 | stw r4, FRAME_OFFSET_R4(sp) |
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| 132 | stw r5, FRAME_OFFSET_R5(sp) |
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| 133 | stw r6, FRAME_OFFSET_R6(sp) |
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| 134 | stw r7, FRAME_OFFSET_R7(sp) |
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| 135 | stw r8, FRAME_OFFSET_R8(sp) |
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| 136 | stw r9, FRAME_OFFSET_R9(sp) |
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| 137 | stw r10, FRAME_OFFSET_R10(sp) |
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| 138 | stw r11, FRAME_OFFSET_R11(sp) |
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| 139 | stw r12, FRAME_OFFSET_R12(sp) |
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| 140 | stw r13, FRAME_OFFSET_R13(sp) |
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| 141 | stw r14, FRAME_OFFSET_R14(sp) |
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| 142 | stw r15, FRAME_OFFSET_R15(sp) |
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| 143 | |
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| 144 | do_thread_dispatch: |
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| 145 | |
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| 146 | call _Thread_Dispatch |
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| 147 | |
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| 148 | /* Restore some volatile registers */ |
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| 149 | ldw ra, FRAME_OFFSET_RA(sp) |
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| 150 | ldw at, FRAME_OFFSET_AT(sp) |
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| 151 | ldw r2, FRAME_OFFSET_R2(sp) |
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| 152 | ldw r3, FRAME_OFFSET_R3(sp) |
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| 153 | ldw r4, FRAME_OFFSET_R4(sp) |
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| 154 | ldw r5, FRAME_OFFSET_R5(sp) |
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| 155 | ldw r6, FRAME_OFFSET_R6(sp) |
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| 156 | ldw r7, FRAME_OFFSET_R7(sp) |
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| 157 | ldw r8, FRAME_OFFSET_R8(sp) |
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| 158 | ldw r9, FRAME_OFFSET_R9(sp) |
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| 159 | ldw r10, FRAME_OFFSET_R10(sp) |
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| 160 | ldw r11, FRAME_OFFSET_R11(sp) |
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| 161 | ldw r12, FRAME_OFFSET_R12(sp) |
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| 162 | |
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| 163 | /* |
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| 164 | * Disable interrupts. |
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| 165 | * |
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| 166 | * We have the following invariants: |
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| 167 | * 1. status.RSIE == 0: thread context initialization |
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| 168 | * 2. status.CRS == 0: thread context initialization |
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| 169 | * 3. status.PRS: arbitrary |
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| 170 | * 4. status.IL < interrupt disable IL: else we would not be here |
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| 171 | * 5. status.IH == 0: thread context initialization |
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| 172 | * 6. status.U == 0: thread context initialization |
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| 173 | * 7. status.PIE == 1: thread context initialization |
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| 174 | * Thus we can use a constant to disable interrupts. |
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| 175 | */ |
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| 176 | rdctl r14, status |
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| 177 | movi r15, %lo(_Nios2_ISR_Status_interrupts_disabled) |
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| 178 | wrctl status, r15 |
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| 179 | |
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| 180 | /* Load thread dispatch necessary */ |
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[0cce75e] | 181 | ldb r13, %gprel(_Per_CPU_Information + PER_CPU_DISPATCH_NEEDED)(gp) |
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[9f1412b9] | 182 | |
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| 183 | /* Is thread dispatch necessary? */ |
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[0cce75e] | 184 | bne r13, zero, enable_interrupts_before_thread_dispatch |
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[9f1412b9] | 185 | |
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[9165349d] | 186 | /* Enable thread dispatch after ISR */ |
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| 187 | stw zero, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp) |
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[9f1412b9] | 188 | |
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| 189 | /* Restore remaining volatile register */ |
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[0cce75e] | 190 | ldw r13, FRAME_OFFSET_R13(sp) |
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[9f1412b9] | 191 | ldw r14, FRAME_OFFSET_R14(sp) |
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| 192 | ldw r15, FRAME_OFFSET_R15(sp) |
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| 193 | |
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| 194 | /* Restore context */ |
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| 195 | ldw et, FRAME_OFFSET_STATUS(sp) |
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| 196 | ldw ea, FRAME_OFFSET_EA(sp) |
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| 197 | |
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| 198 | /* Release stack frame */ |
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| 199 | addi sp, sp, FRAME_SIZE |
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| 200 | |
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| 201 | /* Restore context */ |
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| 202 | wrctl estatus, et |
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| 203 | |
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| 204 | /* Return to interrupted thread */ |
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| 205 | eret |
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| 206 | |
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| 207 | enable_interrupts_before_thread_dispatch: |
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| 208 | |
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| 209 | /* Restore status */ |
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| 210 | wrctl status, r14 |
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| 211 | |
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| 212 | br do_thread_dispatch |
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