[9f1412b9] | 1 | /* |
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[99a1f122] | 2 | * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved. |
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[9f1412b9] | 3 | * |
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| 4 | * embedded brains GmbH |
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[99a1f122] | 5 | * Dornierstr. 4 |
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[9f1412b9] | 6 | * 82178 Puchheim |
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| 7 | * Germany |
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| 8 | * <rtems@embedded-brains.de> |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[c499856] | 12 | * http://www.rtems.org/license/LICENSE. |
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[9f1412b9] | 13 | */ |
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| 14 | |
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| 15 | #include <rtems/score/percpu.h> |
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| 16 | #include <rtems/score/nios2-utility.h> |
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| 17 | |
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| 18 | #define FRAME_OFFSET_RA 0 |
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| 19 | #define FRAME_OFFSET_AT 4 |
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| 20 | #define FRAME_OFFSET_R2 8 |
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| 21 | #define FRAME_OFFSET_R3 12 |
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| 22 | #define FRAME_OFFSET_R4 16 |
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| 23 | #define FRAME_OFFSET_R5 20 |
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| 24 | #define FRAME_OFFSET_R6 24 |
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| 25 | #define FRAME_OFFSET_R7 28 |
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| 26 | #define FRAME_OFFSET_R8 32 |
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| 27 | #define FRAME_OFFSET_R9 36 |
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| 28 | #define FRAME_OFFSET_R10 40 |
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| 29 | #define FRAME_OFFSET_R11 44 |
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| 30 | #define FRAME_OFFSET_R12 48 |
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| 31 | #define FRAME_OFFSET_R13 52 |
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| 32 | #define FRAME_OFFSET_R14 56 |
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| 33 | #define FRAME_OFFSET_R15 60 |
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| 34 | #define FRAME_OFFSET_STATUS 64 |
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| 35 | #define FRAME_OFFSET_EA 68 |
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| 36 | |
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| 37 | #define FRAME_SIZE (FRAME_OFFSET_EA + 4) |
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| 38 | |
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| 39 | .set noat |
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[99a1f122] | 40 | .set nobreak |
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[9f1412b9] | 41 | .section .text |
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| 42 | |
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| 43 | .extern _Per_CPU_Information |
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| 44 | .extern _Nios2_ISR_Status_interrupts_disabled |
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| 45 | |
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[51e59d5] | 46 | .globl _Nios2_ISR_Dispatch_with_shadow_register_set |
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[9f1412b9] | 47 | |
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[51e59d5] | 48 | _Nios2_ISR_Dispatch_with_shadow_register_set: |
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[9f1412b9] | 49 | |
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| 50 | /* Load thread dispatch disable level */ |
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[98c95d1] | 51 | ldw r16, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp) |
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[9f1412b9] | 52 | |
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[51e59d5] | 53 | /* Read status */ |
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| 54 | rdctl r18, status |
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| 55 | |
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[9f1412b9] | 56 | /* Load high level handler address and argument */ |
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| 57 | ldw r8, 4(et) |
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| 58 | ldw r4, 8(et) |
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| 59 | |
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| 60 | /* Increment and store thread dispatch disable level */ |
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[19acb3b] | 61 | addi r17, r16, 1 |
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| 62 | stw r17, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp) |
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[9f1412b9] | 63 | |
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[51e59d5] | 64 | /* |
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| 65 | * Enable higher level interrupts. This is safe since status.RSIE is |
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| 66 | * always 0 and thread dispatching is disabled right above. Higher |
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| 67 | * priority interrupts shall not share shadow register sets with lower |
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| 68 | * priority interrupts. |
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| 69 | */ |
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| 70 | ori r5, r18, 1 |
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| 71 | wrctl status, r5 |
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| 72 | |
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[9f1412b9] | 73 | /* Call high level handler with argument */ |
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| 74 | callr r8 |
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| 75 | |
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[19acb3b] | 76 | /* Load the thread dispatch necessary indicator */ |
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[9f1412b9] | 77 | ldb r12, %gprel(_Per_CPU_Information + PER_CPU_DISPATCH_NEEDED)(gp) |
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| 78 | |
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[19acb3b] | 79 | /* Load the thread dispatch after ISR disable indicator */ |
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[9165349d] | 80 | ldw r13, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp) |
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[9f1412b9] | 81 | |
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| 82 | /* Fix return address */ |
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| 83 | subi ea, ea, 4 |
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| 84 | |
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| 85 | /* |
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[19acb3b] | 86 | * If the current thread dispatch disable level (r17) is one, then |
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| 87 | * negate the thread dispatch necessary indicator, otherwise the value |
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| 88 | * is irrelevant. Or it with the previous thread dispatch disable |
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| 89 | * level value (r16). The r15 which will be used as a status to |
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| 90 | * determine if a thread dispatch is necessary and allowed. |
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[9f1412b9] | 91 | */ |
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[19acb3b] | 92 | xor r12, r17, r12 |
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| 93 | or r15, r12, r16 |
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[9f1412b9] | 94 | |
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[19acb3b] | 95 | /* |
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[51e59d5] | 96 | * Get the previous register set from r18. If it is zero, then this is |
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[19acb3b] | 97 | * the outermost interrupt. Or it to the thread dispatch status (r15). |
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| 98 | */ |
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[51e59d5] | 99 | andhi r12, r18, 0x3f |
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[19acb3b] | 100 | or r15, r12, r15 |
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[9f1412b9] | 101 | |
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[19acb3b] | 102 | /* |
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| 103 | * Or the thread dispatch after ISR disable indicator (r13) to the |
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| 104 | * thread dispatch status (r15). |
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| 105 | */ |
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| 106 | or r15, r13, r15 |
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[9f1412b9] | 107 | |
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[19acb3b] | 108 | /* Is a thread dispatch necessary and allowed? */ |
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| 109 | bne r15, zero, no_thread_dispatch |
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[9f1412b9] | 110 | |
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| 111 | /* Obtain stack frame in normal register set */ |
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| 112 | rdprs r15, sp, -FRAME_SIZE |
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| 113 | |
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[9165349d] | 114 | /* Disable thread dispatch after ISR */ |
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[19acb3b] | 115 | stw r17, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp) |
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[9f1412b9] | 116 | |
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| 117 | /* Save context */ |
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| 118 | stw sstatus, FRAME_OFFSET_STATUS(r15) |
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| 119 | stw ea, FRAME_OFFSET_EA(r15) |
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| 120 | |
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| 121 | /* Set thread dispatch helper address */ |
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| 122 | movhi ea, %hiadj(thread_dispatch_helper) |
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| 123 | addi ea, ea, %lo(thread_dispatch_helper) |
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| 124 | |
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| 125 | /* Update stack pointer in normal register set */ |
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| 126 | wrprs sp, r15 |
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| 127 | |
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[19acb3b] | 128 | /* Jump to thread dispatch helper */ |
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| 129 | eret |
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| 130 | |
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[9f1412b9] | 131 | no_thread_dispatch: |
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| 132 | |
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[19acb3b] | 133 | /* Restore the thread dispatch disable level */ |
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| 134 | stw r16, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp) |
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| 135 | |
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| 136 | /* Return to interrupted context */ |
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[9f1412b9] | 137 | eret |
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| 138 | |
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| 139 | thread_dispatch_helper: |
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| 140 | |
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| 141 | /* This code executes in the context of the interrupted thread */ |
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| 142 | |
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| 143 | /* Save volatile registers */ |
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| 144 | stw ra, FRAME_OFFSET_RA(sp) |
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| 145 | stw at, FRAME_OFFSET_AT(sp) |
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| 146 | stw r2, FRAME_OFFSET_R2(sp) |
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| 147 | stw r3, FRAME_OFFSET_R3(sp) |
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| 148 | stw r4, FRAME_OFFSET_R4(sp) |
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| 149 | stw r5, FRAME_OFFSET_R5(sp) |
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| 150 | stw r6, FRAME_OFFSET_R6(sp) |
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| 151 | stw r7, FRAME_OFFSET_R7(sp) |
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| 152 | stw r8, FRAME_OFFSET_R8(sp) |
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| 153 | stw r9, FRAME_OFFSET_R9(sp) |
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| 154 | stw r10, FRAME_OFFSET_R10(sp) |
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| 155 | stw r11, FRAME_OFFSET_R11(sp) |
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| 156 | stw r12, FRAME_OFFSET_R12(sp) |
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| 157 | stw r13, FRAME_OFFSET_R13(sp) |
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| 158 | stw r14, FRAME_OFFSET_R14(sp) |
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| 159 | stw r15, FRAME_OFFSET_R15(sp) |
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| 160 | |
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[19acb3b] | 161 | /* |
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| 162 | * Disable interrupts (1). |
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| 163 | * |
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| 164 | * We have the following invariants: |
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| 165 | * 1. status.RSIE == 0: thread context initialization |
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| 166 | * 2. status.CRS == 0: thread context initialization |
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| 167 | * 3. status.PRS: arbitrary |
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| 168 | * 4. status.IL < interrupt disable IL: else we would not be here |
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| 169 | * 5. status.IH == 0: thread context initialization |
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| 170 | * 6. status.U == 0: thread context initialization |
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| 171 | * 7. status.PIE == 1: thread context initialization |
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| 172 | * Thus we can use a constant to disable interrupts. |
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| 173 | */ |
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| 174 | movi r5, %lo(_Nios2_ISR_Status_interrupts_disabled) |
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| 175 | wrctl status, r5 |
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| 176 | |
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[9f1412b9] | 177 | do_thread_dispatch: |
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| 178 | |
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[19acb3b] | 179 | addi r4, gp, %gprel(_Per_CPU_Information) |
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| 180 | call _Thread_Do_dispatch |
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[9f1412b9] | 181 | |
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| 182 | /* Restore some volatile registers */ |
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| 183 | ldw ra, FRAME_OFFSET_RA(sp) |
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| 184 | ldw at, FRAME_OFFSET_AT(sp) |
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| 185 | ldw r2, FRAME_OFFSET_R2(sp) |
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| 186 | ldw r3, FRAME_OFFSET_R3(sp) |
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| 187 | ldw r4, FRAME_OFFSET_R4(sp) |
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| 188 | ldw r5, FRAME_OFFSET_R5(sp) |
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| 189 | ldw r6, FRAME_OFFSET_R6(sp) |
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| 190 | ldw r7, FRAME_OFFSET_R7(sp) |
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| 191 | ldw r8, FRAME_OFFSET_R8(sp) |
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| 192 | ldw r9, FRAME_OFFSET_R9(sp) |
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| 193 | ldw r10, FRAME_OFFSET_R10(sp) |
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| 194 | ldw r11, FRAME_OFFSET_R11(sp) |
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| 195 | ldw r12, FRAME_OFFSET_R12(sp) |
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| 196 | |
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[19acb3b] | 197 | /* Disable interrupts, see (1) */ |
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[9f1412b9] | 198 | rdctl r14, status |
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| 199 | movi r15, %lo(_Nios2_ISR_Status_interrupts_disabled) |
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| 200 | wrctl status, r15 |
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| 201 | |
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| 202 | /* Load thread dispatch necessary */ |
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[0cce75e] | 203 | ldb r13, %gprel(_Per_CPU_Information + PER_CPU_DISPATCH_NEEDED)(gp) |
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[9f1412b9] | 204 | |
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| 205 | /* Is thread dispatch necessary? */ |
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[19acb3b] | 206 | bne r13, zero, prepare_thread_dispatch |
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[9f1412b9] | 207 | |
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[9165349d] | 208 | /* Enable thread dispatch after ISR */ |
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| 209 | stw zero, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp) |
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[9f1412b9] | 210 | |
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| 211 | /* Restore remaining volatile register */ |
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[0cce75e] | 212 | ldw r13, FRAME_OFFSET_R13(sp) |
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[9f1412b9] | 213 | ldw r14, FRAME_OFFSET_R14(sp) |
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| 214 | ldw r15, FRAME_OFFSET_R15(sp) |
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| 215 | |
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| 216 | /* Restore context */ |
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| 217 | ldw et, FRAME_OFFSET_STATUS(sp) |
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| 218 | ldw ea, FRAME_OFFSET_EA(sp) |
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| 219 | |
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| 220 | /* Release stack frame */ |
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| 221 | addi sp, sp, FRAME_SIZE |
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| 222 | |
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| 223 | /* Restore context */ |
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| 224 | wrctl estatus, et |
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| 225 | |
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| 226 | /* Return to interrupted thread */ |
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| 227 | eret |
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| 228 | |
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[19acb3b] | 229 | prepare_thread_dispatch: |
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| 230 | |
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| 231 | /* Disable thread dispatching */ |
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| 232 | movi r4, 1 |
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| 233 | stw r4, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp) |
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| 234 | stw r4, %gprel(_Per_CPU_Information + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)(gp) |
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[9f1412b9] | 235 | |
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[19acb3b] | 236 | /* Set interrupt level argument for _Thread_Do_dispatch() */ |
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| 237 | mov r5, r15 |
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[9f1412b9] | 238 | |
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| 239 | br do_thread_dispatch |
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