source: rtems/cpukit/score/cpu/nios2/irq.c @ 7a28ac8

4.104.11
Last change on this file since 7a28ac8 was 7a28ac8, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 10, 2008 at 3:41:37 PM

2008-09-10 Joel Sherrill <joel.sherrill@…>

  • configure.ac, aclocal/canonical-target-name.m4: Readd NIOS2 and TI C4x. Accidentally not done on 4.9 branch. :(
  • score/cpu/c4x/.cvsignore, score/cpu/c4x/ChangeLog, score/cpu/c4x/Makefile.am, score/cpu/c4x/cpu.c, score/cpu/c4x/cpu_asm.S, score/cpu/c4x/irq.c, score/cpu/c4x/preinstall.am, score/cpu/c4x/rtems/asm.h, score/cpu/c4x/rtems/score/c4x.h, score/cpu/c4x/rtems/score/cpu.h, score/cpu/c4x/rtems/score/cpu_asm.h, score/cpu/c4x/rtems/score/types.h, score/cpu/c4x/rtems/tic4x/c4xio.h, score/cpu/nios2/.cvsignore, score/cpu/nios2/ChangeLog, score/cpu/nios2/Makefile.am, score/cpu/nios2/cpu.c, score/cpu/nios2/cpu_asm.S, score/cpu/nios2/irq.c, score/cpu/nios2/preinstall.am, score/cpu/nios2/rtems/asm.h, score/cpu/nios2/rtems/score/cpu.h, score/cpu/nios2/rtems/score/cpu_asm.h, score/cpu/nios2/rtems/score/nios2.h, score/cpu/nios2/rtems/score/types.h: New files.
  • Property mode set to 100644
File size: 2.0 KB
Line 
1/*
2 *  NIOS2 exception and interrupt handler
3 *
4 *  Derived from c4x/irq.c
5 *
6 *  COPYRIGHT (c) 1989-2007.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.com/license/LICENSE.
12 *
13 *  $Id$
14 */
15
16#include <rtems/system.h>
17#include <rtems/score/cpu.h>
18#include <rtems/score/isr.h>
19#include <rtems/score/thread.h>
20
21/*
22 *  This routine provides the RTEMS interrupt management.
23 *
24 *  Upon entry, interrupts are disabled
25 */
26
27#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
28  unsigned long    *_old_stack_ptr;
29#endif
30
31register unsigned long  *stack_ptr asm("sp");
32
33void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr)
34{
35  register uint32_t   level;
36
37  /* Interrupts are disabled upon entry to this Handler */
38
39#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
40  if ( _ISR_Nest_level == 0 ) {
41    /* Install irq stack */
42    _old_stack_ptr = stack_ptr;
43    stack_ptr = _CPU_Interrupt_stack_high - 4;
44  }
45#endif
46
47  _ISR_Nest_level++;
48
49  _Thread_Dispatch_disable_level++;
50
51  if ( _ISR_Vector_table[ vector] )
52  {
53    (*_ISR_Vector_table[ vector ])(vector, ifr);
54  };
55
56  /* Make sure that interrupts are disabled again */
57  _CPU_ISR_Disable( level );
58
59  _Thread_Dispatch_disable_level--;
60
61  _ISR_Nest_level--;
62
63  if( _ISR_Nest_level == 0)
64  {
65#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
66    stack_ptr = _old_stack_ptr;
67#endif
68
69    if( _Thread_Dispatch_disable_level == 0 )
70    {
71      if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing )
72      {
73        _ISR_Signals_to_thread_executing = FALSE;
74        _CPU_ISR_Enable( level );
75        _Thread_Dispatch();
76        /* may have switched to another task and not return here immed. */
77        _CPU_ISR_Disable( level ); /* Keep _pairs_ of Enable/Disable */
78      }
79    }
80    else
81    {
82      _ISR_Signals_to_thread_executing = FALSE;
83    };
84  };
85
86  _CPU_ISR_Enable( level );
87}
88
89void __Exception_Handler(CPU_Exception_frame *efr)
90{
91  _CPU_Fatal_halt(0xECC0);
92}
93
94
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