source: rtems/cpukit/score/cpu/nios2/irq.c @ 5632f8d

4.104.11
Last change on this file since 5632f8d was 5632f8d, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 27, 2010 at 3:02:21 PM

2010-03-27 Joel Sherrill <joel.sherrill@…>

  • cpu.c, cpu_asm.S, irq.c: Add include of config.h
  • Property mode set to 100644
File size: 2.1 KB
Line 
1/*
2 *  NIOS2 exception and interrupt handler
3 *
4 *  Derived from c4x/irq.c
5 *
6 *  COPYRIGHT (c) 1989-2007.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.com/license/LICENSE.
12 *
13 *  $Id$
14 */
15
16#ifdef HAVE_CONFIG_H
17#include "config.h"
18#endif
19
20#include <rtems/system.h>
21#include <rtems/score/cpu.h>
22#include <rtems/score/isr.h>
23#include <rtems/score/thread.h>
24
25/*
26 *  This routine provides the RTEMS interrupt management.
27 *
28 *  Upon entry, interrupts are disabled
29 */
30
31#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
32  unsigned long    *_old_stack_ptr;
33#endif
34
35register unsigned long  *stack_ptr asm("sp");
36
37void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr)
38{
39  register uint32_t   level;
40
41  /* Interrupts are disabled upon entry to this Handler */
42
43#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
44  if ( _ISR_Nest_level == 0 ) {
45    /* Install irq stack */
46    _old_stack_ptr = stack_ptr;
47    stack_ptr = _CPU_Interrupt_stack_high - 4;
48  }
49#endif
50
51  _ISR_Nest_level++;
52
53  _Thread_Dispatch_disable_level++;
54
55  if ( _ISR_Vector_table[ vector] )
56  {
57    (*_ISR_Vector_table[ vector ])(vector, ifr);
58  };
59
60  /* Make sure that interrupts are disabled again */
61  _CPU_ISR_Disable( level );
62
63  _Thread_Dispatch_disable_level--;
64
65  _ISR_Nest_level--;
66
67  if( _ISR_Nest_level == 0)
68  {
69#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
70    stack_ptr = _old_stack_ptr;
71#endif
72
73    if( _Thread_Dispatch_disable_level == 0 )
74    {
75      if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing )
76      {
77        _ISR_Signals_to_thread_executing = FALSE;
78        _CPU_ISR_Enable( level );
79        _Thread_Dispatch();
80        /* may have switched to another task and not return here immed. */
81        _CPU_ISR_Disable( level ); /* Keep _pairs_ of Enable/Disable */
82      }
83    }
84    else
85    {
86      _ISR_Signals_to_thread_executing = FALSE;
87    };
88  };
89
90  _CPU_ISR_Enable( level );
91}
92
93void __Exception_Handler(CPU_Exception_frame *efr)
94{
95  _CPU_Fatal_halt(0xECC0);
96}
97
98
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