source: rtems/cpukit/score/cpu/nios2/include/rtems/score/cpu.h @ d7a48e1

Last change on this file since d7a48e1 was d7a48e1, checked in by Sebastian Huber <sebastian.huber@…>, on Oct 6, 2020 at 5:39:44 AM

rtems: Improve RTEMS_NO_RETURN attribute

Provide RTEMS_NO_RETURN also in case RTEMS_DEBUG is defined to prevent errors
like this:

error: no return statement in function returning non-void [-Werror=return-type]

Use C11 and C++11 standard means to declare a no-return function.

Close #4122.

  • Property mode set to 100644
File size: 9.3 KB
Line 
1/**
2 * @file
3 *
4 * @addtogroup RTEMSScoreCPUnios2
5 *
6 * @brief Altera Nios II CPU Department Source
7 */
8
9/*
10 *  Copyright (c) 2011 embedded brains GmbH
11 *
12 *  Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
13 *
14 *  COPYRIGHT (c) 1989-2004.
15 *  On-Line Applications Research Corporation (OAR).
16 *
17 *  The license and distribution terms for this file may be
18 *  found in the file LICENSE in this distribution or at
19 *  http://www.rtems.org/license/LICENSE.
20 */
21
22#ifndef _RTEMS_SCORE_CPU_H
23#define _RTEMS_SCORE_CPU_H
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <rtems/score/basedefs.h>
30#include <rtems/score/nios2.h>
31
32#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
33
34#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
35
36#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
37
38#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
39
40#define CPU_ISR_PASSES_FRAME_POINTER FALSE
41
42#define CPU_HARDWARE_FP FALSE
43
44#define CPU_SOFTWARE_FP FALSE
45
46#define CPU_ALL_TASKS_ARE_FP FALSE
47
48#define CPU_IDLE_TASK_IS_FP FALSE
49
50#define CPU_USE_DEFERRED_FP_SWITCH FALSE
51
52#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
53
54#define CPU_STACK_GROWS_UP FALSE
55
56/* FIXME: Is this the right value? */
57#define CPU_CACHE_LINE_BYTES 32
58
59#define CPU_STRUCTURE_ALIGNMENT \
60  RTEMS_SECTION( ".sdata" ) RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
61
62#define CPU_STACK_MINIMUM_SIZE (4 * 1024)
63
64#define CPU_SIZEOF_POINTER 4
65
66/*
67 * Alignment value according to "Nios II Processor Reference" chapter 7
68 * "Application Binary Interface" section "Memory Alignment".
69 */
70#define CPU_ALIGNMENT 4
71
72#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
73
74/*
75 * Alignment value according to "Nios II Processor Reference" chapter 7
76 * "Application Binary Interface" section "Stacks".
77 */
78#define CPU_STACK_ALIGNMENT 4
79
80#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
81
82/*
83 * A Nios II configuration with an external interrupt controller (EIC) supports
84 * up to 64 interrupt levels.  A Nios II configuration with an internal
85 * interrupt controller (IIC) has only two interrupt levels (enabled and
86 * disabled).  The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will
87 * take care about configuration specific mappings.
88 */
89#define CPU_MODES_INTERRUPT_MASK 0x3f
90
91#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
92
93#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
94
95#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
96
97#define CPU_MAXIMUM_PROCESSORS 32
98
99#ifndef ASM
100
101/**
102 * @brief Thread register context.
103 *
104 * The thread register context covers the non-volatile registers, the thread
105 * stack pointer, the return address, and the processor status.
106 *
107 * There is no need to save the global pointer (gp) since it is a system wide
108 * constant and set-up with the C runtime environment.
109 *
110 * The @a thread_dispatch_disabled field is used for the external interrupt
111 * controller (EIC) support.
112 *
113 * @see _Nios2_Thread_dispatch_disabled
114 */
115typedef struct {
116  uint32_t r16;
117  uint32_t r17;
118  uint32_t r18;
119  uint32_t r19;
120  uint32_t r20;
121  uint32_t r21;
122  uint32_t r22;
123  uint32_t r23;
124  uint32_t fp;
125  uint32_t status;
126  uint32_t sp;
127  uint32_t ra;
128  uint32_t thread_dispatch_disabled;
129  uint32_t stack_mpubase;
130  uint32_t stack_mpuacc;
131} Context_Control;
132
133#define _CPU_Context_Get_SP( _context ) \
134  (_context)->sp
135
136typedef void CPU_Interrupt_frame;
137
138typedef struct {
139  uint32_t r1;
140  uint32_t r2;
141  uint32_t r3;
142  uint32_t r4;
143  uint32_t r5;
144  uint32_t r6;
145  uint32_t r7;
146  uint32_t r8;
147  uint32_t r9;
148  uint32_t r10;
149  uint32_t r11;
150  uint32_t r12;
151  uint32_t r13;
152  uint32_t r14;
153  uint32_t r15;
154  uint32_t r16;
155  uint32_t r17;
156  uint32_t r18;
157  uint32_t r19;
158  uint32_t r20;
159  uint32_t r21;
160  uint32_t r22;
161  uint32_t r23;
162  uint32_t gp;
163  uint32_t fp;
164  uint32_t sp;
165  uint32_t ra;
166  uint32_t et;
167  uint32_t ea;
168  uint32_t status;
169  uint32_t ienable;
170  uint32_t ipending;
171} CPU_Exception_frame;
172
173#define _CPU_Initialize_vectors()
174
175/**
176 * @brief Macro to disable interrupts.
177 *
178 * The processor status before disabling the interrupts will be stored in
179 * @a _isr_cookie.  This value will be used in _CPU_ISR_Flash() and
180 * _CPU_ISR_Enable().
181 *
182 * The global symbol _Nios2_ISR_Status_mask will be used to clear the bits in
183 * the status register representing the interrupt level.  The global symbol
184 * _Nios2_ISR_Status_bits will be used to set the bits representing an
185 * interrupt level that disables interrupts.  Both global symbols must be
186 * provided by the board support package.
187 *
188 * In case the Nios II uses the internal interrupt controller (IIC), then only
189 * the PIE status bit is used.
190 *
191 * In case the Nios II uses the external interrupt controller (EIC), then the
192 * RSIE status bit or the IL status field is used depending on the interrupt
193 * handling variant and the shadow register usage.
194 */
195#define _CPU_ISR_Disable( _isr_cookie ) \
196  do { \
197    int _tmp; \
198    __asm__ volatile ( \
199      "rdctl %0, status\n" \
200      "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \
201      "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \
202      "and %1, %0, %1\n" \
203      "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \
204      "wrctl status, %1" \
205      : "=&r" (_isr_cookie), "=&r" (_tmp) \
206    ); \
207  } while ( 0 )
208
209/**
210 * @brief Macro to restore the processor status.
211 *
212 * The @a _isr_cookie must contain the processor status returned by
213 * _CPU_ISR_Disable().  The value is not modified.
214 */
215#define _CPU_ISR_Enable( _isr_cookie ) \
216  __builtin_wrctl( 0, (int) _isr_cookie )
217
218/**
219 * @brief Macro to restore the processor status and disable the interrupts
220 * again.
221 *
222 * The @a _isr_cookie must contain the processor status returned by
223 * _CPU_ISR_Disable().  The value is not modified.
224 *
225 * This flash code is optimal for all Nios II configurations.  The rdctl does
226 * not flush the pipeline and has only a late result penalty.  The wrctl on
227 * the other hand leads to a pipeline flush.
228 */
229#define _CPU_ISR_Flash( _isr_cookie ) \
230  do { \
231    int _status = __builtin_rdctl( 0 ); \
232    __builtin_wrctl( 0, (int) _isr_cookie ); \
233    __builtin_wrctl( 0, _status ); \
234  } while ( 0 )
235
236bool _CPU_ISR_Is_enabled( uint32_t level );
237
238/**
239 * @brief Sets the interrupt level for the executing thread.
240 *
241 * The valid values of @a new_level depend on the Nios II configuration.  A
242 * value of zero represents enabled interrupts in all configurations.
243 *
244 * @see _CPU_ISR_Get_level()
245 */
246void _CPU_ISR_Set_level( uint32_t new_level );
247
248/**
249 * @brief Returns the interrupt level of the executing thread.
250 *
251 * @retval 0 Interrupts are enabled.
252 * @retval otherwise The value depends on the Nios II configuration.  In case
253 * of an internal interrupt controller (IIC) the only valid value is one which
254 * indicates disabled interrupts.  In case of an external interrupt controller
255 * (EIC) there are two possibilities.  Firstly if the RSIE status bit is used
256 * to disable interrupts, then one is the only valid value indicating disabled
257 * interrupts.  Secondly if the IL status field is used to disable interrupts,
258 * then this value will be returned.  Interrupts are disabled at the maximum
259 * level specified by the _Nios2_ISR_Status_bits.
260 */
261uint32_t _CPU_ISR_Get_level( void );
262
263/**
264 * @brief Initializes the CPU context.
265 *
266 * The following steps are performed:
267 *  - setting a starting address
268 *  - preparing the stack
269 *  - preparing the stack and frame pointers
270 *  - setting the proper interrupt level in the context
271 *
272 * @param[in] context points to the context area
273 * @param[in] stack_area_begin is the low address of the allocated stack area
274 * @param[in] stack_area_size is the size of the stack area in bytes
275 * @param[in] new_level is the interrupt level for the task
276 * @param[in] entry_point is the task's entry point
277 * @param[in] is_fp is set to @c true if the task is a floating point task
278 * @param[in] tls_area is the thread-local storage (TLS) area
279 */
280void _CPU_Context_Initialize(
281  Context_Control *context,
282  void *stack_area_begin,
283  size_t stack_area_size,
284  uint32_t new_level,
285  void (*entry_point)( void ),
286  bool is_fp,
287  void *tls_area
288);
289
290#define _CPU_Context_Restart_self( _the_context ) \
291  _CPU_Context_restore( (_the_context) );
292
293RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t _source, uint32_t _error );
294
295/**
296 * @brief CPU initialization.
297 */
298void _CPU_Initialize( void );
299
300typedef void ( *CPU_ISR_handler )( uint32_t );
301
302void _CPU_ISR_install_vector(
303  uint32_t         vector,
304  CPU_ISR_handler  new_handler,
305  CPU_ISR_handler *old_handler
306);
307
308void *_CPU_Thread_Idle_body( uintptr_t ignored );
309
310void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
311
312RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context );
313
314void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
315
316static inline uint32_t CPU_swap_u32( uint32_t value )
317{
318  uint32_t byte1, byte2, byte3, byte4, swapped;
319
320  byte4 = (value >> 24) & 0xff;
321  byte3 = (value >> 16) & 0xff;
322  byte2 = (value >> 8)  & 0xff;
323  byte1 =  value        & 0xff;
324
325  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
326
327  return swapped;
328}
329
330#define CPU_swap_u16( value ) \
331  (((value&0xff) << 8) | ((value >> 8)&0xff))
332
333typedef uint32_t CPU_Counter_ticks;
334
335uint32_t _CPU_Counter_frequency( void );
336
337CPU_Counter_ticks _CPU_Counter_read( void );
338
339static inline CPU_Counter_ticks _CPU_Counter_difference(
340  CPU_Counter_ticks second,
341  CPU_Counter_ticks first
342)
343{
344  return second - first;
345}
346
347/** Type that can store a 32-bit integer or a pointer. */
348typedef uintptr_t CPU_Uint32ptr;
349
350#endif /* ASM */
351
352#ifdef __cplusplus
353}
354#endif
355
356#endif
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