source: rtems/cpukit/score/cpu/nios2/include/rtems/score/cpu.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 9.5 KB
Line 
1/**
2 * @file
3 *
4 * @brief Altera Nios II CPU Department Source
5 */
6
7/*
8 *  Copyright (c) 2011 embedded brains GmbH
9 *
10 *  Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
11 *
12 *  COPYRIGHT (c) 1989-2004.
13 *  On-Line Applications Research Corporation (OAR).
14 *
15 *  The license and distribution terms for this file may be
16 *  found in the file LICENSE in this distribution or at
17 *  http://www.rtems.org/license/LICENSE.
18 */
19
20#ifndef _RTEMS_SCORE_CPU_H
21#define _RTEMS_SCORE_CPU_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#include <rtems/score/types.h>
28#include <rtems/score/nios2.h>
29
30#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
31
32#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
33
34#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
35
36#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
37
38#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
39
40#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
41
42#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
43
44#define CPU_ISR_PASSES_FRAME_POINTER FALSE
45
46#define CPU_HARDWARE_FP FALSE
47
48#define CPU_SOFTWARE_FP FALSE
49
50#define CPU_CONTEXT_FP_SIZE 0
51
52#define CPU_ALL_TASKS_ARE_FP FALSE
53
54#define CPU_IDLE_TASK_IS_FP FALSE
55
56#define CPU_USE_DEFERRED_FP_SWITCH FALSE
57
58#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
59
60#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
61
62#define CPU_STACK_GROWS_UP FALSE
63
64/* FIXME: Is this the right value? */
65#define CPU_CACHE_LINE_BYTES 32
66
67#define CPU_STRUCTURE_ALIGNMENT \
68  RTEMS_SECTION( ".sdata" ) RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
69
70#define CPU_STACK_MINIMUM_SIZE (4 * 1024)
71
72#define CPU_SIZEOF_POINTER 4
73
74/*
75 * Alignment value according to "Nios II Processor Reference" chapter 7
76 * "Application Binary Interface" section "Memory Alignment".
77 */
78#define CPU_ALIGNMENT 4
79
80#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
81
82#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
83
84/*
85 * Alignment value according to "Nios II Processor Reference" chapter 7
86 * "Application Binary Interface" section "Stacks".
87 */
88#define CPU_STACK_ALIGNMENT 4
89
90/*
91 * A Nios II configuration with an external interrupt controller (EIC) supports
92 * up to 64 interrupt levels.  A Nios II configuration with an internal
93 * interrupt controller (IIC) has only two interrupt levels (enabled and
94 * disabled).  The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will
95 * take care about configuration specific mappings.
96 */
97#define CPU_MODES_INTERRUPT_MASK 0x3f
98
99#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
100
101#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
102
103#define CPU_MAXIMUM_PROCESSORS 32
104
105#ifndef ASM
106
107/**
108 * @brief Thread register context.
109 *
110 * The thread register context covers the non-volatile registers, the thread
111 * stack pointer, the return address, and the processor status.
112 *
113 * There is no need to save the global pointer (gp) since it is a system wide
114 * constant and set-up with the C runtime environment.
115 *
116 * The @a thread_dispatch_disabled field is used for the external interrupt
117 * controller (EIC) support.
118 *
119 * @see _Nios2_Thread_dispatch_disabled
120 */
121typedef struct {
122  uint32_t r16;
123  uint32_t r17;
124  uint32_t r18;
125  uint32_t r19;
126  uint32_t r20;
127  uint32_t r21;
128  uint32_t r22;
129  uint32_t r23;
130  uint32_t fp;
131  uint32_t status;
132  uint32_t sp;
133  uint32_t ra;
134  uint32_t thread_dispatch_disabled;
135  uint32_t stack_mpubase;
136  uint32_t stack_mpuacc;
137} Context_Control;
138
139#define _CPU_Context_Get_SP( _context ) \
140  (_context)->sp
141
142typedef void CPU_Interrupt_frame;
143
144typedef struct {
145  uint32_t r1;
146  uint32_t r2;
147  uint32_t r3;
148  uint32_t r4;
149  uint32_t r5;
150  uint32_t r6;
151  uint32_t r7;
152  uint32_t r8;
153  uint32_t r9;
154  uint32_t r10;
155  uint32_t r11;
156  uint32_t r12;
157  uint32_t r13;
158  uint32_t r14;
159  uint32_t r15;
160  uint32_t r16;
161  uint32_t r17;
162  uint32_t r18;
163  uint32_t r19;
164  uint32_t r20;
165  uint32_t r21;
166  uint32_t r22;
167  uint32_t r23;
168  uint32_t gp;
169  uint32_t fp;
170  uint32_t sp;
171  uint32_t ra;
172  uint32_t et;
173  uint32_t ea;
174  uint32_t status;
175  uint32_t ienable;
176  uint32_t ipending;
177} CPU_Exception_frame;
178
179#define _CPU_Initialize_vectors()
180
181/**
182 * @brief Macro to disable interrupts.
183 *
184 * The processor status before disabling the interrupts will be stored in
185 * @a _isr_cookie.  This value will be used in _CPU_ISR_Flash() and
186 * _CPU_ISR_Enable().
187 *
188 * The global symbol _Nios2_ISR_Status_mask will be used to clear the bits in
189 * the status register representing the interrupt level.  The global symbol
190 * _Nios2_ISR_Status_bits will be used to set the bits representing an
191 * interrupt level that disables interrupts.  Both global symbols must be
192 * provided by the board support package.
193 *
194 * In case the Nios II uses the internal interrupt controller (IIC), then only
195 * the PIE status bit is used.
196 *
197 * In case the Nios II uses the external interrupt controller (EIC), then the
198 * RSIE status bit or the IL status field is used depending on the interrupt
199 * handling variant and the shadow register usage.
200 */
201#define _CPU_ISR_Disable( _isr_cookie ) \
202  do { \
203    int _tmp; \
204    __asm__ volatile ( \
205      "rdctl %0, status\n" \
206      "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \
207      "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \
208      "and %1, %0, %1\n" \
209      "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \
210      "wrctl status, %1" \
211      : "=&r" (_isr_cookie), "=&r" (_tmp) \
212    ); \
213  } while ( 0 )
214
215/**
216 * @brief Macro to restore the processor status.
217 *
218 * The @a _isr_cookie must contain the processor status returned by
219 * _CPU_ISR_Disable().  The value is not modified.
220 */
221#define _CPU_ISR_Enable( _isr_cookie ) \
222  __builtin_wrctl( 0, (int) _isr_cookie )
223
224/**
225 * @brief Macro to restore the processor status and disable the interrupts
226 * again.
227 *
228 * The @a _isr_cookie must contain the processor status returned by
229 * _CPU_ISR_Disable().  The value is not modified.
230 *
231 * This flash code is optimal for all Nios II configurations.  The rdctl does
232 * not flush the pipeline and has only a late result penalty.  The wrctl on
233 * the other hand leads to a pipeline flush.
234 */
235#define _CPU_ISR_Flash( _isr_cookie ) \
236  do { \
237    int _status = __builtin_rdctl( 0 ); \
238    __builtin_wrctl( 0, (int) _isr_cookie ); \
239    __builtin_wrctl( 0, _status ); \
240  } while ( 0 )
241
242bool _CPU_ISR_Is_enabled( uint32_t level );
243
244/**
245 * @brief Sets the interrupt level for the executing thread.
246 *
247 * The valid values of @a new_level depend on the Nios II configuration.  A
248 * value of zero represents enabled interrupts in all configurations.
249 *
250 * @see _CPU_ISR_Get_level()
251 */
252void _CPU_ISR_Set_level( uint32_t new_level );
253
254/**
255 * @brief Returns the interrupt level of the executing thread.
256 *
257 * @retval 0 Interrupts are enabled.
258 * @retval otherwise The value depends on the Nios II configuration.  In case
259 * of an internal interrupt controller (IIC) the only valid value is one which
260 * indicates disabled interrupts.  In case of an external interrupt controller
261 * (EIC) there are two possibilities.  Firstly if the RSIE status bit is used
262 * to disable interrupts, then one is the only valid value indicating disabled
263 * interrupts.  Secondly if the IL status field is used to disable interrupts,
264 * then this value will be returned.  Interrupts are disabled at the maximum
265 * level specified by the _Nios2_ISR_Status_bits.
266 */
267uint32_t _CPU_ISR_Get_level( void );
268
269/**
270 * @brief Initializes the CPU context.
271 *
272 * The following steps are performed:
273 *  - setting a starting address
274 *  - preparing the stack
275 *  - preparing the stack and frame pointers
276 *  - setting the proper interrupt level in the context
277 *
278 * @param[in] context points to the context area
279 * @param[in] stack_area_begin is the low address of the allocated stack area
280 * @param[in] stack_area_size is the size of the stack area in bytes
281 * @param[in] new_level is the interrupt level for the task
282 * @param[in] entry_point is the task's entry point
283 * @param[in] is_fp is set to @c true if the task is a floating point task
284 * @param[in] tls_area is the thread-local storage (TLS) area
285 */
286void _CPU_Context_Initialize(
287  Context_Control *context,
288  void *stack_area_begin,
289  size_t stack_area_size,
290  uint32_t new_level,
291  void (*entry_point)( void ),
292  bool is_fp,
293  void *tls_area
294);
295
296#define _CPU_Context_Restart_self( _the_context ) \
297  _CPU_Context_restore( (_the_context) );
298
299void _CPU_Fatal_halt( uint32_t _source, uint32_t _error )
300  RTEMS_NO_RETURN;
301
302/**
303 * @brief CPU initialization.
304 */
305void _CPU_Initialize( void );
306
307/**
308 * @brief CPU ISR install raw handler.
309 */
310void _CPU_ISR_install_raw_handler(
311  uint32_t vector,
312  proc_ptr new_handler,
313  proc_ptr *old_handler
314);
315
316/**
317 * @brief CPU ISR install vector.
318 */
319void _CPU_ISR_install_vector(
320  uint32_t vector,
321  proc_ptr new_handler,
322  proc_ptr *old_handler
323);
324
325void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
326
327void _CPU_Context_restore(
328  Context_Control *new_context
329) RTEMS_NO_RETURN;
330
331void _CPU_Context_volatile_clobber( uintptr_t pattern );
332
333void _CPU_Context_validate( uintptr_t pattern );
334
335void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
336
337static inline uint32_t CPU_swap_u32( uint32_t value )
338{
339  uint32_t byte1, byte2, byte3, byte4, swapped;
340
341  byte4 = (value >> 24) & 0xff;
342  byte3 = (value >> 16) & 0xff;
343  byte2 = (value >> 8)  & 0xff;
344  byte1 =  value        & 0xff;
345
346  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
347
348  return swapped;
349}
350
351#define CPU_swap_u16( value ) \
352  (((value&0xff) << 8) | ((value >> 8)&0xff))
353
354typedef uint32_t CPU_Counter_ticks;
355
356CPU_Counter_ticks _CPU_Counter_read( void );
357
358static inline CPU_Counter_ticks _CPU_Counter_difference(
359  CPU_Counter_ticks second,
360  CPU_Counter_ticks first
361)
362{
363  return second - first;
364}
365
366#endif /* ASM */
367
368#ifdef __cplusplus
369}
370#endif
371
372#endif
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