[4f5740f] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @brief Altera Nios II CPU Department Source |
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| 5 | */ |
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| 6 | |
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[7a28ac8] | 7 | /* |
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[2a5880f1] | 8 | * Copyright (c) 2011 embedded brains GmbH |
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[7a28ac8] | 9 | * |
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[2a5880f1] | 10 | * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de) |
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[80f7732] | 11 | * |
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[2a5880f1] | 12 | * COPYRIGHT (c) 1989-2004. |
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[7a28ac8] | 13 | * On-Line Applications Research Corporation (OAR). |
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| 14 | * |
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| 15 | * The license and distribution terms for this file may be |
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| 16 | * found in the file LICENSE in this distribution or at |
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[c499856] | 17 | * http://www.rtems.org/license/LICENSE. |
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[7a28ac8] | 18 | */ |
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| 19 | |
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| 20 | #ifndef _RTEMS_SCORE_CPU_H |
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| 21 | #define _RTEMS_SCORE_CPU_H |
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| 22 | |
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| 23 | #ifdef __cplusplus |
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| 24 | extern "C" { |
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| 25 | #endif |
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| 26 | |
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[00acca28] | 27 | #include <rtems/score/basedefs.h> |
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[89b85e51] | 28 | #include <rtems/score/nios2.h> |
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[7a28ac8] | 29 | |
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| 30 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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| 31 | |
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[2a5880f1] | 32 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 |
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| 33 | |
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| 34 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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| 35 | |
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[e2d0c68] | 36 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE |
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[2a5880f1] | 37 | |
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[8b94c03] | 38 | #define CPU_ISR_PASSES_FRAME_POINTER FALSE |
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[7a28ac8] | 39 | |
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[2a5880f1] | 40 | #define CPU_HARDWARE_FP FALSE |
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[7a28ac8] | 41 | |
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[2a5880f1] | 42 | #define CPU_SOFTWARE_FP FALSE |
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[7a28ac8] | 43 | |
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[2a5880f1] | 44 | #define CPU_CONTEXT_FP_SIZE 0 |
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[7a28ac8] | 45 | |
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[2a5880f1] | 46 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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[7a28ac8] | 47 | |
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[2a5880f1] | 48 | #define CPU_IDLE_TASK_IS_FP FALSE |
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[7a28ac8] | 49 | |
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[2a5880f1] | 50 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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[7a28ac8] | 51 | |
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[84e6f15] | 52 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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| 53 | |
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[2a5880f1] | 54 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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[7a28ac8] | 55 | |
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[2a5880f1] | 56 | #define CPU_STACK_GROWS_UP FALSE |
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| 57 | |
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[a8865f8] | 58 | /* FIXME: Is this the right value? */ |
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| 59 | #define CPU_CACHE_LINE_BYTES 32 |
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| 60 | |
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| 61 | #define CPU_STRUCTURE_ALIGNMENT \ |
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| 62 | RTEMS_SECTION( ".sdata" ) RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
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[7a28ac8] | 63 | |
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[2a5880f1] | 64 | #define CPU_STACK_MINIMUM_SIZE (4 * 1024) |
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[7a28ac8] | 65 | |
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[f1738ed] | 66 | #define CPU_SIZEOF_POINTER 4 |
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| 67 | |
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[7a28ac8] | 68 | /* |
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[2a5880f1] | 69 | * Alignment value according to "Nios II Processor Reference" chapter 7 |
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| 70 | * "Application Binary Interface" section "Memory Alignment". |
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[7a28ac8] | 71 | */ |
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[2a5880f1] | 72 | #define CPU_ALIGNMENT 4 |
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[7a28ac8] | 73 | |
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[2a5880f1] | 74 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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[7a28ac8] | 75 | |
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[e2d0c68] | 76 | /* |
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| 77 | * Alignment value according to "Nios II Processor Reference" chapter 7 |
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| 78 | * "Application Binary Interface" section "Stacks". |
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| 79 | */ |
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| 80 | #define CPU_STACK_ALIGNMENT 4 |
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[2a5880f1] | 81 | |
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[c8df844] | 82 | #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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| 83 | |
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[e2d0c68] | 84 | /* |
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| 85 | * A Nios II configuration with an external interrupt controller (EIC) supports |
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| 86 | * up to 64 interrupt levels. A Nios II configuration with an internal |
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| 87 | * interrupt controller (IIC) has only two interrupt levels (enabled and |
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| 88 | * disabled). The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will |
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| 89 | * take care about configuration specific mappings. |
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| 90 | */ |
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| 91 | #define CPU_MODES_INTERRUPT_MASK 0x3f |
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[2a5880f1] | 92 | |
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| 93 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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| 94 | |
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| 95 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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[10fd4aac] | 96 | |
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[decff899] | 97 | #define CPU_MAXIMUM_PROCESSORS 32 |
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| 98 | |
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[2a5880f1] | 99 | #ifndef ASM |
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[7a28ac8] | 100 | |
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| 101 | /** |
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[40ae1fd] | 102 | * @brief Thread register context. |
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| 103 | * |
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| 104 | * The thread register context covers the non-volatile registers, the thread |
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| 105 | * stack pointer, the return address, and the processor status. |
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| 106 | * |
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| 107 | * There is no need to save the global pointer (gp) since it is a system wide |
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| 108 | * constant and set-up with the C runtime environment. |
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[e2d0c68] | 109 | * |
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| 110 | * The @a thread_dispatch_disabled field is used for the external interrupt |
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| 111 | * controller (EIC) support. |
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| 112 | * |
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| 113 | * @see _Nios2_Thread_dispatch_disabled |
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[7a28ac8] | 114 | */ |
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| 115 | typedef struct { |
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[40ae1fd] | 116 | uint32_t r16; |
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| 117 | uint32_t r17; |
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| 118 | uint32_t r18; |
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| 119 | uint32_t r19; |
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| 120 | uint32_t r20; |
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| 121 | uint32_t r21; |
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| 122 | uint32_t r22; |
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| 123 | uint32_t r23; |
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| 124 | uint32_t fp; |
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[e2d0c68] | 125 | uint32_t status; |
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[40ae1fd] | 126 | uint32_t sp; |
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| 127 | uint32_t ra; |
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[e2d0c68] | 128 | uint32_t thread_dispatch_disabled; |
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[9f1412b9] | 129 | uint32_t stack_mpubase; |
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| 130 | uint32_t stack_mpuacc; |
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[7a28ac8] | 131 | } Context_Control; |
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| 132 | |
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| 133 | #define _CPU_Context_Get_SP( _context ) \ |
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| 134 | (_context)->sp |
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| 135 | |
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[8b94c03] | 136 | typedef void CPU_Interrupt_frame; |
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[7a28ac8] | 137 | |
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| 138 | typedef struct { |
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[2a5880f1] | 139 | uint32_t r1; |
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| 140 | uint32_t r2; |
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| 141 | uint32_t r3; |
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| 142 | uint32_t r4; |
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| 143 | uint32_t r5; |
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| 144 | uint32_t r6; |
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| 145 | uint32_t r7; |
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| 146 | uint32_t r8; |
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| 147 | uint32_t r9; |
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| 148 | uint32_t r10; |
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| 149 | uint32_t r11; |
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| 150 | uint32_t r12; |
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| 151 | uint32_t r13; |
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| 152 | uint32_t r14; |
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| 153 | uint32_t r15; |
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| 154 | uint32_t r16; |
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| 155 | uint32_t r17; |
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| 156 | uint32_t r18; |
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| 157 | uint32_t r19; |
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| 158 | uint32_t r20; |
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| 159 | uint32_t r21; |
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| 160 | uint32_t r22; |
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| 161 | uint32_t r23; |
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| 162 | uint32_t gp; |
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| 163 | uint32_t fp; |
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| 164 | uint32_t sp; |
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| 165 | uint32_t ra; |
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| 166 | uint32_t et; |
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| 167 | uint32_t ea; |
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| 168 | uint32_t status; |
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| 169 | uint32_t ienable; |
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| 170 | uint32_t ipending; |
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[7a28ac8] | 171 | } CPU_Exception_frame; |
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| 172 | |
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[03b7789] | 173 | #define _CPU_Initialize_vectors() |
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[a385489] | 174 | |
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| 175 | /** |
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[e2d0c68] | 176 | * @brief Macro to disable interrupts. |
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| 177 | * |
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| 178 | * The processor status before disabling the interrupts will be stored in |
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| 179 | * @a _isr_cookie. This value will be used in _CPU_ISR_Flash() and |
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| 180 | * _CPU_ISR_Enable(). |
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| 181 | * |
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| 182 | * The global symbol _Nios2_ISR_Status_mask will be used to clear the bits in |
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| 183 | * the status register representing the interrupt level. The global symbol |
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| 184 | * _Nios2_ISR_Status_bits will be used to set the bits representing an |
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| 185 | * interrupt level that disables interrupts. Both global symbols must be |
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| 186 | * provided by the board support package. |
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| 187 | * |
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| 188 | * In case the Nios II uses the internal interrupt controller (IIC), then only |
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| 189 | * the PIE status bit is used. |
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| 190 | * |
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| 191 | * In case the Nios II uses the external interrupt controller (EIC), then the |
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| 192 | * RSIE status bit or the IL status field is used depending on the interrupt |
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| 193 | * handling variant and the shadow register usage. |
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[a385489] | 194 | */ |
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[7a28ac8] | 195 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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[2a5880f1] | 196 | do { \ |
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[e2d0c68] | 197 | int _tmp; \ |
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| 198 | __asm__ volatile ( \ |
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| 199 | "rdctl %0, status\n" \ |
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| 200 | "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \ |
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| 201 | "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \ |
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| 202 | "and %1, %0, %1\n" \ |
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| 203 | "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \ |
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| 204 | "wrctl status, %1" \ |
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| 205 | : "=&r" (_isr_cookie), "=&r" (_tmp) \ |
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| 206 | ); \ |
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[2a5880f1] | 207 | } while ( 0 ) |
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[7a28ac8] | 208 | |
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[a385489] | 209 | /** |
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[e2d0c68] | 210 | * @brief Macro to restore the processor status. |
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| 211 | * |
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| 212 | * The @a _isr_cookie must contain the processor status returned by |
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| 213 | * _CPU_ISR_Disable(). The value is not modified. |
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[a385489] | 214 | */ |
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[2a5880f1] | 215 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
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[e2d0c68] | 216 | __builtin_wrctl( 0, (int) _isr_cookie ) |
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[7a28ac8] | 217 | |
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[a385489] | 218 | /** |
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[e2d0c68] | 219 | * @brief Macro to restore the processor status and disable the interrupts |
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| 220 | * again. |
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| 221 | * |
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| 222 | * The @a _isr_cookie must contain the processor status returned by |
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| 223 | * _CPU_ISR_Disable(). The value is not modified. |
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| 224 | * |
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| 225 | * This flash code is optimal for all Nios II configurations. The rdctl does |
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[4f5740f] | 226 | * not flush the pipeline and has only a late result penalty. The wrctl on |
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| 227 | * the other hand leads to a pipeline flush. |
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[a385489] | 228 | */ |
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[7a28ac8] | 229 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
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[2a5880f1] | 230 | do { \ |
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[e2d0c68] | 231 | int _status = __builtin_rdctl( 0 ); \ |
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[2a5880f1] | 232 | __builtin_wrctl( 0, (int) _isr_cookie ); \ |
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[e2d0c68] | 233 | __builtin_wrctl( 0, _status ); \ |
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[2a5880f1] | 234 | } while ( 0 ) |
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[7a28ac8] | 235 | |
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[408609f6] | 236 | bool _CPU_ISR_Is_enabled( uint32_t level ); |
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| 237 | |
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[a385489] | 238 | /** |
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[e2d0c68] | 239 | * @brief Sets the interrupt level for the executing thread. |
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| 240 | * |
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| 241 | * The valid values of @a new_level depend on the Nios II configuration. A |
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| 242 | * value of zero represents enabled interrupts in all configurations. |
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| 243 | * |
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| 244 | * @see _CPU_ISR_Get_level() |
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[a385489] | 245 | */ |
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[e2d0c68] | 246 | void _CPU_ISR_Set_level( uint32_t new_level ); |
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[7a28ac8] | 247 | |
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[a385489] | 248 | /** |
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[e2d0c68] | 249 | * @brief Returns the interrupt level of the executing thread. |
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[a385489] | 250 | * |
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[e2d0c68] | 251 | * @retval 0 Interrupts are enabled. |
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| 252 | * @retval otherwise The value depends on the Nios II configuration. In case |
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| 253 | * of an internal interrupt controller (IIC) the only valid value is one which |
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| 254 | * indicates disabled interrupts. In case of an external interrupt controller |
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| 255 | * (EIC) there are two possibilities. Firstly if the RSIE status bit is used |
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| 256 | * to disable interrupts, then one is the only valid value indicating disabled |
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| 257 | * interrupts. Secondly if the IL status field is used to disable interrupts, |
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| 258 | * then this value will be returned. Interrupts are disabled at the maximum |
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| 259 | * level specified by the _Nios2_ISR_Status_bits. |
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[a385489] | 260 | */ |
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[2a5880f1] | 261 | uint32_t _CPU_ISR_Get_level( void ); |
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[7a28ac8] | 262 | |
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[a385489] | 263 | /** |
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[e2d0c68] | 264 | * @brief Initializes the CPU context. |
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[43e0599] | 265 | * |
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[e2d0c68] | 266 | * The following steps are performed: |
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[a385489] | 267 | * - setting a starting address |
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| 268 | * - preparing the stack |
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| 269 | * - preparing the stack and frame pointers |
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| 270 | * - setting the proper interrupt level in the context |
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| 271 | * |
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[e2d0c68] | 272 | * @param[in] context points to the context area |
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| 273 | * @param[in] stack_area_begin is the low address of the allocated stack area |
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| 274 | * @param[in] stack_area_size is the size of the stack area in bytes |
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[a385489] | 275 | * @param[in] new_level is the interrupt level for the task |
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| 276 | * @param[in] entry_point is the task's entry point |
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[e2d0c68] | 277 | * @param[in] is_fp is set to @c true if the task is a floating point task |
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[022851a] | 278 | * @param[in] tls_area is the thread-local storage (TLS) area |
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[7a28ac8] | 279 | */ |
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[a385489] | 280 | void _CPU_Context_Initialize( |
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[e2d0c68] | 281 | Context_Control *context, |
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| 282 | void *stack_area_begin, |
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| 283 | size_t stack_area_size, |
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| 284 | uint32_t new_level, |
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| 285 | void (*entry_point)( void ), |
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[022851a] | 286 | bool is_fp, |
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| 287 | void *tls_area |
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[a385489] | 288 | ); |
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[7a28ac8] | 289 | |
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| 290 | #define _CPU_Context_Restart_self( _the_context ) \ |
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[2a5880f1] | 291 | _CPU_Context_restore( (_the_context) ); |
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[7a28ac8] | 292 | |
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[f82752a4] | 293 | void _CPU_Fatal_halt( uint32_t _source, uint32_t _error ) |
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[143696a] | 294 | RTEMS_NO_RETURN; |
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[7a28ac8] | 295 | |
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[43e0599] | 296 | /** |
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[4f5740f] | 297 | * @brief CPU initialization. |
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[43e0599] | 298 | */ |
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[2a5880f1] | 299 | void _CPU_Initialize( void ); |
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[7a28ac8] | 300 | |
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[43e0599] | 301 | /** |
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[4f5740f] | 302 | * @brief CPU ISR install raw handler. |
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[43e0599] | 303 | */ |
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[7a28ac8] | 304 | void _CPU_ISR_install_raw_handler( |
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[2a5880f1] | 305 | uint32_t vector, |
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| 306 | proc_ptr new_handler, |
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| 307 | proc_ptr *old_handler |
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[7a28ac8] | 308 | ); |
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| 309 | |
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[43e0599] | 310 | /** |
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[4f5740f] | 311 | * @brief CPU ISR install vector. |
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[43e0599] | 312 | */ |
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[7a28ac8] | 313 | void _CPU_ISR_install_vector( |
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[2a5880f1] | 314 | uint32_t vector, |
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| 315 | proc_ptr new_handler, |
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| 316 | proc_ptr *old_handler |
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[7a28ac8] | 317 | ); |
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| 318 | |
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[2a5880f1] | 319 | void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); |
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[7a28ac8] | 320 | |
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| 321 | void _CPU_Context_restore( |
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| 322 | Context_Control *new_context |
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[143696a] | 323 | ) RTEMS_NO_RETURN; |
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[7a28ac8] | 324 | |
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[815994f] | 325 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
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| 326 | |
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[2a5880f1] | 327 | static inline uint32_t CPU_swap_u32( uint32_t value ) |
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[7a28ac8] | 328 | { |
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[2a5880f1] | 329 | uint32_t byte1, byte2, byte3, byte4, swapped; |
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[80f7732] | 330 | |
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[7a28ac8] | 331 | byte4 = (value >> 24) & 0xff; |
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| 332 | byte3 = (value >> 16) & 0xff; |
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| 333 | byte2 = (value >> 8) & 0xff; |
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| 334 | byte1 = value & 0xff; |
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[80f7732] | 335 | |
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[7a28ac8] | 336 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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[2a5880f1] | 337 | |
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| 338 | return swapped; |
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[7a28ac8] | 339 | } |
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| 340 | |
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| 341 | #define CPU_swap_u16( value ) \ |
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| 342 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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| 343 | |
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[24bf11e] | 344 | typedef uint32_t CPU_Counter_ticks; |
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| 345 | |
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[65f868c] | 346 | uint32_t _CPU_Counter_frequency( void ); |
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| 347 | |
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[24bf11e] | 348 | CPU_Counter_ticks _CPU_Counter_read( void ); |
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| 349 | |
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| 350 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
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| 351 | CPU_Counter_ticks second, |
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| 352 | CPU_Counter_ticks first |
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| 353 | ) |
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| 354 | { |
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| 355 | return second - first; |
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| 356 | } |
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| 357 | |
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[00acca28] | 358 | /** Type that can store a 32-bit integer or a pointer. */ |
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| 359 | typedef uintptr_t CPU_Uint32ptr; |
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| 360 | |
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[2a5880f1] | 361 | #endif /* ASM */ |
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| 362 | |
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[7a28ac8] | 363 | #ifdef __cplusplus |
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| 364 | } |
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| 365 | #endif |
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| 366 | |
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| 367 | #endif |
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