[7a28ac8] | 1 | /* |
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| 2 | * $Id$ |
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| 3 | * |
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| 4 | * This file contains all assembly code for the |
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| 5 | * NIOS2 implementation of RTEMS. |
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| 6 | * |
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| 7 | * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de) |
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| 8 | * |
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| 9 | * Derived from no_cpu/cpu_asm.S, copyright (c) 1989-1999, |
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| 10 | * On-Line Applications Research Corporation (OAR). |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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| 14 | * http://www.rtems.com/license/LICENSE. |
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| 15 | * |
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| 16 | */ |
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| 17 | |
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[5632f8d] | 18 | #ifdef HAVE_CONFIG_H |
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| 19 | #include "config.h" |
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| 20 | #endif |
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| 21 | |
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[7a28ac8] | 22 | #include <rtems/asm.h> |
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| 23 | #include <rtems/score/cpu_asm.h> |
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| 24 | |
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| 25 | .set noat |
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| 26 | |
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| 27 | /* ===================================================================== */ |
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| 28 | |
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| 29 | /* |
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| 30 | * void _CPU_Context_switch( run_context, heir_context ) |
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| 31 | * void _CPU_Context_restore( run_context, heir_context ) |
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| 32 | * |
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| 33 | * This routine performs a normal non-FP context switch. |
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| 34 | */ |
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| 35 | |
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| 36 | .globl _CPU_Context_switch |
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| 37 | |
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| 38 | _CPU_Context_switch: |
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| 39 | |
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| 40 | rdctl r6, status |
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| 41 | stw r16, 0(r4) |
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| 42 | stw r17, 4(r4) |
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| 43 | stw r18, 8(r4) |
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| 44 | stw r19, 12(r4) |
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| 45 | stw r20, 16(r4) |
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| 46 | stw r21, 20(r4) |
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| 47 | stw r22, 24(r4) |
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| 48 | stw r23, 28(r4) |
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| 49 | stw gp, 32(r4) |
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| 50 | stw fp, 36(r4) |
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| 51 | stw sp, 40(r4) |
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| 52 | stw ra, 44(r4) |
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| 53 | /* r6 saved status */ |
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| 54 | stw r6, 48(r4) |
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| 55 | |
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| 56 | _CPU_Context_switch_restore: |
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| 57 | |
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| 58 | ldw r16, 0(r5) |
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| 59 | ldw r17, 4(r5) |
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| 60 | ldw r18, 8(r5) |
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| 61 | ldw r19, 12(r5) |
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| 62 | ldw r20, 16(r5) |
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| 63 | ldw r21, 20(r5) |
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| 64 | ldw r22, 24(r5) |
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| 65 | ldw r23, 28(r5) |
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| 66 | ldw gp, 32(r5) |
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| 67 | ldw fp, 36(r5) |
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| 68 | ldw sp, 40(r5) |
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| 69 | |
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| 70 | /* Disable interrupts */ |
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| 71 | wrctl status, r0 |
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| 72 | |
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| 73 | ldw ea, 44(r5) |
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| 74 | ldw at, 48(r5) |
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| 75 | /* FIXME: Always have interrupts enabled when we return from Context_switch */ |
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| 76 | ori at, at, 1 |
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| 77 | wrctl estatus, at |
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| 78 | |
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| 79 | eret |
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| 80 | |
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| 81 | .globl _CPU_Context_restore |
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| 82 | |
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| 83 | _CPU_Context_restore: |
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| 84 | |
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| 85 | /* Copy first to second arg, then re-use 2nd half of Context_switch */ |
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| 86 | mov r5, r4 |
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| 87 | br _CPU_Context_switch_restore |
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| 88 | |
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| 89 | |
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| 90 | /* ===================================================================== */ |
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| 91 | |
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| 92 | .globl _exception_vector |
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| 93 | |
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| 94 | _exception_vector: |
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| 95 | |
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[80f7732] | 96 | /* |
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[7a28ac8] | 97 | * First, re-wind so we're pointed to the instruction where the exception |
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| 98 | * occurred. |
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| 99 | */ |
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| 100 | |
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[80f7732] | 101 | addi ea, ea, -4 |
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[7a28ac8] | 102 | |
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| 103 | /* |
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| 104 | * Now test to determine the cause of the exception. |
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| 105 | */ |
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| 106 | |
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| 107 | /* TODO: Look at [ea] if there was an unknown/trap instruction */ |
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| 108 | |
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| 109 | /* If interrupts are globally disabled, it certainly was no interrupt */ |
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| 110 | rdctl et, estatus |
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| 111 | andi et, et, 1 |
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| 112 | beq et, zero, _Exception_Handler |
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| 113 | |
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| 114 | /* If no interrupts are pending, it was a software exception */ |
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| 115 | rdctl et, ipending |
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| 116 | beq et, zero, _Exception_Handler |
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| 117 | |
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| 118 | /* |
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| 119 | * Falling through to here means that this was a hardware interrupt. |
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| 120 | */ |
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| 121 | |
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| 122 | br _ISR_Handler |
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| 123 | |
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[80f7732] | 124 | /* ===================================================================== |
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[7a28ac8] | 125 | * Exception handler: |
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| 126 | * Responsible for unimplemented instructions and other software |
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| 127 | * exceptions. Not responsible for hardware interrupts. Currently, |
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| 128 | * software exceptions are regarded as error conditions, and the |
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| 129 | * handling isn't perfect. */ |
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| 130 | |
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| 131 | _Exception_Handler: |
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| 132 | |
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| 133 | /* stw et, 108(sp') => stw et, -20(sp) */ |
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| 134 | stw et, -20(sp) |
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| 135 | mov et, sp |
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| 136 | addi sp, sp, -128 |
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| 137 | |
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| 138 | stw r1, 0(sp) |
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| 139 | stw r2, 4(sp) |
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| 140 | stw r3, 8(sp) |
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| 141 | |
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| 142 | rdctl r1, estatus |
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| 143 | rdctl r2, ienable |
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| 144 | rdctl r3, ipending |
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| 145 | |
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| 146 | stw r4, 12(sp) |
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| 147 | stw r5, 16(sp) |
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| 148 | stw r6, 20(sp) |
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| 149 | stw r7, 24(sp) |
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| 150 | stw r8, 28(sp) |
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| 151 | stw r9, 32(sp) |
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| 152 | stw r10, 36(sp) |
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| 153 | stw r11, 40(sp) |
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| 154 | stw r12, 44(sp) |
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| 155 | stw r13, 48(sp) |
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| 156 | stw r14, 52(sp) |
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| 157 | stw r15, 56(sp) |
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| 158 | stw r16, 60(sp) |
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| 159 | stw r17, 64(sp) |
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| 160 | stw r18, 68(sp) |
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| 161 | stw r19, 72(sp) |
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| 162 | stw r20, 76(sp) |
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| 163 | stw r21, 80(sp) |
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| 164 | stw r22, 84(sp) |
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| 165 | stw r23, 88(sp) |
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| 166 | stw gp, 92(sp) |
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| 167 | stw fp, 96(sp) |
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| 168 | /* sp */ |
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| 169 | stw et, 100(sp) |
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| 170 | stw ra, 104(sp) |
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| 171 | /* stw et, 108(sp) */ |
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| 172 | stw ea, 112(sp) |
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| 173 | |
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| 174 | /* status */ |
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| 175 | stw r1, 116(sp) |
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| 176 | /* ienable */ |
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| 177 | stw r2, 120(sp) |
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| 178 | /* ipending */ |
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| 179 | stw r3, 124(sp) |
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| 180 | |
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| 181 | /* |
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| 182 | * Restore the global pointer. |
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| 183 | */ |
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| 184 | |
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| 185 | movhi gp, %hiadj(_gp) |
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| 186 | addi gp, gp, %lo(_gp) |
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| 187 | |
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| 188 | /* |
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[80f7732] | 189 | * Pass a pointer to the stack frame as the input argument of the |
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[7a28ac8] | 190 | * exception handler (CPU_Exception_frame *). |
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| 191 | */ |
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| 192 | |
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| 193 | mov r4, sp |
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| 194 | |
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| 195 | /* |
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| 196 | * Call the exception handler. |
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| 197 | */ |
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| 198 | |
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| 199 | .extern __Exception_Handler |
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| 200 | call __Exception_Handler |
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| 201 | |
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| 202 | stuck_in_exception: |
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| 203 | br stuck_in_exception |
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| 204 | |
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[80f7732] | 205 | /* |
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| 206 | * Restore the saved registers, so that all general purpose registers |
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[7a28ac8] | 207 | * have been restored to their state at the time the interrupt occured. |
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| 208 | */ |
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| 209 | |
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| 210 | ldw r1, 0(sp) |
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| 211 | ldw r2, 4(sp) |
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| 212 | ldw r3, 8(sp) |
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| 213 | ldw r4, 12(sp) |
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| 214 | ldw r5, 16(sp) |
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| 215 | ldw r6, 20(sp) |
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| 216 | ldw r7, 24(sp) |
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| 217 | ldw r8, 28(sp) |
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| 218 | ldw r9, 32(sp) |
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| 219 | ldw r10, 36(sp) |
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| 220 | ldw r11, 40(sp) |
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| 221 | ldw r12, 44(sp) |
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| 222 | ldw r13, 48(sp) |
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| 223 | ldw r14, 52(sp) |
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| 224 | ldw r15, 56(sp) |
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| 225 | ldw r16, 60(sp) |
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| 226 | ldw r17, 64(sp) |
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| 227 | ldw r18, 68(sp) |
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| 228 | ldw r19, 72(sp) |
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| 229 | ldw r20, 76(sp) |
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| 230 | ldw r21, 80(sp) |
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| 231 | ldw r22, 84(sp) |
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| 232 | ldw r23, 88(sp) |
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| 233 | ldw gp, 92(sp) |
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| 234 | ldw fp, 96(sp) |
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| 235 | ldw ra, 104(sp) |
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| 236 | |
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| 237 | /* Disable interrupts */ |
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| 238 | wrctl status, r0 |
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| 239 | |
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| 240 | ldw ea, 112(sp) |
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| 241 | ldw et, 116(sp) |
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| 242 | |
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| 243 | /* FIXME: Enable interrupts after exception processing */ |
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| 244 | ori et, et, 1 |
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| 245 | wrctl estatus, et |
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| 246 | ldw et, 108(sp) |
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| 247 | |
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| 248 | /* Restore stack pointer */ |
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| 249 | ldw sp, 100(sp) |
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| 250 | |
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| 251 | eret |
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| 252 | |
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| 253 | /* ===================================================================== */ |
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| 254 | |
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| 255 | .section .text |
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| 256 | |
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| 257 | _ISR_Handler: |
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| 258 | |
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[80f7732] | 259 | /* |
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| 260 | * Process an external hardware interrupt. |
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[7a28ac8] | 261 | * |
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[80f7732] | 262 | * First, preserve all callee saved registers on |
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[7a28ac8] | 263 | * the stack. (See the Nios2 ABI documentation for details). |
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| 264 | * |
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[80f7732] | 265 | * Do we really need to save all? |
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[7a28ac8] | 266 | * |
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| 267 | * If this is interrupting a task (and not another interrupt), |
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| 268 | * everything is saved into the task's stack, thus putting us |
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| 269 | * in a situation similar to when the task calls a subroutine |
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| 270 | * (and only the CPU_Context_Control subset needs to be changed) |
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| 271 | */ |
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| 272 | |
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| 273 | rdctl et, estatus |
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| 274 | |
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| 275 | /* Keep this in the same order as CPU_Interrupt_frame: */ |
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| 276 | |
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| 277 | addi sp, sp, -76 |
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| 278 | stw r1, 0(sp) |
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| 279 | stw r2, 4(sp) |
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| 280 | stw r3, 8(sp) |
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| 281 | stw r4, 12(sp) |
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| 282 | stw r5, 16(sp) |
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| 283 | stw r6, 20(sp) |
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| 284 | stw r7, 24(sp) |
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| 285 | stw r8, 28(sp) |
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| 286 | stw r9, 32(sp) |
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| 287 | stw r10, 36(sp) |
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| 288 | stw r11, 40(sp) |
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| 289 | stw r12, 44(sp) |
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| 290 | stw r13, 48(sp) |
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| 291 | stw r14, 52(sp) |
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| 292 | stw r15, 56(sp) |
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| 293 | stw ra, 60(sp) |
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| 294 | stw gp, 64(sp) |
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| 295 | /* et contains status */ |
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| 296 | stw et, 68(sp) |
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| 297 | stw ea, 72(sp) |
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| 298 | |
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| 299 | /* |
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| 300 | * Obtain a bitlist of the pending interrupts. |
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| 301 | */ |
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| 302 | |
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| 303 | rdctl et, ipending |
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| 304 | |
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| 305 | /* |
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| 306 | * Restore the global pointer to the expected value. |
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| 307 | */ |
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| 308 | |
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| 309 | movhi gp, %hiadj(_gp) |
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| 310 | addi gp, gp, %lo(_gp) |
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| 311 | |
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| 312 | /* |
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| 313 | * Search through the bit list stored in r24(et) to find the first enabled |
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| 314 | * bit. The offset of this bit is the index of the interrupt that is |
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| 315 | * to be handled. |
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| 316 | */ |
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| 317 | |
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| 318 | mov r4, zero |
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| 319 | 6: |
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| 320 | andi r3, r24, 1 |
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| 321 | bne r3, zero, 7f |
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| 322 | addi r4, r4, 1 |
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| 323 | srli r24, r24, 1 |
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| 324 | br 6b |
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| 325 | 7: |
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| 326 | |
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| 327 | /* |
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| 328 | * Having located the interrupt source, r4 contains the index of the |
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| 329 | * interrupt to be handled. r5, the 2nd argument to the function, |
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| 330 | * will point to the CPU_Interrupt_frame. |
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| 331 | */ |
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| 332 | |
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| 333 | mov r5, sp |
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| 334 | |
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| 335 | .extern __ISR_Handler |
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| 336 | call __ISR_Handler |
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| 337 | |
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[80f7732] | 338 | /* |
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[7a28ac8] | 339 | * Now that the interrupt processing is complete, prepare to return to |
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| 340 | * the interrupted code. |
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| 341 | */ |
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| 342 | |
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| 343 | /* |
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[80f7732] | 344 | * Restore the saved registers, so that all general purpose registers |
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[7a28ac8] | 345 | * have been restored to their state at the time the interrupt occured. |
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| 346 | */ |
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| 347 | |
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| 348 | ldw r1, 0(sp) |
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| 349 | ldw r2, 4(sp) |
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| 350 | ldw r3, 8(sp) |
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| 351 | ldw r4, 12(sp) |
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| 352 | ldw r5, 16(sp) |
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| 353 | ldw r6, 20(sp) |
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| 354 | ldw r7, 24(sp) |
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| 355 | ldw r8, 28(sp) |
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| 356 | ldw r9, 32(sp) |
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| 357 | ldw r10, 36(sp) |
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| 358 | ldw r11, 40(sp) |
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| 359 | ldw r12, 44(sp) |
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| 360 | ldw r13, 48(sp) |
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| 361 | ldw r14, 52(sp) |
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| 362 | ldw r15, 56(sp) |
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| 363 | ldw ra, 60(sp) |
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| 364 | ldw gp, 64(sp) |
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| 365 | |
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| 366 | /* Disable interrupts */ |
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| 367 | wrctl status, r0 |
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| 368 | |
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| 369 | /* Restore the exception registers */ |
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| 370 | |
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| 371 | /* load saved ea into ea */ |
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| 372 | ldw ea, 72(sp) |
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| 373 | /* load saved estatus into et */ |
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| 374 | ldw et, 68(sp) |
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| 375 | /* Always have interrupts enabled when we return from interrupt */ |
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| 376 | ori et, et, 1 |
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| 377 | wrctl estatus, et |
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| 378 | /* Restore the stack pointer */ |
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| 379 | addi sp, sp, 76 |
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| 380 | |
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| 381 | /* |
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| 382 | * Return to the interrupted instruction. |
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| 383 | */ |
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| 384 | eret |
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| 385 | |
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| 386 | |
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