source: rtems/cpukit/score/cpu/nios2/cpu.c @ 60f016f

4.104.114.84.95
Last change on this file since 60f016f was 60f016f, checked in by Joel Sherrill <joel.sherrill@…>, on May 22, 2007 at 8:57:34 PM

2007-05-22 Joel Sherrill <joel.sherrill@…>

  • score/cpu/arm/cpu.c, score/cpu/avr/cpu.c, score/cpu/bfin/cpu.c, score/cpu/c4x/cpu.c, score/cpu/h8300/cpu.c, score/cpu/i386/cpu.c, score/cpu/m68k/cpu.c, score/cpu/mips/cpu.c, score/cpu/nios2/cpu.c, score/cpu/no_cpu/cpu.c, score/cpu/sh/cpu.c, score/cpu/sparc/cpu.c, cpukit/sapi/src/exinit.c: Move copying of CPU Table to shared executive initialization.
  • Property mode set to 100644
File size: 4.4 KB
Line 
1/*
2 *  NIOS2 CPU Dependent Source
3 *
4 *  COPYRIGHT (c) 1989-2006
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16#include <rtems/score/wkspace.h>
17
18/*  _CPU_Initialize
19 *
20 *  This routine performs processor dependent initialization.
21 *
22 *  INPUT PARAMETERS:
23 *    cpu_table       - CPU table to initialize
24 *    thread_dispatch - address of disptaching routine
25 *
26 *  NO_CPU Specific Information:
27 *
28 *  XXX document implementation including references if appropriate
29 */
30
31
32void _CPU_Initialize(
33  rtems_cpu_table  *cpu_table,
34  void      (*thread_dispatch)      /* ignored on this CPU */
35)
36{
37  /*
38   *  The thread_dispatch argument is the address of the entry point
39   *  for the routine called at the end of an ISR once it has been
40   *  decided a context switch is necessary.  On some compilation
41   *  systems it is difficult to call a high-level language routine
42   *  from assembly.  This allows us to trick these systems.
43   *
44   *  If you encounter this problem save the entry point in a CPU
45   *  dependent variable.
46   */
47
48  _CPU_Thread_dispatch_pointer = thread_dispatch;
49
50  /*
51   *  If there is not an easy way to initialize the FP context
52   *  during Context_Initialize, then it is usually easier to
53   *  save an "uninitialized" FP context here and copy it to
54   *  the task's during Context_Initialize.
55   */
56
57  /* FP context initialization support goes here */
58}
59
60/*PAGE
61 *
62 *  _CPU_ISR_Get_level
63 *
64 *  NO_CPU Specific Information:
65 *
66 *  XXX document implementation including references if appropriate
67 */
68 
69uint32_t   _CPU_ISR_Get_level( void )
70{
71  /*
72   *  This routine returns the current interrupt level.
73   */
74
75  return 0;
76}
77
78/*PAGE
79 *
80 *  _CPU_ISR_install_raw_handler
81 *
82 *  NO_CPU Specific Information:
83 *
84 *  XXX document implementation including references if appropriate
85 */
86 
87void _CPU_ISR_install_raw_handler(
88  uint32_t    vector,
89  proc_ptr    new_handler,
90  proc_ptr   *old_handler
91)
92{
93  /*
94   *  This is where we install the interrupt handler into the "raw" interrupt
95   *  table used by the CPU to dispatch interrupt handlers.
96   */
97}
98
99/*PAGE
100 *
101 *  _CPU_ISR_install_vector
102 *
103 *  This kernel routine installs the RTEMS handler for the
104 *  specified vector.
105 *
106 *  Input parameters:
107 *    vector      - interrupt vector number
108 *    old_handler - former ISR for this vector number
109 *    new_handler - replacement ISR for this vector number
110 *
111 *  Output parameters:  NONE
112 *
113 *
114 *  NO_CPU Specific Information:
115 *
116 *  XXX document implementation including references if appropriate
117 */
118
119void _CPU_ISR_install_vector(
120  uint32_t    vector,
121  proc_ptr    new_handler,
122  proc_ptr   *old_handler
123)
124{
125   *old_handler = _ISR_Vector_table[ vector ];
126
127   /*
128    *  If the interrupt vector table is a table of pointer to isr entry
129    *  points, then we need to install the appropriate RTEMS interrupt
130    *  handler for this vector number.
131    */
132
133   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
134
135   /*
136    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
137    *  be used by the _ISR_Handler so the user gets control.
138    */
139
140    _ISR_Vector_table[ vector ] = new_handler;
141}
142
143/*PAGE
144 *
145 *  _CPU_Install_interrupt_stack
146 *
147 *  NO_CPU Specific Information:
148 *
149 *  XXX document implementation including references if appropriate
150 */
151
152void _CPU_Install_interrupt_stack( void )
153{
154}
155
156/*PAGE
157 *
158 *  _CPU_Thread_Idle_body
159 *
160 *  NOTES:
161 *
162 *  1. This is the same as the regular CPU independent algorithm.
163 *
164 *  2. If you implement this using a "halt", "idle", or "shutdown"
165 *     instruction, then don't forget to put it in an infinite loop.
166 *
167 *  3. Be warned. Some processors with onboard DMA have been known
168 *     to stop the DMA if the CPU were put in IDLE mode.  This might
169 *     also be a problem with other on-chip peripherals.  So use this
170 *     hook with caution.
171 *
172 *  NO_CPU Specific Information:
173 *
174 *  XXX document implementation including references if appropriate
175 */
176
177void _CPU_Thread_Idle_body( void )
178{
179#if 1
180  for(;;);
181#else
182  for(;;)
183  {
184    uint32_t st = __builtin_rdctl(0); /* read status  register */
185
186    /* Differentiate between IRQ off and on (for debugging) */
187    if(st & 1)
188      for(;;); 
189    else
190      for(;;); 
191 
192    /* insert your "halt" instruction here */ ;
193  }
194#endif
195}
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