source: rtems/cpukit/score/cpu/moxie/rtems/score/cpu.h @ f82752a4

4.115
Last change on this file since f82752a4 was f82752a4, checked in by Daniel Hellstrom <daniel@…>, on Jun 4, 2014 at 9:23:34 AM

Let CPU/BSP Fatal handler have access to source

Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.

This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.

  • Property mode set to 100644
File size: 31.3 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the Moxie
7 *  processor.
8 *
9 *  Copyright (c) 2013  Anthony Green
10 *
11 *  Based on code with the following copyright..
12 *  COPYRIGHT (c) 1989-2006, 2010.
13 *  On-Line Applications Research Corporation (OAR).
14 *
15 *  The license and distribution terms for this file may be
16 *  found in the file LICENSE in this distribution or at
17 *  http://www.rtems.org/license/LICENSE.
18 */
19
20#ifndef _RTEMS_SCORE_CPU_H
21#define _RTEMS_SCORE_CPU_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#include <rtems/score/types.h>
28#include <rtems/score/moxie.h>  /* pick up machine definitions */
29
30#include <rtems/bspIo.h>        /* printk */
31
32/* conditional compilation parameters */
33
34/*
35 *  Should the calls to _Thread_Enable_dispatch be inlined?
36 *
37 *  If TRUE, then they are inlined.
38 *  If FALSE, then a subroutine call is made.
39 *
40 *  Basically this is an example of the classic trade-off of size
41 *  versus speed.  Inlining the call (TRUE) typically increases the
42 *  size of RTEMS while speeding up the enabling of dispatching.
43 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
44 *  only be 0 or 1 unless you are in an interrupt handler and that
45 *  interrupt handler invokes the executive.]  When not inlined
46 *  something calls _Thread_Enable_dispatch which in turns calls
47 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
48 *  one subroutine call is avoided entirely.]
49 *
50 *  MOXIE Specific Information:
51 *
52 *  XXX
53 */
54#define CPU_INLINE_ENABLE_DISPATCH       FALSE
55
56/*
57 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
58 *  be unrolled one time?  In unrolled each iteration of the loop examines
59 *  two "nodes" on the chain being searched.  Otherwise, only one node
60 *  is examined per iteration.
61 *
62 *  If TRUE, then the loops are unrolled.
63 *  If FALSE, then the loops are not unrolled.
64 *
65 *  The primary factor in making this decision is the cost of disabling
66 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
67 *  body of the loop.  On some CPUs, the flash is more expensive than
68 *  one iteration of the loop body.  In this case, it might be desirable
69 *  to unroll the loop.  It is important to note that on some CPUs, this
70 *  code is the longest interrupt disable period in RTEMS.  So it is
71 *  necessary to strike a balance when setting this parameter.
72 *
73 *  MOXIE Specific Information:
74 *
75 *  XXX
76 */
77#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
78
79/*
80 *  Should this target use 16 or 32 bit object Ids?
81 *
82 */
83#define RTEMS_USE_32_BIT_OBJECT
84
85/*
86 *  Does RTEMS manage a dedicated interrupt stack in software?
87 *
88 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
89 *  If FALSE, nothing is done.
90 *
91 *  If the CPU supports a dedicated interrupt stack in hardware,
92 *  then it is generally the responsibility of the BSP to allocate it
93 *  and set it up.
94 *
95 *  If the CPU does not support a dedicated interrupt stack, then
96 *  the porter has two options: (1) execute interrupts on the
97 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
98 *  interrupt stack.
99 *
100 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
101 *
102 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
103 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
104 *  possible that both are FALSE for a particular CPU.  Although it
105 *  is unclear what that would imply about the interrupt processing
106 *  procedure on that CPU.
107 *
108 *  MOXIE Specific Information:
109 *
110 *  XXX
111 */
112#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
113
114/*
115 *  Does the CPU follow the simple vectored interrupt model?
116 *
117 *  If TRUE, then RTEMS allocates the vector table it internally manages.
118 *  If FALSE, then the BSP is assumed to allocate and manage the vector
119 *  table
120 *
121 *  MOXIE Specific Information:
122 *
123 *  XXX document implementation including references if appropriate
124 */
125#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
126
127/*
128 *  Does this CPU have hardware support for a dedicated interrupt stack?
129 *
130 *  If TRUE, then it must be installed during initialization.
131 *  If FALSE, then no installation is performed.
132 *
133 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
134 *
135 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
136 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
137 *  possible that both are FALSE for a particular CPU.  Although it
138 *  is unclear what that would imply about the interrupt processing
139 *  procedure on that CPU.
140 *
141 *  MOXIE Specific Information:
142 *
143 *  XXX
144 */
145#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
146
147/*
148 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
149 *
150 *  If TRUE, then the memory is allocated during initialization.
151 *  If FALSE, then the memory is allocated during initialization.
152 *
153 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
154 *
155 *  MOXIE Specific Information:
156 *
157 *  XXX
158 */
159#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
160
161/*
162 *  Does the CPU have hardware floating point?
163 *
164 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
165 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
166 *
167 *  If there is a FP coprocessor such as the i387 or mc68881, then
168 *  the answer is TRUE.
169 *
170 *  The macro name "MOXIE_HAS_FPU" should be made CPU specific.
171 *  It indicates whether or not this CPU model has FP support.  For
172 *  example, it would be possible to have an i386_nofp CPU model
173 *  which set this to false to indicate that you have an i386 without
174 *  an i387 and wish to leave floating point support out of RTEMS.
175 *
176 *  MOXIE Specific Information:
177 *
178 *  XXX
179 */
180#define CPU_HARDWARE_FP     FALSE
181
182/*
183 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
184 *
185 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
186 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
187 *
188 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
189 *
190 *  MOXIE Specific Information:
191 *
192 *  XXX
193 */
194#define CPU_ALL_TASKS_ARE_FP     FALSE
195
196/*
197 *  Should the IDLE task have a floating point context?
198 *
199 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
200 *  and it has a floating point context which is switched in and out.
201 *  If FALSE, then the IDLE task does not have a floating point context.
202 *
203 *  Setting this to TRUE negatively impacts the time required to preempt
204 *  the IDLE task from an interrupt because the floating point context
205 *  must be saved as part of the preemption.
206 *
207 *  MOXIE Specific Information:
208 *
209 *  XXX
210 */
211#define CPU_IDLE_TASK_IS_FP      FALSE
212
213/*
214 *  Should the saving of the floating point registers be deferred
215 *  until a context switch is made to another different floating point
216 *  task?
217 *
218 *  If TRUE, then the floating point context will not be stored until
219 *  necessary.  It will remain in the floating point registers and not
220 *  disturned until another floating point task is switched to.
221 *
222 *  If FALSE, then the floating point context is saved when a floating
223 *  point task is switched out and restored when the next floating point
224 *  task is restored.  The state of the floating point registers between
225 *  those two operations is not specified.
226 *
227 *  If the floating point context does NOT have to be saved as part of
228 *  interrupt dispatching, then it should be safe to set this to TRUE.
229 *
230 *  Setting this flag to TRUE results in using a different algorithm
231 *  for deciding when to save and restore the floating point context.
232 *  The deferred FP switch algorithm minimizes the number of times
233 *  the FP context is saved and restored.  The FP context is not saved
234 *  until a context switch is made to another, different FP task.
235 *  Thus in a system with only one FP task, the FP context will never
236 *  be saved or restored.
237 *
238 *  MOXIE Specific Information:
239 *
240 *  XXX
241 */
242#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
243
244/*
245 *  Does this port provide a CPU dependent IDLE task implementation?
246 *
247 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
248 *  must be provided and is the default IDLE thread body instead of
249 *  _Internal_threads_Idle_thread_body.
250 *
251 *  If FALSE, then use the generic IDLE thread body if the BSP does
252 *  not provide one.
253 *
254 *  This is intended to allow for supporting processors which have
255 *  a low power or idle mode.  When the IDLE thread is executed, then
256 *  the CPU can be powered down.
257 *
258 *  The order of precedence for selecting the IDLE thread body is:
259 *
260 *    1.  BSP provided
261 *    2.  CPU dependent (if provided)
262 *    3.  generic (if no BSP and no CPU dependent)
263 *
264 *  MOXIE Specific Information:
265 *
266 *  XXX
267 *  The port initially called a BSP dependent routine called
268 *  IDLE_Monitor.  The idle task body can be overridden by
269 *  the BSP in newer versions of RTEMS.
270 */
271#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
272
273/*
274 *  Does the stack grow up (toward higher addresses) or down
275 *  (toward lower addresses)?
276 *
277 *  If TRUE, then the grows upward.
278 *  If FALSE, then the grows toward smaller addresses.
279 *
280 *  MOXIE Specific Information:
281 *
282 *  XXX
283 */
284#define CPU_STACK_GROWS_UP               FALSE
285
286/*
287 *  The following is the variable attribute used to force alignment
288 *  of critical RTEMS structures.  On some processors it may make
289 *  sense to have these aligned on tighter boundaries than
290 *  the minimum requirements of the compiler in order to have as
291 *  much of the critical data area as possible in a cache line.
292 *
293 *  The placement of this macro in the declaration of the variables
294 *  is based on the syntactically requirements of the GNU C
295 *  "__attribute__" extension.  For example with GNU C, use
296 *  the following to force a structures to a 32 byte boundary.
297 *
298 *      __attribute__ ((aligned (32)))
299 *
300 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
301 *         To benefit from using this, the data must be heavily
302 *         used so it will stay in the cache and used frequently enough
303 *         in the executive to justify turning this on.
304 *
305 *  MOXIE Specific Information:
306 *
307 *  XXX
308 */
309#define CPU_STRUCTURE_ALIGNMENT
310
311#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
312#define CPU_TIMESTAMP_USE_INT64 FALSE
313#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE
314
315/*
316 *  Define what is required to specify how the network to host conversion
317 *  routines are handled.
318 */
319#define CPU_BIG_ENDIAN                           TRUE
320#define CPU_LITTLE_ENDIAN                        FALSE
321
322/*
323 *  The following defines the number of bits actually used in the
324 *  interrupt field of the task mode.  How those bits map to the
325 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
326 *
327 *  MOXIE Specific Information:
328 *
329 *  XXX
330 */
331#define CPU_MODES_INTERRUPT_MASK   0x00000001
332
333#define CPU_PER_CPU_CONTROL_SIZE 0
334
335/*
336 *  Processor defined structures required for cpukit/score.
337 *
338 *  MOXIE Specific Information:
339 *
340 *  XXX
341 */
342
343/* may need to put some structures here.  */
344
345typedef struct {
346  /* There is no CPU specific per-CPU state */
347} CPU_Per_CPU_control;
348
349/*
350 * Contexts
351 *
352 *  Generally there are 2 types of context to save.
353 *     1. Interrupt registers to save
354 *     2. Task level registers to save
355 *
356 *  This means we have the following 3 context items:
357 *     1. task level context stuff::  Context_Control
358 *     2. floating point task stuff:: Context_Control_fp
359 *     3. special interrupt level context :: Context_Control_interrupt
360 *
361 *  On some processors, it is cost-effective to save only the callee
362 *  preserved registers during a task context switch.  This means
363 *  that the ISR code needs to save those registers which do not
364 *  persist across function calls.  It is not mandatory to make this
365 *  distinctions between the caller/callee saves registers for the
366 *  purpose of minimizing context saved during task switch and on interrupts.
367 *  If the cost of saving extra registers is minimal, simplicity is the
368 *  choice.  Save the same context on interrupt entry as for tasks in
369 *  this case.
370 *
371 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
372 *  care should be used in designing the context area.
373 *
374 *  On some CPUs with hardware floating point support, the Context_Control_fp
375 *  structure will not be used or it simply consist of an array of a
376 *  fixed number of bytes.   This is done when the floating point context
377 *  is dumped by a "FP save context" type instruction and the format
378 *  is not really defined by the CPU.  In this case, there is no need
379 *  to figure out the exact format -- only the size.  Of course, although
380 *  this is enough information for RTEMS, it is probably not enough for
381 *  a debugger such as gdb.  But that is another problem.
382 *
383 *  MOXIE Specific Information:
384 *
385 *  XXX
386 */
387
388#define nogap __attribute__ ((packed))
389
390typedef struct {
391    void        *fp nogap;
392    void        *sp nogap;
393    uint32_t    r0 nogap;
394    uint32_t    r1 nogap;
395    uint32_t    r2 nogap;
396    uint32_t    r3 nogap;
397    uint32_t    r4 nogap;
398    uint32_t    r5 nogap;
399    uint32_t    r6 nogap;
400    uint32_t    r7 nogap;
401    uint32_t    r8 nogap;
402    uint32_t    r9 nogap;
403    uint32_t    r10 nogap;
404    uint32_t    r11 nogap;
405    uint32_t    r12 nogap;
406    uint32_t    r13 nogap;
407} Context_Control;
408
409#define _CPU_Context_Get_SP( _context ) \
410  (_context)->sp
411
412typedef struct {
413    double      some_float_register[2];
414} Context_Control_fp;
415
416typedef struct {
417    uint32_t   special_interrupt_register;
418} CPU_Interrupt_frame;
419
420/*
421 *  This variable is optional.  It is used on CPUs on which it is difficult
422 *  to generate an "uninitialized" FP context.  It is filled in by
423 *  _CPU_Initialize and copied into the task's FP context area during
424 *  _CPU_Context_Initialize.
425 *
426 *  MOXIE Specific Information:
427 *
428 *  XXX
429 */
430SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
431
432/*
433 *  Nothing prevents the porter from declaring more CPU specific variables.
434 *
435 *  MOXIE Specific Information:
436 *
437 *  XXX
438 */
439
440/*
441 *  The size of the floating point context area.  On some CPUs this
442 *  will not be a "sizeof" because the format of the floating point
443 *  area is not defined -- only the size is.  This is usually on
444 *  CPUs with a "floating point save context" instruction.
445 *
446 *  MOXIE Specific Information:
447 *
448 *  XXX
449 */
450#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
451
452/*
453 *  Amount of extra stack (above minimum stack size) required by
454 *  system initialization thread.  Remember that in a multiprocessor
455 *  system the system intialization thread becomes the MP server thread.
456 *
457 *  MOXIE Specific Information:
458 *
459 *  It is highly unlikely the MOXIE will get used in a multiprocessor system.
460 */
461#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
462
463/*
464 *  This defines the number of entries in the ISR_Vector_table managed
465 *  by RTEMS.
466 *
467 *  MOXIE Specific Information:
468 *
469 *  XXX
470 */
471#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
472#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER \
473    (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
474
475/*
476 *  This is defined if the port has a special way to report the ISR nesting
477 *  level.  Most ports maintain the variable _ISR_Nest_level.
478 */
479#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
480
481/*
482 *  Should be large enough to run all RTEMS tests.  This ensures
483 *  that a "reasonable" small application should not have any problems.
484 *
485 *  MOXIE Specific Information:
486 *
487 *  XXX
488 */
489#define CPU_STACK_MINIMUM_SIZE          (1536)
490
491/**
492 * Size of a pointer.
493 *
494 * This must be an integer literal that can be used by the assembler.  This
495 * value will be used to calculate offsets of structure members.  These
496 * offsets will be used in assembler code.
497 */
498#define CPU_SIZEOF_POINTER         4
499
500/*
501 *  CPU's worst alignment requirement for data types on a byte boundary.  This
502 *  alignment does not take into account the requirements for the stack.
503 *
504 *  MOXIE Specific Information:
505 *
506 *  XXX
507 */
508#define CPU_ALIGNMENT              8
509
510/*
511 *  This number corresponds to the byte alignment requirement for the
512 *  heap handler.  This alignment requirement may be stricter than that
513 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
514 *  common for the heap to follow the same alignment requirement as
515 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
516 *  then this should be set to CPU_ALIGNMENT.
517 *
518 *  NOTE:  This does not have to be a power of 2.  It does have to
519 *         be greater or equal to than CPU_ALIGNMENT.
520 *
521 *  MOXIE Specific Information:
522 *
523 *  XXX
524 */
525#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
526
527/*
528 *  This number corresponds to the byte alignment requirement for memory
529 *  buffers allocated by the partition manager.  This alignment requirement
530 *  may be stricter than that for the data types alignment specified by
531 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
532 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
533 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
534 *
535 *  NOTE:  This does not have to be a power of 2.  It does have to
536 *         be greater or equal to than CPU_ALIGNMENT.
537 *
538 *  MOXIE Specific Information:
539 *
540 *  XXX
541 */
542#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
543
544/*
545 *  This number corresponds to the byte alignment requirement for the
546 *  stack.  This alignment requirement may be stricter than that for the
547 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
548 *  is strict enough for the stack, then this should be set to 0.
549 *
550 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
551 *
552 *  MOXIE Specific Information:
553 *
554 *  XXX
555 */
556#define CPU_STACK_ALIGNMENT        0
557
558/*
559 *  ISR handler macros
560 */
561
562/*
563 *  Support routine to initialize the RTEMS vector table after it is allocated.
564 */
565#define _CPU_Initialize_vectors()
566
567/*
568 *  Disable all interrupts for an RTEMS critical section.  The previous
569 *  level is returned in _level.
570 *
571 *  MOXIE Specific Information:
572 *
573 *  XXX
574 */
575#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0
576
577/*
578 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
579 *  This indicates the end of an RTEMS critical section.  The parameter
580 *  _level is not modified.
581 *
582 *  MOXIE Specific Information:
583 *
584 *  XXX
585 */
586#define _CPU_ISR_Enable( _isr_cookie )
587
588/*
589 *  This temporarily restores the interrupt to _level before immediately
590 *  disabling them again.  This is used to divide long RTEMS critical
591 *  sections into two or more parts.  The parameter _level is not
592 *  modified.
593 *
594 *  MOXIE Specific Information:
595 *
596 *  XXX
597 */
598#define _CPU_ISR_Flash( _isr_cookie )
599
600/*
601 *  Map interrupt level in task mode onto the hardware that the CPU
602 *  actually provides.  Currently, interrupt levels which do not
603 *  map onto the CPU in a generic fashion are undefined.  Someday,
604 *  it would be nice if these were "mapped" by the application
605 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
606 *  8 - 255 would be available for bsp/application specific meaning.
607 *  This could be used to manage a programmable interrupt controller
608 *  via the rtems_task_mode directive.
609 *
610 *  MOXIE Specific Information:
611 *
612 *  XXX
613 */
614#define _CPU_ISR_Set_level( _new_level )        \
615  {                                                     \
616    if (_new_level)   asm volatile ( "nop\n" );         \
617    else              asm volatile ( "nop\n" );         \
618  }
619
620uint32_t   _CPU_ISR_Get_level( void );
621
622/* end of ISR handler macros */
623
624/* Context handler macros */
625
626/*
627 *  Initialize the context to a state suitable for starting a
628 *  task after a context restore operation.  Generally, this
629 *  involves:
630 *
631 *     - setting a starting address
632 *     - preparing the stack
633 *     - preparing the stack and frame pointers
634 *     - setting the proper interrupt level in the context
635 *     - initializing the floating point context
636 *
637 *  This routine generally does not set any unnecessary register
638 *  in the context.  The state of the "general data" registers is
639 *  undefined at task start time.
640 *
641 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
642 *        point thread.  This is typically only used on CPUs where the
643 *        FPU may be easily disabled by software such as on the SPARC
644 *        where the PSR contains an enable FPU bit.
645 *
646 *  MOXIE Specific Information:
647 *
648 *  XXX
649 */
650#define CPU_CCR_INTERRUPTS_ON  0x80
651#define CPU_CCR_INTERRUPTS_OFF 0x00
652
653#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
654                                 _isr, _entry_point, _is_fp, _tls_area ) \
655  /* Locate Me */                                                  \
656  do {                                                             \
657    uintptr_t   _stack;                                            \
658                                                                   \
659    _stack = ((uintptr_t)(_stack_base)) + (_size) - 8;             \
660    *((proc_ptr *)(_stack)) = (_entry_point);                      \
661    _stack -= 4;                                                   \
662    (_the_context)->fp = (void *)_stack;                           \
663    (_the_context)->sp = (void *)_stack;                           \
664  } while (0)
665
666
667/*
668 *  This routine is responsible for somehow restarting the currently
669 *  executing task.  If you are lucky, then all that is necessary
670 *  is restoring the context.  Otherwise, there will need to be
671 *  a special assembly routine which does something special in this
672 *  case.  Context_Restore should work most of the time.  It will
673 *  not work if restarting self conflicts with the stack frame
674 *  assumptions of restoring a context.
675 *
676 *  MOXIE Specific Information:
677 *
678 *  XXX
679 */
680#define _CPU_Context_Restart_self( _the_context ) \
681   _CPU_Context_restore( (_the_context) );
682
683/*
684 *  The purpose of this macro is to allow the initial pointer into
685 *  a floating point context area (used to save the floating point
686 *  context) to be at an arbitrary place in the floating point
687 *  context area.
688 *
689 *  This is necessary because some FP units are designed to have
690 *  their context saved as a stack which grows into lower addresses.
691 *  Other FP units can be saved by simply moving registers into offsets
692 *  from the base of the context area.  Finally some FP units provide
693 *  a "dump context" instruction which could fill in from high to low
694 *  or low to high based on the whim of the CPU designers.
695 *
696 *  MOXIE Specific Information:
697 *
698 *  XXX
699 */
700#define _CPU_Context_Fp_start( _base, _offset ) \
701   ( (void *) (_base) + (_offset) )
702
703/*
704 *  This routine initializes the FP context area passed to it to.
705 *  There are a few standard ways in which to initialize the
706 *  floating point context.  The code included for this macro assumes
707 *  that this is a CPU in which a "initial" FP context was saved into
708 *  _CPU_Null_fp_context and it simply copies it to the destination
709 *  context passed to it.
710 *
711 *  Other models include (1) not doing anything, and (2) putting
712 *  a "null FP status word" in the correct place in the FP context.
713 *
714 *  MOXIE Specific Information:
715 *
716 *  XXX
717 */
718#define _CPU_Context_Initialize_fp( _destination ) \
719  { \
720   *(*(_destination)) = _CPU_Null_fp_context; \
721  }
722
723/* end of Context handler macros */
724
725/* Fatal Error manager macros */
726
727/*
728 *  This routine copies _error into a known place -- typically a stack
729 *  location or a register, optionally disables interrupts, and
730 *  halts/stops the CPU.
731 *
732 *  MOXIE Specific Information:
733 *
734 *  XXX
735 */
736#define _CPU_Fatal_halt( _source, _error ) \
737        printk("Fatal Error %d.%d Halted\n",_source,_error); \
738        for(;;)
739
740/* end of Fatal Error manager macros */
741
742/* Bitfield handler macros */
743
744/*
745 *  This routine sets _output to the bit number of the first bit
746 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
747 *  This type may be either 16 or 32 bits wide although only the 16
748 *  least significant bits will be used.
749 *
750 *  There are a number of variables in using a "find first bit" type
751 *  instruction.
752 *
753 *    (1) What happens when run on a value of zero?
754 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
755 *    (3) The numbering may be zero or one based.
756 *    (4) The "find first bit" instruction may search from MSB or LSB.
757 *
758 *  RTEMS guarantees that (1) will never happen so it is not a concern.
759 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
760 *  _CPU_Priority_bits_index().  These three form a set of routines
761 *  which must logically operate together.  Bits in the _value are
762 *  set and cleared based on masks built by _CPU_Priority_mask().
763 *  The basic major and minor values calculated by _Priority_Major()
764 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
765 *  to properly range between the values returned by the "find first bit"
766 *  instruction.  This makes it possible for _Priority_Get_highest() to
767 *  calculate the major and directly index into the minor table.
768 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
769 *  is the first bit found.
770 *
771 *  This entire "find first bit" and mapping process depends heavily
772 *  on the manner in which a priority is broken into a major and minor
773 *  components with the major being the 4 MSB of a priority and minor
774 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
775 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
776 *  to the lowest priority.
777 *
778 *  If your CPU does not have a "find first bit" instruction, then
779 *  there are ways to make do without it.  Here are a handful of ways
780 *  to implement this in software:
781 *
782 *    - a series of 16 bit test instructions
783 *    - a "binary search using if's"
784 *    - _number = 0
785 *      if _value > 0x00ff
786 *        _value >>=8
787 *        _number = 8;
788 *
789 *      if _value > 0x0000f
790 *        _value >=8
791 *        _number += 4
792 *
793 *      _number += bit_set_table[ _value ]
794 *
795 *    where bit_set_table[ 16 ] has values which indicate the first
796 *      bit set
797 *
798 *  MOXIE Specific Information:
799 *
800 *  XXX
801 */
802#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
803#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
804
805#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
806
807#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
808  { \
809    (_output) = 0;   /* do something to prevent warnings */ \
810  }
811
812#endif
813
814/* end of Bitfield handler macros */
815
816/*
817 *  This routine builds the mask which corresponds to the bit fields
818 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
819 *  for that routine.
820 *
821 *  MOXIE Specific Information:
822 *
823 *  XXX
824 */
825#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
826
827#define _CPU_Priority_Mask( _bit_number ) \
828  ( 1 << (_bit_number) )
829
830#endif
831
832/*
833 *  This routine translates the bit numbers returned by
834 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
835 *  a major or minor component of a priority.  See the discussion
836 *  for that routine.
837 *
838 *  MOXIE Specific Information:
839 *
840 *  XXX
841 */
842#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
843
844#define _CPU_Priority_bits_index( _priority ) \
845  (_priority)
846
847#endif
848
849/* end of Priority handler macros */
850
851/* functions */
852
853/*
854 *  _CPU_Initialize
855 *
856 *  This routine performs CPU dependent initialization.
857 *
858 *  MOXIE Specific Information:
859 *
860 *  XXX
861 */
862void _CPU_Initialize(void);
863
864/*
865 *  _CPU_ISR_install_raw_handler
866 *
867 *  This routine installs a "raw" interrupt handler directly into the
868 *  processor's vector table.
869 *
870 *  MOXIE Specific Information:
871 *
872 *  XXX
873 */
874void _CPU_ISR_install_raw_handler(
875  uint32_t    vector,
876  proc_ptr    new_handler,
877  proc_ptr   *old_handler
878);
879
880/*
881 *  _CPU_ISR_install_vector
882 *
883 *  This routine installs an interrupt vector.
884 *
885 *  MOXIE Specific Information:
886 *
887 *  XXX
888 */
889void _CPU_ISR_install_vector(
890  uint32_t    vector,
891  proc_ptr    new_handler,
892  proc_ptr   *old_handler
893);
894
895/*
896 *  _CPU_Install_interrupt_stack
897 *
898 *  This routine installs the hardware interrupt stack pointer.
899 *
900 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
901 *         is TRUE.
902 *
903 *  MOXIE Specific Information:
904 *
905 *  XXX
906 */
907void _CPU_Install_interrupt_stack( void );
908
909/*
910 *  _CPU_Internal_threads_Idle_thread_body
911 *
912 *  This routine is the CPU dependent IDLE thread body.
913 *
914 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
915 *         is TRUE.
916 *
917 *  MOXIE Specific Information:
918 *
919 *  XXX
920 */
921void *_CPU_Thread_Idle_body( uint32_t );
922
923/*
924 *  _CPU_Context_switch
925 *
926 *  This routine switches from the run context to the heir context.
927 *
928 *  MOXIE Specific Information:
929 *
930 *  XXX
931 */
932void _CPU_Context_switch(
933  Context_Control  *run,
934  Context_Control  *heir
935);
936
937/*
938 *  _CPU_Context_restore
939 *
940 *  This routine is generallu used only to restart self in an
941 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
942 *
943 *  NOTE: May be unnecessary to reload some registers.
944 *
945 *  MOXIE Specific Information:
946 *
947 *  XXX
948 */
949void _CPU_Context_restore(
950  Context_Control *new_context
951);
952
953/*
954 *  _CPU_Context_save_fp
955 *
956 *  This routine saves the floating point context passed to it.
957 *
958 *  MOXIE Specific Information:
959 *
960 *  XXX
961 */
962void _CPU_Context_save_fp(
963  Context_Control_fp **fp_context_ptr
964);
965
966/*
967 *  _CPU_Context_restore_fp
968 *
969 *  This routine restores the floating point context passed to it.
970 *
971 *  MOXIE Specific Information:
972 *
973 *  XXX
974 */
975void _CPU_Context_restore_fp(
976  Context_Control_fp **fp_context_ptr
977);
978
979static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
980{
981  /* TODO */
982}
983
984static inline void _CPU_Context_validate( uintptr_t pattern )
985{
986  while (1) {
987    /* TODO */
988  }
989}
990
991/**
992 * @brief The set of registers that specifies the complete processor state.
993 *
994 * The CPU exception frame may be available in fatal error conditions like for
995 * example illegal opcodes, instruction fetch errors, or data access errors.
996 *
997 * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and
998 * rtems_exception_frame_print().
999 */
1000typedef struct {
1001  uint32_t integer_registers [16];
1002} CPU_Exception_frame;
1003
1004/**
1005 * @brief Prints the exception frame via printk().
1006 *
1007 * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
1008 */
1009void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1010
1011/*  The following routine swaps the endian format of an unsigned int.
1012 *  It must be static because it is referenced indirectly.
1013 *
1014 *  This version will work on any processor, but if there is a better
1015 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1016 *
1017 *     swap least significant two bytes with 16-bit rotate
1018 *     swap upper and lower 16-bits
1019 *     swap most significant two bytes with 16-bit rotate
1020 *
1021 *  Some CPUs have special instructions which swap a 32-bit quantity in
1022 *  a single instruction (e.g. i486).  It is probably best to avoid
1023 *  an "endian swapping control bit" in the CPU.  One good reason is
1024 *  that interrupts would probably have to be disabled to ensure that
1025 *  an interrupt does not try to access the same "chunk" with the wrong
1026 *  endian.  Another good reason is that on some CPUs, the endian bit
1027 *  endianness for ALL fetches -- both code and data -- so the code
1028 *  will be fetched incorrectly.
1029 *
1030 *  MOXIE Specific Information:
1031 *
1032 *  This is the generic implementation.
1033 */
1034static inline uint32_t   CPU_swap_u32(
1035  uint32_t   value
1036)
1037{
1038  uint32_t   byte1, byte2, byte3, byte4, swapped;
1039
1040  byte4 = (value >> 24) & 0xff;
1041  byte3 = (value >> 16) & 0xff;
1042  byte2 = (value >> 8)  & 0xff;
1043  byte1 =  value        & 0xff;
1044
1045  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1046  return( swapped );
1047}
1048
1049#define CPU_swap_u16( value ) \
1050  (((value&0xff) << 8) | ((value >> 8)&0xff))
1051
1052typedef uint32_t CPU_Counter_ticks;
1053
1054CPU_Counter_ticks _CPU_Counter_read( void );
1055
1056static inline CPU_Counter_ticks _CPU_Counter_difference(
1057  CPU_Counter_ticks second,
1058  CPU_Counter_ticks first
1059)
1060{
1061  return second - first;
1062}
1063
1064#ifdef __cplusplus
1065}
1066#endif
1067
1068#endif
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