source: rtems/cpukit/score/cpu/moxie/include/rtems/score/cpu.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 24.1 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the Moxie
7 *  processor.
8 *
9 *  Copyright (c) 2013  Anthony Green
10 *
11 *  Based on code with the following copyright..
12 *  COPYRIGHT (c) 1989-2006, 2010.
13 *  On-Line Applications Research Corporation (OAR).
14 *
15 *  The license and distribution terms for this file may be
16 *  found in the file LICENSE in this distribution or at
17 *  http://www.rtems.org/license/LICENSE.
18 */
19
20#ifndef _RTEMS_SCORE_CPU_H
21#define _RTEMS_SCORE_CPU_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#include <rtems/score/types.h>
28#include <rtems/score/moxie.h>  /* pick up machine definitions */
29
30#include <rtems/bspIo.h>        /* printk */
31
32/* conditional compilation parameters */
33
34/*
35 *  Should this target use 16 or 32 bit object Ids?
36 *
37 */
38#define RTEMS_USE_32_BIT_OBJECT
39
40/*
41 *  Does RTEMS manage a dedicated interrupt stack in software?
42 *
43 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
44 *  If FALSE, nothing is done.
45 *
46 *  If the CPU supports a dedicated interrupt stack in hardware,
47 *  then it is generally the responsibility of the BSP to allocate it
48 *  and set it up.
49 *
50 *  If the CPU does not support a dedicated interrupt stack, then
51 *  the porter has two options: (1) execute interrupts on the
52 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
53 *  interrupt stack.
54 *
55 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
56 *
57 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
58 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
59 *  possible that both are FALSE for a particular CPU.  Although it
60 *  is unclear what that would imply about the interrupt processing
61 *  procedure on that CPU.
62 *
63 *  MOXIE Specific Information:
64 *
65 *  XXX
66 */
67#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
68
69/*
70 *  Does the CPU follow the simple vectored interrupt model?
71 *
72 *  If TRUE, then RTEMS allocates the vector table it internally manages.
73 *  If FALSE, then the BSP is assumed to allocate and manage the vector
74 *  table
75 *
76 *  MOXIE Specific Information:
77 *
78 *  XXX document implementation including references if appropriate
79 */
80#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
81
82/*
83 *  Does this CPU have hardware support for a dedicated interrupt stack?
84 *
85 *  If TRUE, then it must be installed during initialization.
86 *  If FALSE, then no installation is performed.
87 *
88 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
89 *
90 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
91 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
92 *  possible that both are FALSE for a particular CPU.  Although it
93 *  is unclear what that would imply about the interrupt processing
94 *  procedure on that CPU.
95 *
96 *  MOXIE Specific Information:
97 *
98 *  XXX
99 */
100#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
101
102/*
103 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
104 *
105 *  If TRUE, then the memory is allocated during initialization.
106 *  If FALSE, then the memory is allocated during initialization.
107 *
108 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
109 *
110 *  MOXIE Specific Information:
111 *
112 *  XXX
113 */
114#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
115
116/*
117 *  Does the CPU have hardware floating point?
118 *
119 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
120 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
121 *
122 *  If there is a FP coprocessor such as the i387 or mc68881, then
123 *  the answer is TRUE.
124 *
125 *  The macro name "MOXIE_HAS_FPU" should be made CPU specific.
126 *  It indicates whether or not this CPU model has FP support.  For
127 *  example, it would be possible to have an i386_nofp CPU model
128 *  which set this to false to indicate that you have an i386 without
129 *  an i387 and wish to leave floating point support out of RTEMS.
130 *
131 *  MOXIE Specific Information:
132 *
133 *  XXX
134 */
135#define CPU_HARDWARE_FP     FALSE
136
137/*
138 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
139 *
140 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
141 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
142 *
143 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
144 *
145 *  MOXIE Specific Information:
146 *
147 *  XXX
148 */
149#define CPU_ALL_TASKS_ARE_FP     FALSE
150
151/*
152 *  Should the IDLE task have a floating point context?
153 *
154 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
155 *  and it has a floating point context which is switched in and out.
156 *  If FALSE, then the IDLE task does not have a floating point context.
157 *
158 *  Setting this to TRUE negatively impacts the time required to preempt
159 *  the IDLE task from an interrupt because the floating point context
160 *  must be saved as part of the preemption.
161 *
162 *  MOXIE Specific Information:
163 *
164 *  XXX
165 */
166#define CPU_IDLE_TASK_IS_FP      FALSE
167
168/*
169 *  Should the saving of the floating point registers be deferred
170 *  until a context switch is made to another different floating point
171 *  task?
172 *
173 *  If TRUE, then the floating point context will not be stored until
174 *  necessary.  It will remain in the floating point registers and not
175 *  disturned until another floating point task is switched to.
176 *
177 *  If FALSE, then the floating point context is saved when a floating
178 *  point task is switched out and restored when the next floating point
179 *  task is restored.  The state of the floating point registers between
180 *  those two operations is not specified.
181 *
182 *  If the floating point context does NOT have to be saved as part of
183 *  interrupt dispatching, then it should be safe to set this to TRUE.
184 *
185 *  Setting this flag to TRUE results in using a different algorithm
186 *  for deciding when to save and restore the floating point context.
187 *  The deferred FP switch algorithm minimizes the number of times
188 *  the FP context is saved and restored.  The FP context is not saved
189 *  until a context switch is made to another, different FP task.
190 *  Thus in a system with only one FP task, the FP context will never
191 *  be saved or restored.
192 *
193 *  MOXIE Specific Information:
194 *
195 *  XXX
196 */
197#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
198
199#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
200
201/*
202 *  Does this port provide a CPU dependent IDLE task implementation?
203 *
204 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
205 *  must be provided and is the default IDLE thread body instead of
206 *  _Internal_threads_Idle_thread_body.
207 *
208 *  If FALSE, then use the generic IDLE thread body if the BSP does
209 *  not provide one.
210 *
211 *  This is intended to allow for supporting processors which have
212 *  a low power or idle mode.  When the IDLE thread is executed, then
213 *  the CPU can be powered down.
214 *
215 *  The order of precedence for selecting the IDLE thread body is:
216 *
217 *    1.  BSP provided
218 *    2.  CPU dependent (if provided)
219 *    3.  generic (if no BSP and no CPU dependent)
220 *
221 *  MOXIE Specific Information:
222 *
223 *  XXX
224 *  The port initially called a BSP dependent routine called
225 *  IDLE_Monitor.  The idle task body can be overridden by
226 *  the BSP in newer versions of RTEMS.
227 */
228#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
229
230/*
231 *  Does the stack grow up (toward higher addresses) or down
232 *  (toward lower addresses)?
233 *
234 *  If TRUE, then the grows upward.
235 *  If FALSE, then the grows toward smaller addresses.
236 *
237 *  MOXIE Specific Information:
238 *
239 *  XXX
240 */
241#define CPU_STACK_GROWS_UP               FALSE
242
243/* FIXME: Is this the right value? */
244#define CPU_CACHE_LINE_BYTES 32
245
246#define CPU_STRUCTURE_ALIGNMENT
247
248/*
249 *  The following defines the number of bits actually used in the
250 *  interrupt field of the task mode.  How those bits map to the
251 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
252 *
253 *  MOXIE Specific Information:
254 *
255 *  XXX
256 */
257#define CPU_MODES_INTERRUPT_MASK   0x00000001
258
259#define CPU_MAXIMUM_PROCESSORS 32
260
261/*
262 *  Processor defined structures required for cpukit/score.
263 *
264 *  MOXIE Specific Information:
265 *
266 *  XXX
267 */
268
269/* may need to put some structures here.  */
270
271/*
272 * Contexts
273 *
274 *  Generally there are 2 types of context to save.
275 *     1. Interrupt registers to save
276 *     2. Task level registers to save
277 *
278 *  This means we have the following 3 context items:
279 *     1. task level context stuff::  Context_Control
280 *     2. floating point task stuff:: Context_Control_fp
281 *     3. special interrupt level context :: Context_Control_interrupt
282 *
283 *  On some processors, it is cost-effective to save only the callee
284 *  preserved registers during a task context switch.  This means
285 *  that the ISR code needs to save those registers which do not
286 *  persist across function calls.  It is not mandatory to make this
287 *  distinctions between the caller/callee saves registers for the
288 *  purpose of minimizing context saved during task switch and on interrupts.
289 *  If the cost of saving extra registers is minimal, simplicity is the
290 *  choice.  Save the same context on interrupt entry as for tasks in
291 *  this case.
292 *
293 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
294 *  care should be used in designing the context area.
295 *
296 *  On some CPUs with hardware floating point support, the Context_Control_fp
297 *  structure will not be used or it simply consist of an array of a
298 *  fixed number of bytes.   This is done when the floating point context
299 *  is dumped by a "FP save context" type instruction and the format
300 *  is not really defined by the CPU.  In this case, there is no need
301 *  to figure out the exact format -- only the size.  Of course, although
302 *  this is enough information for RTEMS, it is probably not enough for
303 *  a debugger such as gdb.  But that is another problem.
304 *
305 *  MOXIE Specific Information:
306 *
307 *  XXX
308 */
309
310#define nogap __attribute__ ((packed))
311
312typedef struct {
313    void        *fp nogap;
314    void        *sp nogap;
315    uint32_t    r0 nogap;
316    uint32_t    r1 nogap;
317    uint32_t    r2 nogap;
318    uint32_t    r3 nogap;
319    uint32_t    r4 nogap;
320    uint32_t    r5 nogap;
321    uint32_t    r6 nogap;
322    uint32_t    r7 nogap;
323    uint32_t    r8 nogap;
324    uint32_t    r9 nogap;
325    uint32_t    r10 nogap;
326    uint32_t    r11 nogap;
327    uint32_t    r12 nogap;
328    uint32_t    r13 nogap;
329} Context_Control;
330
331#define _CPU_Context_Get_SP( _context ) \
332  (_context)->sp
333
334typedef struct {
335    double      some_float_register[2];
336} Context_Control_fp;
337
338typedef struct {
339    uint32_t   special_interrupt_register;
340} CPU_Interrupt_frame;
341
342/*
343 *  Nothing prevents the porter from declaring more CPU specific variables.
344 *
345 *  MOXIE Specific Information:
346 *
347 *  XXX
348 */
349
350/*
351 *  The size of the floating point context area.  On some CPUs this
352 *  will not be a "sizeof" because the format of the floating point
353 *  area is not defined -- only the size is.  This is usually on
354 *  CPUs with a "floating point save context" instruction.
355 *
356 *  MOXIE Specific Information:
357 *
358 *  XXX
359 */
360#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
361
362/*
363 *  Amount of extra stack (above minimum stack size) required by
364 *  system initialization thread.  Remember that in a multiprocessor
365 *  system the system intialization thread becomes the MP server thread.
366 *
367 *  MOXIE Specific Information:
368 *
369 *  It is highly unlikely the MOXIE will get used in a multiprocessor system.
370 */
371#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
372
373/*
374 *  This defines the number of entries in the ISR_Vector_table managed
375 *  by RTEMS.
376 *
377 *  MOXIE Specific Information:
378 *
379 *  XXX
380 */
381#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
382#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER \
383    (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
384
385/*
386 *  This is defined if the port has a special way to report the ISR nesting
387 *  level.  Most ports maintain the variable _ISR_Nest_level.
388 */
389#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
390
391/*
392 *  Should be large enough to run all RTEMS tests.  This ensures
393 *  that a "reasonable" small application should not have any problems.
394 *
395 *  MOXIE Specific Information:
396 *
397 *  XXX
398 */
399#define CPU_STACK_MINIMUM_SIZE          (1536)
400
401/**
402 * Size of a pointer.
403 *
404 * This must be an integer literal that can be used by the assembler.  This
405 * value will be used to calculate offsets of structure members.  These
406 * offsets will be used in assembler code.
407 */
408#define CPU_SIZEOF_POINTER         4
409
410/*
411 *  CPU's worst alignment requirement for data types on a byte boundary.  This
412 *  alignment does not take into account the requirements for the stack.
413 *
414 *  MOXIE Specific Information:
415 *
416 *  XXX
417 */
418#define CPU_ALIGNMENT              8
419
420/*
421 *  This number corresponds to the byte alignment requirement for the
422 *  heap handler.  This alignment requirement may be stricter than that
423 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
424 *  common for the heap to follow the same alignment requirement as
425 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
426 *  then this should be set to CPU_ALIGNMENT.
427 *
428 *  NOTE:  This does not have to be a power of 2.  It does have to
429 *         be greater or equal to than CPU_ALIGNMENT.
430 *
431 *  MOXIE Specific Information:
432 *
433 *  XXX
434 */
435#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
436
437/*
438 *  This number corresponds to the byte alignment requirement for memory
439 *  buffers allocated by the partition manager.  This alignment requirement
440 *  may be stricter than that for the data types alignment specified by
441 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
442 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
443 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
444 *
445 *  NOTE:  This does not have to be a power of 2.  It does have to
446 *         be greater or equal to than CPU_ALIGNMENT.
447 *
448 *  MOXIE Specific Information:
449 *
450 *  XXX
451 */
452#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
453
454/*
455 *  This number corresponds to the byte alignment requirement for the
456 *  stack.  This alignment requirement may be stricter than that for the
457 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
458 *  is strict enough for the stack, then this should be set to 0.
459 *
460 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
461 *
462 *  MOXIE Specific Information:
463 *
464 *  XXX
465 */
466#define CPU_STACK_ALIGNMENT        0
467
468/*
469 *  ISR handler macros
470 */
471
472/*
473 *  Support routine to initialize the RTEMS vector table after it is allocated.
474 */
475#define _CPU_Initialize_vectors()
476
477/*
478 *  Disable all interrupts for an RTEMS critical section.  The previous
479 *  level is returned in _level.
480 *
481 *  MOXIE Specific Information:
482 *
483 *  TODO: As of 7 October 2014, this method is not implemented.
484 */
485#define _CPU_ISR_Disable( _isr_cookie ) \
486  do { \
487    (_isr_cookie) = 0; \
488  } while (0)
489
490/*
491 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
492 *  This indicates the end of an RTEMS critical section.  The parameter
493 *  _level is not modified.
494 *
495 *  MOXIE Specific Information:
496 *
497 *  TODO: As of 7 October 2014, this method is not implemented.
498 */
499#define _CPU_ISR_Enable( _isr_cookie ) \
500  do { \
501    (_isr_cookie) = (_isr_cookie); \
502  } while (0)
503
504/*
505 *  This temporarily restores the interrupt to _level before immediately
506 *  disabling them again.  This is used to divide long RTEMS critical
507 *  sections into two or more parts.  The parameter _level is not
508 *  modified.
509 *
510 *  MOXIE Specific Information:
511 *
512 *  TODO: As of 7 October 2014, this method is not implemented.
513 */
514#define _CPU_ISR_Flash( _isr_cookie ) \
515  do { \
516    _CPU_ISR_Enable( _isr_cookie ); \
517    _CPU_ISR_Disable( _isr_cookie ); \
518  } while (0)
519
520RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
521{
522  return true;
523}
524
525/*
526 *  Map interrupt level in task mode onto the hardware that the CPU
527 *  actually provides.  Currently, interrupt levels which do not
528 *  map onto the CPU in a generic fashion are undefined.  Someday,
529 *  it would be nice if these were "mapped" by the application
530 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
531 *  8 - 255 would be available for bsp/application specific meaning.
532 *  This could be used to manage a programmable interrupt controller
533 *  via the rtems_task_mode directive.
534 *
535 *  MOXIE Specific Information:
536 *
537 *  TODO: As of 7 October 2014, this method is not implemented.
538 */
539#define _CPU_ISR_Set_level( _new_level )        \
540  {                                                     \
541    if (_new_level)   asm volatile ( "nop\n" );         \
542    else              asm volatile ( "nop\n" );         \
543  }
544
545uint32_t   _CPU_ISR_Get_level( void );
546
547/* end of ISR handler macros */
548
549/* Context handler macros */
550
551/*
552 *  Initialize the context to a state suitable for starting a
553 *  task after a context restore operation.  Generally, this
554 *  involves:
555 *
556 *     - setting a starting address
557 *     - preparing the stack
558 *     - preparing the stack and frame pointers
559 *     - setting the proper interrupt level in the context
560 *     - initializing the floating point context
561 *
562 *  This routine generally does not set any unnecessary register
563 *  in the context.  The state of the "general data" registers is
564 *  undefined at task start time.
565 *
566 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
567 *        point thread.  This is typically only used on CPUs where the
568 *        FPU may be easily disabled by software such as on the SPARC
569 *        where the PSR contains an enable FPU bit.
570 *
571 *  MOXIE Specific Information:
572 *
573 *  TODO: As of 7 October 2014, this method does not ensure that the context
574 *  is set up with interrupts disabled/enabled as requested.
575 */
576#define CPU_CCR_INTERRUPTS_ON  0x80
577#define CPU_CCR_INTERRUPTS_OFF 0x00
578
579#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
580                                 _isr, _entry_point, _is_fp, _tls_area ) \
581  /* Locate Me */                                                  \
582  do {                                                             \
583    uintptr_t   _stack;                                            \
584                                                                   \
585    (void) _is_fp; /* avoid warning for being unused */            \
586    (void) _isr;   /* avoid warning for being unused */            \
587    _stack = ((uintptr_t)(_stack_base)) + (_size) - 8;             \
588    *((proc_ptr *)(_stack)) = (_entry_point);                      \
589    _stack -= 4;                                                   \
590    (_the_context)->fp = (void *)_stack;                           \
591    (_the_context)->sp = (void *)_stack;                           \
592  } while (0)
593
594
595/*
596 *  This routine is responsible for somehow restarting the currently
597 *  executing task.  If you are lucky, then all that is necessary
598 *  is restoring the context.  Otherwise, there will need to be
599 *  a special assembly routine which does something special in this
600 *  case.  Context_Restore should work most of the time.  It will
601 *  not work if restarting self conflicts with the stack frame
602 *  assumptions of restoring a context.
603 *
604 *  MOXIE Specific Information:
605 *
606 *  XXX
607 */
608#define _CPU_Context_Restart_self( _the_context ) \
609   _CPU_Context_restore( (_the_context) );
610
611#define _CPU_Context_Initialize_fp( _destination ) \
612  memset( *( _destination ), 0, CPU_CONTEXT_FP_SIZE );
613
614/* end of Context handler macros */
615
616/* Fatal Error manager macros */
617
618/*
619 *  This routine copies _error into a known place -- typically a stack
620 *  location or a register, optionally disables interrupts, and
621 *  halts/stops the CPU.
622 *
623 *  MOXIE Specific Information:
624 *
625 *  XXX
626 */
627#define _CPU_Fatal_halt( _source, _error ) \
628        printk("Fatal Error %d.%lu Halted\n",_source,_error); \
629        for(;;)
630
631/* end of Fatal Error manager macros */
632
633#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
634
635/* functions */
636
637/*
638 *  _CPU_Initialize
639 *
640 *  This routine performs CPU dependent initialization.
641 *
642 *  MOXIE Specific Information:
643 *
644 *  XXX
645 */
646void _CPU_Initialize(void);
647
648/*
649 *  _CPU_ISR_install_raw_handler
650 *
651 *  This routine installs a "raw" interrupt handler directly into the
652 *  processor's vector table.
653 *
654 *  MOXIE Specific Information:
655 *
656 *  XXX
657 */
658void _CPU_ISR_install_raw_handler(
659  uint32_t    vector,
660  proc_ptr    new_handler,
661  proc_ptr   *old_handler
662);
663
664/*
665 *  _CPU_ISR_install_vector
666 *
667 *  This routine installs an interrupt vector.
668 *
669 *  MOXIE Specific Information:
670 *
671 *  XXX
672 */
673void _CPU_ISR_install_vector(
674  uint32_t    vector,
675  proc_ptr    new_handler,
676  proc_ptr   *old_handler
677);
678
679/*
680 *  _CPU_Install_interrupt_stack
681 *
682 *  This routine installs the hardware interrupt stack pointer.
683 *
684 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
685 *         is TRUE.
686 *
687 *  MOXIE Specific Information:
688 *
689 *  XXX
690 */
691void _CPU_Install_interrupt_stack( void );
692
693/*
694 *  _CPU_Internal_threads_Idle_thread_body
695 *
696 *  This routine is the CPU dependent IDLE thread body.
697 *
698 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
699 *         is TRUE.
700 *
701 *  MOXIE Specific Information:
702 *
703 *  XXX
704 */
705void *_CPU_Thread_Idle_body( uint32_t );
706
707/*
708 *  _CPU_Context_switch
709 *
710 *  This routine switches from the run context to the heir context.
711 *
712 *  MOXIE Specific Information:
713 *
714 *  XXX
715 */
716void _CPU_Context_switch(
717  Context_Control  *run,
718  Context_Control  *heir
719);
720
721/*
722 *  _CPU_Context_restore
723 *
724 *  This routine is generallu used only to restart self in an
725 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
726 *
727 *  NOTE: May be unnecessary to reload some registers.
728 *
729 *  MOXIE Specific Information:
730 *
731 *  XXX
732 */
733void _CPU_Context_restore(
734  Context_Control *new_context
735) RTEMS_NO_RETURN;
736
737/*
738 *  _CPU_Context_save_fp
739 *
740 *  This routine saves the floating point context passed to it.
741 *
742 *  MOXIE Specific Information:
743 *
744 *  XXX
745 */
746void _CPU_Context_save_fp(
747  Context_Control_fp **fp_context_ptr
748);
749
750/*
751 *  _CPU_Context_restore_fp
752 *
753 *  This routine restores the floating point context passed to it.
754 *
755 *  MOXIE Specific Information:
756 *
757 *  XXX
758 */
759void _CPU_Context_restore_fp(
760  Context_Control_fp **fp_context_ptr
761);
762
763static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
764{
765  /* TODO */
766}
767
768static inline void _CPU_Context_validate( uintptr_t pattern )
769{
770  while (1) {
771    /* TODO */
772  }
773}
774
775/**
776 * @brief The set of registers that specifies the complete processor state.
777 *
778 * The CPU exception frame may be available in fatal error conditions like for
779 * example illegal opcodes, instruction fetch errors, or data access errors.
780 *
781 * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and
782 * rtems_exception_frame_print().
783 */
784typedef struct {
785  uint32_t integer_registers [16];
786} CPU_Exception_frame;
787
788/**
789 * @brief Prints the exception frame via printk().
790 *
791 * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
792 */
793void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
794
795/*  The following routine swaps the endian format of an unsigned int.
796 *  It must be static because it is referenced indirectly.
797 *
798 *  This version will work on any processor, but if there is a better
799 *  way for your CPU PLEASE use it.  The most common way to do this is to:
800 *
801 *     swap least significant two bytes with 16-bit rotate
802 *     swap upper and lower 16-bits
803 *     swap most significant two bytes with 16-bit rotate
804 *
805 *  Some CPUs have special instructions which swap a 32-bit quantity in
806 *  a single instruction (e.g. i486).  It is probably best to avoid
807 *  an "endian swapping control bit" in the CPU.  One good reason is
808 *  that interrupts would probably have to be disabled to ensure that
809 *  an interrupt does not try to access the same "chunk" with the wrong
810 *  endian.  Another good reason is that on some CPUs, the endian bit
811 *  endianness for ALL fetches -- both code and data -- so the code
812 *  will be fetched incorrectly.
813 *
814 *  MOXIE Specific Information:
815 *
816 *  This is the generic implementation.
817 */
818static inline uint32_t   CPU_swap_u32(
819  uint32_t   value
820)
821{
822  uint32_t   byte1, byte2, byte3, byte4, swapped;
823
824  byte4 = (value >> 24) & 0xff;
825  byte3 = (value >> 16) & 0xff;
826  byte2 = (value >> 8)  & 0xff;
827  byte1 =  value        & 0xff;
828
829  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
830  return( swapped );
831}
832
833#define CPU_swap_u16( value ) \
834  (((value&0xff) << 8) | ((value >> 8)&0xff))
835
836typedef uint32_t CPU_Counter_ticks;
837
838CPU_Counter_ticks _CPU_Counter_read( void );
839
840static inline CPU_Counter_ticks _CPU_Counter_difference(
841  CPU_Counter_ticks second,
842  CPU_Counter_ticks first
843)
844{
845  return second - first;
846}
847
848#ifdef __cplusplus
849}
850#endif
851
852#endif
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