source: rtems/cpukit/score/cpu/moxie/include/rtems/score/cpu.h @ 27bbc05

Last change on this file since 27bbc05 was 27bbc05, checked in by Sebastian Huber <sebastian.huber@…>, on Aug 2, 2018 at 12:49:01 PM

score: Remove CPU_PARTITION_ALIGNMENT

Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment
requirement is defined by the use of Chain_Node (consisting of two
pointers) to manage the free chain of partitions.

It seems that previously the condition

CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node)

was true on all CPU ports. Now, we need an additional check.

Update #3482.

  • Property mode set to 100644
File size: 21.2 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the Moxie
7 *  processor.
8 *
9 *  Copyright (c) 2013  Anthony Green
10 *
11 *  Based on code with the following copyright..
12 *  COPYRIGHT (c) 1989-2006, 2010.
13 *  On-Line Applications Research Corporation (OAR).
14 *
15 *  The license and distribution terms for this file may be
16 *  found in the file LICENSE in this distribution or at
17 *  http://www.rtems.org/license/LICENSE.
18 */
19
20#ifndef _RTEMS_SCORE_CPU_H
21#define _RTEMS_SCORE_CPU_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#include <rtems/score/basedefs.h>
28#include <rtems/score/moxie.h>  /* pick up machine definitions */
29
30#include <rtems/bspIo.h>        /* printk */
31
32/* conditional compilation parameters */
33
34/*
35 *  Should this target use 16 or 32 bit object Ids?
36 *
37 */
38#define RTEMS_USE_32_BIT_OBJECT
39
40/*
41 *  Does the CPU follow the simple vectored interrupt model?
42 *
43 *  If TRUE, then RTEMS allocates the vector table it internally manages.
44 *  If FALSE, then the BSP is assumed to allocate and manage the vector
45 *  table
46 *
47 *  MOXIE Specific Information:
48 *
49 *  XXX document implementation including references if appropriate
50 */
51#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
52
53/*
54 *  Does the CPU have hardware floating point?
55 *
56 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
57 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
58 *
59 *  If there is a FP coprocessor such as the i387 or mc68881, then
60 *  the answer is TRUE.
61 *
62 *  The macro name "MOXIE_HAS_FPU" should be made CPU specific.
63 *  It indicates whether or not this CPU model has FP support.  For
64 *  example, it would be possible to have an i386_nofp CPU model
65 *  which set this to false to indicate that you have an i386 without
66 *  an i387 and wish to leave floating point support out of RTEMS.
67 *
68 *  MOXIE Specific Information:
69 *
70 *  XXX
71 */
72#define CPU_HARDWARE_FP     FALSE
73
74/*
75 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
76 *
77 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
78 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
79 *
80 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
81 *
82 *  MOXIE Specific Information:
83 *
84 *  XXX
85 */
86#define CPU_ALL_TASKS_ARE_FP     FALSE
87
88/*
89 *  Should the IDLE task have a floating point context?
90 *
91 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
92 *  and it has a floating point context which is switched in and out.
93 *  If FALSE, then the IDLE task does not have a floating point context.
94 *
95 *  Setting this to TRUE negatively impacts the time required to preempt
96 *  the IDLE task from an interrupt because the floating point context
97 *  must be saved as part of the preemption.
98 *
99 *  MOXIE Specific Information:
100 *
101 *  XXX
102 */
103#define CPU_IDLE_TASK_IS_FP      FALSE
104
105/*
106 *  Should the saving of the floating point registers be deferred
107 *  until a context switch is made to another different floating point
108 *  task?
109 *
110 *  If TRUE, then the floating point context will not be stored until
111 *  necessary.  It will remain in the floating point registers and not
112 *  disturned until another floating point task is switched to.
113 *
114 *  If FALSE, then the floating point context is saved when a floating
115 *  point task is switched out and restored when the next floating point
116 *  task is restored.  The state of the floating point registers between
117 *  those two operations is not specified.
118 *
119 *  If the floating point context does NOT have to be saved as part of
120 *  interrupt dispatching, then it should be safe to set this to TRUE.
121 *
122 *  Setting this flag to TRUE results in using a different algorithm
123 *  for deciding when to save and restore the floating point context.
124 *  The deferred FP switch algorithm minimizes the number of times
125 *  the FP context is saved and restored.  The FP context is not saved
126 *  until a context switch is made to another, different FP task.
127 *  Thus in a system with only one FP task, the FP context will never
128 *  be saved or restored.
129 *
130 *  MOXIE Specific Information:
131 *
132 *  XXX
133 */
134#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
135
136#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
137
138/*
139 *  Does this port provide a CPU dependent IDLE task implementation?
140 *
141 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
142 *  must be provided and is the default IDLE thread body instead of
143 *  _Internal_threads_Idle_thread_body.
144 *
145 *  If FALSE, then use the generic IDLE thread body if the BSP does
146 *  not provide one.
147 *
148 *  This is intended to allow for supporting processors which have
149 *  a low power or idle mode.  When the IDLE thread is executed, then
150 *  the CPU can be powered down.
151 *
152 *  The order of precedence for selecting the IDLE thread body is:
153 *
154 *    1.  BSP provided
155 *    2.  CPU dependent (if provided)
156 *    3.  generic (if no BSP and no CPU dependent)
157 *
158 *  MOXIE Specific Information:
159 *
160 *  XXX
161 *  The port initially called a BSP dependent routine called
162 *  IDLE_Monitor.  The idle task body can be overridden by
163 *  the BSP in newer versions of RTEMS.
164 */
165#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
166
167/*
168 *  Does the stack grow up (toward higher addresses) or down
169 *  (toward lower addresses)?
170 *
171 *  If TRUE, then the grows upward.
172 *  If FALSE, then the grows toward smaller addresses.
173 *
174 *  MOXIE Specific Information:
175 *
176 *  XXX
177 */
178#define CPU_STACK_GROWS_UP               FALSE
179
180/* FIXME: Is this the right value? */
181#define CPU_CACHE_LINE_BYTES 32
182
183#define CPU_STRUCTURE_ALIGNMENT
184
185/*
186 *  The following defines the number of bits actually used in the
187 *  interrupt field of the task mode.  How those bits map to the
188 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
189 *
190 *  MOXIE Specific Information:
191 *
192 *  XXX
193 */
194#define CPU_MODES_INTERRUPT_MASK   0x00000001
195
196#define CPU_MAXIMUM_PROCESSORS 32
197
198/*
199 *  Processor defined structures required for cpukit/score.
200 *
201 *  MOXIE Specific Information:
202 *
203 *  XXX
204 */
205
206/* may need to put some structures here.  */
207
208/*
209 * Contexts
210 *
211 *  Generally there are 2 types of context to save.
212 *     1. Interrupt registers to save
213 *     2. Task level registers to save
214 *
215 *  This means we have the following 3 context items:
216 *     1. task level context stuff::  Context_Control
217 *     2. floating point task stuff:: Context_Control_fp
218 *     3. special interrupt level context :: Context_Control_interrupt
219 *
220 *  On some processors, it is cost-effective to save only the callee
221 *  preserved registers during a task context switch.  This means
222 *  that the ISR code needs to save those registers which do not
223 *  persist across function calls.  It is not mandatory to make this
224 *  distinctions between the caller/callee saves registers for the
225 *  purpose of minimizing context saved during task switch and on interrupts.
226 *  If the cost of saving extra registers is minimal, simplicity is the
227 *  choice.  Save the same context on interrupt entry as for tasks in
228 *  this case.
229 *
230 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
231 *  care should be used in designing the context area.
232 *
233 *  On some CPUs with hardware floating point support, the Context_Control_fp
234 *  structure will not be used or it simply consist of an array of a
235 *  fixed number of bytes.   This is done when the floating point context
236 *  is dumped by a "FP save context" type instruction and the format
237 *  is not really defined by the CPU.  In this case, there is no need
238 *  to figure out the exact format -- only the size.  Of course, although
239 *  this is enough information for RTEMS, it is probably not enough for
240 *  a debugger such as gdb.  But that is another problem.
241 *
242 *  MOXIE Specific Information:
243 *
244 *  XXX
245 */
246
247#define nogap __attribute__ ((packed))
248
249typedef struct {
250    void        *fp nogap;
251    void        *sp nogap;
252    uint32_t    r0 nogap;
253    uint32_t    r1 nogap;
254    uint32_t    r2 nogap;
255    uint32_t    r3 nogap;
256    uint32_t    r4 nogap;
257    uint32_t    r5 nogap;
258    uint32_t    r6 nogap;
259    uint32_t    r7 nogap;
260    uint32_t    r8 nogap;
261    uint32_t    r9 nogap;
262    uint32_t    r10 nogap;
263    uint32_t    r11 nogap;
264    uint32_t    r12 nogap;
265    uint32_t    r13 nogap;
266} Context_Control;
267
268#define _CPU_Context_Get_SP( _context ) \
269  (_context)->sp
270
271typedef struct {
272    double      some_float_register[2];
273} Context_Control_fp;
274
275typedef struct {
276    uint32_t   special_interrupt_register;
277} CPU_Interrupt_frame;
278
279/*
280 *  Nothing prevents the porter from declaring more CPU specific variables.
281 *
282 *  MOXIE Specific Information:
283 *
284 *  XXX
285 */
286
287/*
288 *  The size of the floating point context area.  On some CPUs this
289 *  will not be a "sizeof" because the format of the floating point
290 *  area is not defined -- only the size is.  This is usually on
291 *  CPUs with a "floating point save context" instruction.
292 *
293 *  MOXIE Specific Information:
294 *
295 *  XXX
296 */
297#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
298
299/*
300 *  Amount of extra stack (above minimum stack size) required by
301 *  system initialization thread.  Remember that in a multiprocessor
302 *  system the system intialization thread becomes the MP server thread.
303 *
304 *  MOXIE Specific Information:
305 *
306 *  It is highly unlikely the MOXIE will get used in a multiprocessor system.
307 */
308#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
309
310/*
311 *  This defines the number of entries in the ISR_Vector_table managed
312 *  by RTEMS.
313 *
314 *  MOXIE Specific Information:
315 *
316 *  XXX
317 */
318#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
319#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER \
320    (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
321
322/*
323 *  This is defined if the port has a special way to report the ISR nesting
324 *  level.  Most ports maintain the variable _ISR_Nest_level.
325 */
326#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
327
328/*
329 *  Should be large enough to run all RTEMS tests.  This ensures
330 *  that a "reasonable" small application should not have any problems.
331 *
332 *  MOXIE Specific Information:
333 *
334 *  XXX
335 */
336#define CPU_STACK_MINIMUM_SIZE          (1536)
337
338/**
339 * Size of a pointer.
340 *
341 * This must be an integer literal that can be used by the assembler.  This
342 * value will be used to calculate offsets of structure members.  These
343 * offsets will be used in assembler code.
344 */
345#define CPU_SIZEOF_POINTER         4
346
347/*
348 *  CPU's worst alignment requirement for data types on a byte boundary.  This
349 *  alignment does not take into account the requirements for the stack.
350 *
351 *  MOXIE Specific Information:
352 *
353 *  XXX
354 */
355#define CPU_ALIGNMENT              8
356
357/*
358 *  This number corresponds to the byte alignment requirement for the
359 *  heap handler.  This alignment requirement may be stricter than that
360 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
361 *  common for the heap to follow the same alignment requirement as
362 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
363 *  then this should be set to CPU_ALIGNMENT.
364 *
365 *  NOTE:  This does not have to be a power of 2.  It does have to
366 *         be greater or equal to than CPU_ALIGNMENT.
367 *
368 *  MOXIE Specific Information:
369 *
370 *  XXX
371 */
372#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
373
374/*
375 *  This number corresponds to the byte alignment requirement for the
376 *  stack.  This alignment requirement may be stricter than that for the
377 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
378 *  is strict enough for the stack, then this should be set to 0.
379 *
380 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
381 *
382 *  MOXIE Specific Information:
383 *
384 *  XXX
385 */
386#define CPU_STACK_ALIGNMENT        0
387
388#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
389
390/*
391 *  ISR handler macros
392 */
393
394/*
395 *  Support routine to initialize the RTEMS vector table after it is allocated.
396 */
397#define _CPU_Initialize_vectors()
398
399/*
400 *  Disable all interrupts for an RTEMS critical section.  The previous
401 *  level is returned in _level.
402 *
403 *  MOXIE Specific Information:
404 *
405 *  TODO: As of 7 October 2014, this method is not implemented.
406 */
407#define _CPU_ISR_Disable( _isr_cookie ) \
408  do { \
409    (_isr_cookie) = 0; \
410  } while (0)
411
412/*
413 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
414 *  This indicates the end of an RTEMS critical section.  The parameter
415 *  _level is not modified.
416 *
417 *  MOXIE Specific Information:
418 *
419 *  TODO: As of 7 October 2014, this method is not implemented.
420 */
421#define _CPU_ISR_Enable( _isr_cookie ) \
422  do { \
423    (_isr_cookie) = (_isr_cookie); \
424  } while (0)
425
426/*
427 *  This temporarily restores the interrupt to _level before immediately
428 *  disabling them again.  This is used to divide long RTEMS critical
429 *  sections into two or more parts.  The parameter _level is not
430 *  modified.
431 *
432 *  MOXIE Specific Information:
433 *
434 *  TODO: As of 7 October 2014, this method is not implemented.
435 */
436#define _CPU_ISR_Flash( _isr_cookie ) \
437  do { \
438    _CPU_ISR_Enable( _isr_cookie ); \
439    _CPU_ISR_Disable( _isr_cookie ); \
440  } while (0)
441
442RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
443{
444  return true;
445}
446
447/*
448 *  Map interrupt level in task mode onto the hardware that the CPU
449 *  actually provides.  Currently, interrupt levels which do not
450 *  map onto the CPU in a generic fashion are undefined.  Someday,
451 *  it would be nice if these were "mapped" by the application
452 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
453 *  8 - 255 would be available for bsp/application specific meaning.
454 *  This could be used to manage a programmable interrupt controller
455 *  via the rtems_task_mode directive.
456 *
457 *  MOXIE Specific Information:
458 *
459 *  TODO: As of 7 October 2014, this method is not implemented.
460 */
461#define _CPU_ISR_Set_level( _new_level )        \
462  {                                                     \
463    if (_new_level)   asm volatile ( "nop\n" );         \
464    else              asm volatile ( "nop\n" );         \
465  }
466
467uint32_t   _CPU_ISR_Get_level( void );
468
469/* end of ISR handler macros */
470
471/* Context handler macros */
472
473/*
474 *  Initialize the context to a state suitable for starting a
475 *  task after a context restore operation.  Generally, this
476 *  involves:
477 *
478 *     - setting a starting address
479 *     - preparing the stack
480 *     - preparing the stack and frame pointers
481 *     - setting the proper interrupt level in the context
482 *     - initializing the floating point context
483 *
484 *  This routine generally does not set any unnecessary register
485 *  in the context.  The state of the "general data" registers is
486 *  undefined at task start time.
487 *
488 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
489 *        point thread.  This is typically only used on CPUs where the
490 *        FPU may be easily disabled by software such as on the SPARC
491 *        where the PSR contains an enable FPU bit.
492 *
493 *  MOXIE Specific Information:
494 *
495 *  TODO: As of 7 October 2014, this method does not ensure that the context
496 *  is set up with interrupts disabled/enabled as requested.
497 */
498#define CPU_CCR_INTERRUPTS_ON  0x80
499#define CPU_CCR_INTERRUPTS_OFF 0x00
500
501#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
502                                 _isr, _entry_point, _is_fp, _tls_area ) \
503  /* Locate Me */                                                  \
504  do {                                                             \
505    uintptr_t   _stack;                                            \
506                                                                   \
507    (void) _is_fp; /* avoid warning for being unused */            \
508    (void) _isr;   /* avoid warning for being unused */            \
509    _stack = ((uintptr_t)(_stack_base)) + (_size) - 8;             \
510    *((proc_ptr *)(_stack)) = (_entry_point);                      \
511    _stack -= 4;                                                   \
512    (_the_context)->fp = (void *)_stack;                           \
513    (_the_context)->sp = (void *)_stack;                           \
514  } while (0)
515
516
517/*
518 *  This routine is responsible for somehow restarting the currently
519 *  executing task.  If you are lucky, then all that is necessary
520 *  is restoring the context.  Otherwise, there will need to be
521 *  a special assembly routine which does something special in this
522 *  case.  Context_Restore should work most of the time.  It will
523 *  not work if restarting self conflicts with the stack frame
524 *  assumptions of restoring a context.
525 *
526 *  MOXIE Specific Information:
527 *
528 *  XXX
529 */
530#define _CPU_Context_Restart_self( _the_context ) \
531   _CPU_Context_restore( (_the_context) );
532
533#define _CPU_Context_Initialize_fp( _destination ) \
534  memset( *( _destination ), 0, CPU_CONTEXT_FP_SIZE );
535
536/* end of Context handler macros */
537
538/* Fatal Error manager macros */
539
540/*
541 *  This routine copies _error into a known place -- typically a stack
542 *  location or a register, optionally disables interrupts, and
543 *  halts/stops the CPU.
544 *
545 *  MOXIE Specific Information:
546 *
547 *  XXX
548 */
549#define _CPU_Fatal_halt( _source, _error ) \
550        printk("Fatal Error %d.%lu Halted\n",_source,_error); \
551        for(;;)
552
553/* end of Fatal Error manager macros */
554
555#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
556
557/* functions */
558
559/*
560 *  _CPU_Initialize
561 *
562 *  This routine performs CPU dependent initialization.
563 *
564 *  MOXIE Specific Information:
565 *
566 *  XXX
567 */
568void _CPU_Initialize(void);
569
570/*
571 *  _CPU_ISR_install_raw_handler
572 *
573 *  This routine installs a "raw" interrupt handler directly into the
574 *  processor's vector table.
575 *
576 *  MOXIE Specific Information:
577 *
578 *  XXX
579 */
580void _CPU_ISR_install_raw_handler(
581  uint32_t    vector,
582  proc_ptr    new_handler,
583  proc_ptr   *old_handler
584);
585
586/*
587 *  _CPU_ISR_install_vector
588 *
589 *  This routine installs an interrupt vector.
590 *
591 *  MOXIE Specific Information:
592 *
593 *  XXX
594 */
595void _CPU_ISR_install_vector(
596  uint32_t    vector,
597  proc_ptr    new_handler,
598  proc_ptr   *old_handler
599);
600
601/*
602 *  _CPU_Internal_threads_Idle_thread_body
603 *
604 *  This routine is the CPU dependent IDLE thread body.
605 *
606 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
607 *         is TRUE.
608 *
609 *  MOXIE Specific Information:
610 *
611 *  XXX
612 */
613void *_CPU_Thread_Idle_body( uint32_t );
614
615/*
616 *  _CPU_Context_switch
617 *
618 *  This routine switches from the run context to the heir context.
619 *
620 *  MOXIE Specific Information:
621 *
622 *  XXX
623 */
624void _CPU_Context_switch(
625  Context_Control  *run,
626  Context_Control  *heir
627);
628
629/*
630 *  _CPU_Context_restore
631 *
632 *  This routine is generallu used only to restart self in an
633 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
634 *
635 *  NOTE: May be unnecessary to reload some registers.
636 *
637 *  MOXIE Specific Information:
638 *
639 *  XXX
640 */
641void _CPU_Context_restore(
642  Context_Control *new_context
643) RTEMS_NO_RETURN;
644
645/*
646 *  _CPU_Context_save_fp
647 *
648 *  This routine saves the floating point context passed to it.
649 *
650 *  MOXIE Specific Information:
651 *
652 *  XXX
653 */
654void _CPU_Context_save_fp(
655  Context_Control_fp **fp_context_ptr
656);
657
658/*
659 *  _CPU_Context_restore_fp
660 *
661 *  This routine restores the floating point context passed to it.
662 *
663 *  MOXIE Specific Information:
664 *
665 *  XXX
666 */
667void _CPU_Context_restore_fp(
668  Context_Control_fp **fp_context_ptr
669);
670
671/**
672 * @brief The set of registers that specifies the complete processor state.
673 *
674 * The CPU exception frame may be available in fatal error conditions like for
675 * example illegal opcodes, instruction fetch errors, or data access errors.
676 *
677 * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and
678 * rtems_exception_frame_print().
679 */
680typedef struct {
681  uint32_t integer_registers [16];
682} CPU_Exception_frame;
683
684/**
685 * @brief Prints the exception frame via printk().
686 *
687 * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
688 */
689void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
690
691/*  The following routine swaps the endian format of an unsigned int.
692 *  It must be static because it is referenced indirectly.
693 *
694 *  This version will work on any processor, but if there is a better
695 *  way for your CPU PLEASE use it.  The most common way to do this is to:
696 *
697 *     swap least significant two bytes with 16-bit rotate
698 *     swap upper and lower 16-bits
699 *     swap most significant two bytes with 16-bit rotate
700 *
701 *  Some CPUs have special instructions which swap a 32-bit quantity in
702 *  a single instruction (e.g. i486).  It is probably best to avoid
703 *  an "endian swapping control bit" in the CPU.  One good reason is
704 *  that interrupts would probably have to be disabled to ensure that
705 *  an interrupt does not try to access the same "chunk" with the wrong
706 *  endian.  Another good reason is that on some CPUs, the endian bit
707 *  endianness for ALL fetches -- both code and data -- so the code
708 *  will be fetched incorrectly.
709 *
710 *  MOXIE Specific Information:
711 *
712 *  This is the generic implementation.
713 */
714static inline uint32_t   CPU_swap_u32(
715  uint32_t   value
716)
717{
718  uint32_t   byte1, byte2, byte3, byte4, swapped;
719
720  byte4 = (value >> 24) & 0xff;
721  byte3 = (value >> 16) & 0xff;
722  byte2 = (value >> 8)  & 0xff;
723  byte1 =  value        & 0xff;
724
725  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
726  return( swapped );
727}
728
729#define CPU_swap_u16( value ) \
730  (((value&0xff) << 8) | ((value >> 8)&0xff))
731
732typedef uint32_t CPU_Counter_ticks;
733
734uint32_t _CPU_Counter_frequency( void );
735
736CPU_Counter_ticks _CPU_Counter_read( void );
737
738static inline CPU_Counter_ticks _CPU_Counter_difference(
739  CPU_Counter_ticks second,
740  CPU_Counter_ticks first
741)
742{
743  return second - first;
744}
745
746/** Type that can store a 32-bit integer or a pointer. */
747typedef uintptr_t CPU_Uint32ptr;
748
749#ifdef __cplusplus
750}
751#endif
752
753#endif
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