1 | /** |
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2 | * @file |
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3 | * |
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4 | * @addtogroup RTEMSScoreCPUMoxie |
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5 | */ |
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6 | |
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7 | /* |
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8 | * This include file contains information pertaining to the Moxie |
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9 | * processor. |
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10 | * |
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11 | * Copyright (c) 2013 Anthony Green |
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12 | * |
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13 | * Based on code with the following copyright.. |
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14 | * COPYRIGHT (c) 1989-2006, 2010. |
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15 | * On-Line Applications Research Corporation (OAR). |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.org/license/LICENSE. |
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20 | */ |
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21 | |
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22 | #ifndef _RTEMS_SCORE_CPU_H |
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23 | #define _RTEMS_SCORE_CPU_H |
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24 | |
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25 | #ifdef __cplusplus |
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26 | extern "C" { |
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27 | #endif |
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28 | |
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29 | #include <rtems/score/basedefs.h> |
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30 | #include <rtems/score/moxie.h> /* pick up machine definitions */ |
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31 | |
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32 | #include <rtems/bspIo.h> /* printk */ |
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33 | |
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34 | /* conditional compilation parameters */ |
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35 | |
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36 | /* |
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37 | * Should this target use 16 or 32 bit object Ids? |
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38 | * |
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39 | */ |
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40 | #define RTEMS_USE_32_BIT_OBJECT |
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41 | |
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42 | /* |
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43 | * Does the CPU follow the simple vectored interrupt model? |
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44 | * |
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45 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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46 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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47 | * table |
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48 | * |
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49 | * MOXIE Specific Information: |
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50 | * |
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51 | * XXX document implementation including references if appropriate |
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52 | */ |
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53 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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54 | |
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55 | #define CPU_HARDWARE_FP FALSE |
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56 | |
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57 | #define CPU_SOFTWARE_FP FALSE |
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58 | |
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59 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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60 | |
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61 | #define CPU_IDLE_TASK_IS_FP FALSE |
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62 | |
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63 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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64 | |
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65 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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66 | |
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67 | /* |
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68 | * Does the stack grow up (toward higher addresses) or down |
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69 | * (toward lower addresses)? |
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70 | * |
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71 | * If TRUE, then the grows upward. |
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72 | * If FALSE, then the grows toward smaller addresses. |
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73 | * |
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74 | * MOXIE Specific Information: |
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75 | * |
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76 | * XXX |
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77 | */ |
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78 | #define CPU_STACK_GROWS_UP FALSE |
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79 | |
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80 | /* FIXME: Is this the right value? */ |
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81 | #define CPU_CACHE_LINE_BYTES 32 |
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82 | |
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83 | #define CPU_STRUCTURE_ALIGNMENT |
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84 | |
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85 | /* |
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86 | * The following defines the number of bits actually used in the |
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87 | * interrupt field of the task mode. How those bits map to the |
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88 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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89 | * |
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90 | * MOXIE Specific Information: |
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91 | * |
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92 | * XXX |
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93 | */ |
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94 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
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95 | |
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96 | #define CPU_MAXIMUM_PROCESSORS 32 |
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97 | |
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98 | /* |
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99 | * Processor defined structures required for cpukit/score. |
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100 | * |
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101 | * MOXIE Specific Information: |
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102 | * |
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103 | * XXX |
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104 | */ |
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105 | |
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106 | /* may need to put some structures here. */ |
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107 | |
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108 | /* |
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109 | * Contexts |
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110 | * |
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111 | * Generally there are 2 types of context to save. |
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112 | * 1. Interrupt registers to save |
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113 | * 2. Task level registers to save |
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114 | * |
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115 | * This means we have the following 3 context items: |
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116 | * 1. task level context stuff:: Context_Control |
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117 | * 2. floating point task stuff:: Context_Control_fp |
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118 | * 3. special interrupt level context :: Context_Control_interrupt |
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119 | * |
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120 | * On some processors, it is cost-effective to save only the callee |
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121 | * preserved registers during a task context switch. This means |
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122 | * that the ISR code needs to save those registers which do not |
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123 | * persist across function calls. It is not mandatory to make this |
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124 | * distinctions between the caller/callee saves registers for the |
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125 | * purpose of minimizing context saved during task switch and on interrupts. |
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126 | * If the cost of saving extra registers is minimal, simplicity is the |
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127 | * choice. Save the same context on interrupt entry as for tasks in |
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128 | * this case. |
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129 | * |
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130 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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131 | * care should be used in designing the context area. |
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132 | * |
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133 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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134 | * structure will not be used or it simply consist of an array of a |
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135 | * fixed number of bytes. This is done when the floating point context |
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136 | * is dumped by a "FP save context" type instruction and the format |
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137 | * is not really defined by the CPU. In this case, there is no need |
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138 | * to figure out the exact format -- only the size. Of course, although |
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139 | * this is enough information for RTEMS, it is probably not enough for |
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140 | * a debugger such as gdb. But that is another problem. |
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141 | * |
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142 | * MOXIE Specific Information: |
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143 | * |
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144 | * XXX |
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145 | */ |
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146 | |
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147 | #define nogap __attribute__ ((packed)) |
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148 | |
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149 | typedef struct { |
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150 | void *fp nogap; |
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151 | void *sp nogap; |
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152 | uint32_t r0 nogap; |
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153 | uint32_t r1 nogap; |
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154 | uint32_t r2 nogap; |
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155 | uint32_t r3 nogap; |
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156 | uint32_t r4 nogap; |
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157 | uint32_t r5 nogap; |
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158 | uint32_t r6 nogap; |
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159 | uint32_t r7 nogap; |
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160 | uint32_t r8 nogap; |
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161 | uint32_t r9 nogap; |
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162 | uint32_t r10 nogap; |
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163 | uint32_t r11 nogap; |
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164 | uint32_t r12 nogap; |
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165 | uint32_t r13 nogap; |
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166 | } Context_Control; |
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167 | |
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168 | #define _CPU_Context_Get_SP( _context ) \ |
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169 | (_context)->sp |
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170 | |
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171 | typedef struct { |
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172 | uint32_t special_interrupt_register; |
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173 | } CPU_Interrupt_frame; |
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174 | |
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175 | /* |
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176 | * Amount of extra stack (above minimum stack size) required by |
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177 | * system initialization thread. Remember that in a multiprocessor |
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178 | * system the system intialization thread becomes the MP server thread. |
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179 | * |
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180 | * MOXIE Specific Information: |
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181 | * |
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182 | * It is highly unlikely the MOXIE will get used in a multiprocessor system. |
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183 | */ |
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184 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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185 | |
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186 | /* |
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187 | * This defines the number of entries in the ISR_Vector_table managed |
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188 | * by RTEMS. |
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189 | * |
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190 | * MOXIE Specific Information: |
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191 | * |
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192 | * XXX |
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193 | */ |
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194 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 |
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195 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER \ |
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196 | (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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197 | |
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198 | /* |
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199 | * This is defined if the port has a special way to report the ISR nesting |
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200 | * level. Most ports maintain the variable _ISR_Nest_level. |
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201 | */ |
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202 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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203 | |
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204 | /* |
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205 | * Should be large enough to run all RTEMS tests. This ensures |
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206 | * that a "reasonable" small application should not have any problems. |
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207 | * |
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208 | * MOXIE Specific Information: |
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209 | * |
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210 | * XXX |
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211 | */ |
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212 | #define CPU_STACK_MINIMUM_SIZE (1536) |
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213 | |
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214 | /** |
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215 | * Size of a pointer. |
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216 | * |
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217 | * This must be an integer literal that can be used by the assembler. This |
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218 | * value will be used to calculate offsets of structure members. These |
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219 | * offsets will be used in assembler code. |
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220 | */ |
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221 | #define CPU_SIZEOF_POINTER 4 |
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222 | |
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223 | /* |
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224 | * CPU's worst alignment requirement for data types on a byte boundary. This |
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225 | * alignment does not take into account the requirements for the stack. |
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226 | * |
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227 | * MOXIE Specific Information: |
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228 | * |
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229 | * XXX |
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230 | */ |
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231 | #define CPU_ALIGNMENT 8 |
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232 | |
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233 | /* |
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234 | * This number corresponds to the byte alignment requirement for the |
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235 | * heap handler. This alignment requirement may be stricter than that |
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236 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
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237 | * common for the heap to follow the same alignment requirement as |
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238 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
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239 | * then this should be set to CPU_ALIGNMENT. |
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240 | * |
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241 | * NOTE: This does not have to be a power of 2. It does have to |
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242 | * be greater or equal to than CPU_ALIGNMENT. |
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243 | * |
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244 | * MOXIE Specific Information: |
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245 | * |
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246 | * XXX |
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247 | */ |
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248 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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249 | |
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250 | #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT |
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251 | |
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252 | #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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253 | |
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254 | /* |
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255 | * ISR handler macros |
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256 | */ |
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257 | |
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258 | /* |
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259 | * Disable all interrupts for an RTEMS critical section. The previous |
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260 | * level is returned in _level. |
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261 | * |
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262 | * MOXIE Specific Information: |
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263 | * |
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264 | * TODO: As of 7 October 2014, this method is not implemented. |
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265 | */ |
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266 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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267 | do { \ |
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268 | (_isr_cookie) = 0; \ |
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269 | } while (0) |
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270 | |
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271 | /* |
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272 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
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273 | * This indicates the end of an RTEMS critical section. The parameter |
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274 | * _level is not modified. |
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275 | * |
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276 | * MOXIE Specific Information: |
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277 | * |
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278 | * TODO: As of 7 October 2014, this method is not implemented. |
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279 | */ |
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280 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
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281 | do { \ |
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282 | (_isr_cookie) = (_isr_cookie); \ |
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283 | } while (0) |
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284 | |
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285 | /* |
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286 | * This temporarily restores the interrupt to _level before immediately |
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287 | * disabling them again. This is used to divide long RTEMS critical |
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288 | * sections into two or more parts. The parameter _level is not |
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289 | * modified. |
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290 | * |
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291 | * MOXIE Specific Information: |
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292 | * |
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293 | * TODO: As of 7 October 2014, this method is not implemented. |
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294 | */ |
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295 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
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296 | do { \ |
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297 | _CPU_ISR_Enable( _isr_cookie ); \ |
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298 | _CPU_ISR_Disable( _isr_cookie ); \ |
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299 | } while (0) |
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300 | |
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301 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
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302 | { |
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303 | return true; |
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304 | } |
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305 | |
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306 | /* |
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307 | * Map interrupt level in task mode onto the hardware that the CPU |
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308 | * actually provides. Currently, interrupt levels which do not |
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309 | * map onto the CPU in a generic fashion are undefined. Someday, |
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310 | * it would be nice if these were "mapped" by the application |
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311 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
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312 | * 8 - 255 would be available for bsp/application specific meaning. |
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313 | * This could be used to manage a programmable interrupt controller |
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314 | * via the rtems_task_mode directive. |
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315 | * |
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316 | * MOXIE Specific Information: |
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317 | * |
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318 | * TODO: As of 7 October 2014, this method is not implemented. |
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319 | */ |
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320 | #define _CPU_ISR_Set_level( _new_level ) \ |
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321 | { \ |
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322 | if (_new_level) asm volatile ( "nop\n" ); \ |
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323 | else asm volatile ( "nop\n" ); \ |
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324 | } |
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325 | |
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326 | uint32_t _CPU_ISR_Get_level( void ); |
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327 | |
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328 | /* end of ISR handler macros */ |
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329 | |
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330 | /* Context handler macros */ |
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331 | |
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332 | /* |
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333 | * Initialize the context to a state suitable for starting a |
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334 | * task after a context restore operation. Generally, this |
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335 | * involves: |
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336 | * |
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337 | * - setting a starting address |
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338 | * - preparing the stack |
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339 | * - preparing the stack and frame pointers |
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340 | * - setting the proper interrupt level in the context |
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341 | * - initializing the floating point context |
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342 | * |
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343 | * This routine generally does not set any unnecessary register |
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344 | * in the context. The state of the "general data" registers is |
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345 | * undefined at task start time. |
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346 | * |
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347 | * NOTE: This is_fp parameter is TRUE if the thread is to be a floating |
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348 | * point thread. This is typically only used on CPUs where the |
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349 | * FPU may be easily disabled by software such as on the SPARC |
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350 | * where the PSR contains an enable FPU bit. |
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351 | * |
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352 | * MOXIE Specific Information: |
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353 | * |
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354 | * TODO: As of 7 October 2014, this method does not ensure that the context |
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355 | * is set up with interrupts disabled/enabled as requested. |
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356 | */ |
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357 | #define CPU_CCR_INTERRUPTS_ON 0x80 |
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358 | #define CPU_CCR_INTERRUPTS_OFF 0x00 |
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359 | |
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360 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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361 | _isr, _entry_point, _is_fp, _tls_area ) \ |
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362 | /* Locate Me */ \ |
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363 | do { \ |
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364 | uintptr_t _stack; \ |
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365 | \ |
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366 | (void) _is_fp; /* avoid warning for being unused */ \ |
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367 | (void) _isr; /* avoid warning for being unused */ \ |
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368 | _stack = ((uintptr_t)(_stack_base)) + (_size) - 8; \ |
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369 | *((void (**)(void))(_stack)) = (_entry_point); \ |
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370 | _stack -= 4; \ |
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371 | (_the_context)->fp = (void *)_stack; \ |
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372 | (_the_context)->sp = (void *)_stack; \ |
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373 | } while (0) |
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374 | |
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375 | |
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376 | /* |
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377 | * This routine is responsible for somehow restarting the currently |
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378 | * executing task. If you are lucky, then all that is necessary |
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379 | * is restoring the context. Otherwise, there will need to be |
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380 | * a special assembly routine which does something special in this |
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381 | * case. Context_Restore should work most of the time. It will |
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382 | * not work if restarting self conflicts with the stack frame |
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383 | * assumptions of restoring a context. |
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384 | * |
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385 | * MOXIE Specific Information: |
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386 | * |
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387 | * XXX |
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388 | */ |
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389 | #define _CPU_Context_Restart_self( _the_context ) \ |
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390 | _CPU_Context_restore( (_the_context) ); |
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391 | |
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392 | /* end of Context handler macros */ |
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393 | |
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394 | /* Fatal Error manager macros */ |
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395 | |
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396 | /* |
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397 | * This routine copies _error into a known place -- typically a stack |
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398 | * location or a register, optionally disables interrupts, and |
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399 | * halts/stops the CPU. |
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400 | * |
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401 | * MOXIE Specific Information: |
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402 | * |
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403 | * XXX |
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404 | */ |
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405 | #define _CPU_Fatal_halt( _source, _error ) \ |
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406 | printk("Fatal Error %d.%lu Halted\n",_source,_error); \ |
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407 | for(;;) |
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408 | |
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409 | /* end of Fatal Error manager macros */ |
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410 | |
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411 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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412 | |
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413 | #define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE |
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414 | |
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415 | /* functions */ |
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416 | |
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417 | /* |
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418 | * _CPU_Initialize |
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419 | * |
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420 | * This routine performs CPU dependent initialization. |
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421 | * |
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422 | * MOXIE Specific Information: |
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423 | * |
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424 | * XXX |
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425 | */ |
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426 | void _CPU_Initialize(void); |
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427 | |
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428 | typedef void ( *CPU_ISR_handler )( uint32_t ); |
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429 | |
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430 | void _CPU_ISR_install_vector( |
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431 | uint32_t vector, |
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432 | CPU_ISR_handler new_handler, |
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433 | CPU_ISR_handler *old_handler |
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434 | ); |
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435 | |
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436 | void *_CPU_Thread_Idle_body( uintptr_t ); |
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437 | |
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438 | /* |
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439 | * _CPU_Context_switch |
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440 | * |
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441 | * This routine switches from the run context to the heir context. |
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442 | * |
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443 | * MOXIE Specific Information: |
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444 | * |
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445 | * XXX |
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446 | */ |
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447 | void _CPU_Context_switch( |
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448 | Context_Control *run, |
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449 | Context_Control *heir |
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450 | ); |
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451 | |
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452 | /* |
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453 | * _CPU_Context_restore |
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454 | * |
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455 | * This routine is generallu used only to restart self in an |
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456 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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457 | * |
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458 | * NOTE: May be unnecessary to reload some registers. |
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459 | * |
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460 | * MOXIE Specific Information: |
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461 | * |
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462 | * XXX |
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463 | */ |
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464 | RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context ); |
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465 | |
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466 | /** |
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467 | * @brief The set of registers that specifies the complete processor state. |
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468 | * |
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469 | * The CPU exception frame may be available in fatal error conditions like for |
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470 | * example illegal opcodes, instruction fetch errors, or data access errors. |
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471 | * |
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472 | * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and |
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473 | * rtems_exception_frame_print(). |
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474 | */ |
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475 | typedef struct { |
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476 | uint32_t integer_registers [16]; |
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477 | } CPU_Exception_frame; |
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478 | |
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479 | /** |
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480 | * @brief Prints the exception frame via printk(). |
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481 | * |
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482 | * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. |
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483 | */ |
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484 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
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485 | |
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486 | /* The following routine swaps the endian format of an unsigned int. |
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487 | * It must be static because it is referenced indirectly. |
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488 | * |
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489 | * This version will work on any processor, but if there is a better |
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490 | * way for your CPU PLEASE use it. The most common way to do this is to: |
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491 | * |
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492 | * swap least significant two bytes with 16-bit rotate |
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493 | * swap upper and lower 16-bits |
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494 | * swap most significant two bytes with 16-bit rotate |
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495 | * |
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496 | * Some CPUs have special instructions which swap a 32-bit quantity in |
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497 | * a single instruction (e.g. i486). It is probably best to avoid |
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498 | * an "endian swapping control bit" in the CPU. One good reason is |
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499 | * that interrupts would probably have to be disabled to ensure that |
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500 | * an interrupt does not try to access the same "chunk" with the wrong |
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501 | * endian. Another good reason is that on some CPUs, the endian bit |
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502 | * endianness for ALL fetches -- both code and data -- so the code |
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503 | * will be fetched incorrectly. |
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504 | * |
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505 | * MOXIE Specific Information: |
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506 | * |
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507 | * This is the generic implementation. |
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508 | */ |
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509 | static inline uint32_t CPU_swap_u32( |
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510 | uint32_t value |
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511 | ) |
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512 | { |
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513 | uint32_t byte1, byte2, byte3, byte4, swapped; |
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514 | |
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515 | byte4 = (value >> 24) & 0xff; |
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516 | byte3 = (value >> 16) & 0xff; |
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517 | byte2 = (value >> 8) & 0xff; |
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518 | byte1 = value & 0xff; |
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519 | |
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520 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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521 | return( swapped ); |
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522 | } |
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523 | |
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524 | #define CPU_swap_u16( value ) \ |
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525 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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526 | |
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527 | typedef uint32_t CPU_Counter_ticks; |
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528 | |
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529 | uint32_t _CPU_Counter_frequency( void ); |
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530 | |
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531 | CPU_Counter_ticks _CPU_Counter_read( void ); |
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532 | |
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533 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
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534 | CPU_Counter_ticks second, |
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535 | CPU_Counter_ticks first |
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536 | ) |
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537 | { |
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538 | return second - first; |
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539 | } |
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540 | |
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541 | /** Type that can store a 32-bit integer or a pointer. */ |
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542 | typedef uintptr_t CPU_Uint32ptr; |
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543 | |
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544 | #ifdef __cplusplus |
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545 | } |
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546 | #endif |
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547 | |
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548 | #endif |
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