1 | /* cpu_asm.S |
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2 | * |
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3 | * This file contains the basic algorithms for all assembly code used |
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4 | * in an specific CPU port of RTEMS. These algorithms must be implemented |
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5 | * in assembly language |
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6 | * |
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7 | * Author: Craig Lebakken <craigl@transition.com> |
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8 | * |
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9 | * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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10 | * |
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11 | * To anyone who acknowledges that this file is provided "AS IS" |
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12 | * without any express or implied warranty: |
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13 | * permission to use, copy, modify, and distribute this file |
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14 | * for any purpose is hereby granted without fee, provided that |
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15 | * the above copyright notice and this notice appears in all |
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16 | * copies, and that the name of Transition Networks not be used in |
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17 | * advertising or publicity pertaining to distribution of the |
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18 | * software without specific, written prior permission. |
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19 | * Transition Networks makes no representations about the suitability |
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20 | * of this software for any purpose. |
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21 | * |
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22 | * Derived from source copyrighted as follows: |
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23 | * |
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24 | * COPYRIGHT (c) 1989-1999. |
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25 | * On-Line Applications Research Corporation (OAR). |
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26 | * |
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27 | * The license and distribution terms for this file may be |
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28 | * found in the file LICENSE in this distribution or at |
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29 | * http://www.OARcorp.com/rtems/license.html. |
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30 | * |
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31 | * $Id$ |
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32 | */ |
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33 | /* @(#)cpu_asm.S 08/20/96 1.15 */ |
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34 | |
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35 | #include "cpu_asm.h" |
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36 | |
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37 | #include "iregdef.h" |
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38 | #include "idtcpu.h" |
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39 | |
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40 | #define FRAME(name,frm_reg,offset,ret_reg) \ |
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41 | .globl name; \ |
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42 | .ent name; \ |
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43 | name:; \ |
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44 | .frame frm_reg,offset,ret_reg |
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45 | #define ENDFRAME(name) \ |
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46 | .end name |
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47 | |
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48 | |
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49 | #define EXCP_STACK_SIZE (NREGS*R_SZ) |
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50 | |
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51 | #if __ghs__ |
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52 | #define sd sw |
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53 | #define ld lw |
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54 | #define dmtc0 mtc0 |
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55 | #define dsll sll |
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56 | #define dmfc0 mfc0 |
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57 | #endif |
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58 | |
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59 | #if 1 /* 32 bit unsigned32 types */ |
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60 | #define sint sw |
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61 | #define lint lw |
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62 | #define stackadd addiu |
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63 | #define intadd addu |
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64 | #define SZ_INT 4 |
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65 | #define SZ_INT_POW2 2 |
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66 | #else /* 64 bit unsigned32 types */ |
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67 | #define sint dw |
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68 | #define lint dw |
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69 | #define stackadd daddiu |
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70 | #define intadd daddu |
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71 | #define SZ_INT 8 |
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72 | #define SZ_INT_POW2 3 |
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73 | #endif |
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74 | |
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75 | #ifdef __GNUC__ |
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76 | #define EXTERN(x,size) .extern x,size |
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77 | #else |
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78 | #define EXTERN(x,size) |
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79 | #endif |
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80 | |
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81 | /* NOTE: these constants must match the Context_Control structure in cpu.h */ |
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82 | #define S0_OFFSET 0 |
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83 | #define S1_OFFSET 1 |
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84 | #define S2_OFFSET 2 |
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85 | #define S3_OFFSET 3 |
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86 | #define S4_OFFSET 4 |
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87 | #define S5_OFFSET 5 |
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88 | #define S6_OFFSET 6 |
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89 | #define S7_OFFSET 7 |
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90 | #define SP_OFFSET 8 |
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91 | #define FP_OFFSET 9 |
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92 | #define RA_OFFSET 10 |
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93 | #define C0_SR_OFFSET 11 |
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94 | #define C0_EPC_OFFSET 12 |
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95 | |
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96 | /* NOTE: these constants must match the Context_Control_fp structure in cpu.h */ |
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97 | #define FP0_OFFSET 0 |
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98 | #define FP1_OFFSET 1 |
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99 | #define FP2_OFFSET 2 |
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100 | #define FP3_OFFSET 3 |
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101 | #define FP4_OFFSET 4 |
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102 | #define FP5_OFFSET 5 |
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103 | #define FP6_OFFSET 6 |
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104 | #define FP7_OFFSET 7 |
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105 | #define FP8_OFFSET 8 |
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106 | #define FP9_OFFSET 9 |
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107 | #define FP10_OFFSET 10 |
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108 | #define FP11_OFFSET 11 |
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109 | #define FP12_OFFSET 12 |
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110 | #define FP13_OFFSET 13 |
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111 | #define FP14_OFFSET 14 |
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112 | #define FP15_OFFSET 15 |
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113 | #define FP16_OFFSET 16 |
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114 | #define FP17_OFFSET 17 |
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115 | #define FP18_OFFSET 18 |
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116 | #define FP19_OFFSET 19 |
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117 | #define FP20_OFFSET 20 |
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118 | #define FP21_OFFSET 21 |
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119 | #define FP22_OFFSET 22 |
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120 | #define FP23_OFFSET 23 |
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121 | #define FP24_OFFSET 24 |
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122 | #define FP25_OFFSET 25 |
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123 | #define FP26_OFFSET 26 |
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124 | #define FP27_OFFSET 27 |
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125 | #define FP28_OFFSET 28 |
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126 | #define FP29_OFFSET 29 |
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127 | #define FP30_OFFSET 30 |
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128 | #define FP31_OFFSET 31 |
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129 | |
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130 | |
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131 | /*PAGE |
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132 | * |
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133 | * _CPU_ISR_Get_level |
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134 | */ |
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135 | |
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136 | #if 0 |
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137 | unsigned32 _CPU_ISR_Get_level( void ) |
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138 | { |
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139 | /* |
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140 | * This routine returns the current interrupt level. |
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141 | */ |
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142 | } |
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143 | #endif |
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144 | /* return the current exception level for the 4650 */ |
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145 | FRAME(_CPU_ISR_Get_level,sp,0,ra) |
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146 | mfc0 v0,C0_SR |
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147 | nop |
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148 | andi v0,SR_EXL |
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149 | srl v0,1 |
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150 | j ra |
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151 | ENDFRAME(_CPU_ISR_Get_level) |
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152 | |
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153 | FRAME(_CPU_ISR_Set_level,sp,0,ra) |
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154 | nop |
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155 | mfc0 v0,C0_SR |
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156 | nop |
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157 | andi v0,SR_EXL |
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158 | beqz v0,_CPU_ISR_Set_1 /* normalize v0 */ |
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159 | nop |
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160 | li v0,1 |
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161 | _CPU_ISR_Set_1: |
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162 | beq v0,a0,_CPU_ISR_Set_exit /* if (current_level != new_level ) */ |
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163 | nop |
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164 | bnez a0,_CPU_ISR_Set_2 |
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165 | nop |
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166 | nop |
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167 | mfc0 t0,C0_SR |
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168 | nop |
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169 | li t1,~SR_EXL |
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170 | and t0,t1 |
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171 | nop |
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172 | mtc0 t0,C0_SR /* disable exception level */ |
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173 | nop |
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174 | j ra |
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175 | nop |
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176 | _CPU_ISR_Set_2: |
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177 | nop |
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178 | mfc0 t0,C0_SR |
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179 | nop |
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180 | li t1,~SR_IE |
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181 | and t0,t1 |
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182 | nop |
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183 | mtc0 t0,C0_SR /* first disable ie bit (recommended) */ |
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184 | nop |
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185 | ori t0,SR_EXL|SR_IE /* enable exception level */ |
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186 | nop |
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187 | mtc0 t0,C0_SR |
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188 | nop |
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189 | _CPU_ISR_Set_exit: |
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190 | j ra |
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191 | nop |
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192 | ENDFRAME(_CPU_ISR_Set_level) |
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193 | |
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194 | /* |
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195 | * _CPU_Context_save_fp_context |
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196 | * |
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197 | * This routine is responsible for saving the FP context |
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198 | * at *fp_context_ptr. If the point to load the FP context |
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199 | * from is changed then the pointer is modified by this routine. |
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200 | * |
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201 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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202 | * the ** and a similarly named routine in this file is passed something |
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203 | * like a (Context_Control_fp *). The general rule on making this decision |
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204 | * is to avoid writing assembly language. |
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205 | */ |
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206 | |
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207 | /* void _CPU_Context_save_fp( |
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208 | * void **fp_context_ptr |
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209 | * ) |
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210 | * { |
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211 | * } |
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212 | */ |
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213 | |
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214 | FRAME(_CPU_Context_save_fp,sp,0,ra) |
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215 | .set noat |
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216 | ld a1,(a0) |
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217 | swc1 $f0,FP0_OFFSET*4(a1) |
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218 | swc1 $f1,FP1_OFFSET*4(a1) |
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219 | swc1 $f2,FP2_OFFSET*4(a1) |
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220 | swc1 $f3,FP3_OFFSET*4(a1) |
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221 | swc1 $f4,FP4_OFFSET*4(a1) |
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222 | swc1 $f5,FP5_OFFSET*4(a1) |
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223 | swc1 $f6,FP6_OFFSET*4(a1) |
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224 | swc1 $f7,FP7_OFFSET*4(a1) |
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225 | swc1 $f8,FP8_OFFSET*4(a1) |
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226 | swc1 $f9,FP9_OFFSET*4(a1) |
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227 | swc1 $f10,FP10_OFFSET*4(a1) |
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228 | swc1 $f11,FP11_OFFSET*4(a1) |
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229 | swc1 $f12,FP12_OFFSET*4(a1) |
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230 | swc1 $f13,FP13_OFFSET*4(a1) |
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231 | swc1 $f14,FP14_OFFSET*4(a1) |
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232 | swc1 $f15,FP15_OFFSET*4(a1) |
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233 | swc1 $f16,FP16_OFFSET*4(a1) |
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234 | swc1 $f17,FP17_OFFSET*4(a1) |
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235 | swc1 $f18,FP18_OFFSET*4(a1) |
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236 | swc1 $f19,FP19_OFFSET*4(a1) |
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237 | swc1 $f20,FP20_OFFSET*4(a1) |
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238 | swc1 $f21,FP21_OFFSET*4(a1) |
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239 | swc1 $f22,FP22_OFFSET*4(a1) |
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240 | swc1 $f23,FP23_OFFSET*4(a1) |
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241 | swc1 $f24,FP24_OFFSET*4(a1) |
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242 | swc1 $f25,FP25_OFFSET*4(a1) |
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243 | swc1 $f26,FP26_OFFSET*4(a1) |
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244 | swc1 $f27,FP27_OFFSET*4(a1) |
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245 | swc1 $f28,FP28_OFFSET*4(a1) |
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246 | swc1 $f29,FP29_OFFSET*4(a1) |
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247 | swc1 $f30,FP30_OFFSET*4(a1) |
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248 | swc1 $f31,FP31_OFFSET*4(a1) |
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249 | j ra |
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250 | nop |
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251 | .set at |
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252 | ENDFRAME(_CPU_Context_save_fp) |
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253 | |
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254 | /* |
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255 | * _CPU_Context_restore_fp_context |
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256 | * |
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257 | * This routine is responsible for restoring the FP context |
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258 | * at *fp_context_ptr. If the point to load the FP context |
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259 | * from is changed then the pointer is modified by this routine. |
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260 | * |
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261 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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262 | * the ** and a similarly named routine in this file is passed something |
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263 | * like a (Context_Control_fp *). The general rule on making this decision |
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264 | * is to avoid writing assembly language. |
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265 | */ |
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266 | |
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267 | /* void _CPU_Context_restore_fp( |
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268 | * void **fp_context_ptr |
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269 | * ) |
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270 | * { |
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271 | * } |
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272 | */ |
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273 | |
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274 | FRAME(_CPU_Context_restore_fp,sp,0,ra) |
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275 | .set noat |
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276 | ld a1,(a0) |
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277 | lwc1 $f0,FP0_OFFSET*4(a1) |
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278 | lwc1 $f1,FP1_OFFSET*4(a1) |
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279 | lwc1 $f2,FP2_OFFSET*4(a1) |
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280 | lwc1 $f3,FP3_OFFSET*4(a1) |
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281 | lwc1 $f4,FP4_OFFSET*4(a1) |
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282 | lwc1 $f5,FP5_OFFSET*4(a1) |
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283 | lwc1 $f6,FP6_OFFSET*4(a1) |
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284 | lwc1 $f7,FP7_OFFSET*4(a1) |
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285 | lwc1 $f8,FP8_OFFSET*4(a1) |
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286 | lwc1 $f9,FP9_OFFSET*4(a1) |
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287 | lwc1 $f10,FP10_OFFSET*4(a1) |
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288 | lwc1 $f11,FP11_OFFSET*4(a1) |
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289 | lwc1 $f12,FP12_OFFSET*4(a1) |
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290 | lwc1 $f13,FP13_OFFSET*4(a1) |
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291 | lwc1 $f14,FP14_OFFSET*4(a1) |
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292 | lwc1 $f15,FP15_OFFSET*4(a1) |
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293 | lwc1 $f16,FP16_OFFSET*4(a1) |
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294 | lwc1 $f17,FP17_OFFSET*4(a1) |
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295 | lwc1 $f18,FP18_OFFSET*4(a1) |
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296 | lwc1 $f19,FP19_OFFSET*4(a1) |
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297 | lwc1 $f20,FP20_OFFSET*4(a1) |
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298 | lwc1 $f21,FP21_OFFSET*4(a1) |
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299 | lwc1 $f22,FP22_OFFSET*4(a1) |
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300 | lwc1 $f23,FP23_OFFSET*4(a1) |
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301 | lwc1 $f24,FP24_OFFSET*4(a1) |
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302 | lwc1 $f25,FP25_OFFSET*4(a1) |
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303 | lwc1 $f26,FP26_OFFSET*4(a1) |
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304 | lwc1 $f27,FP27_OFFSET*4(a1) |
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305 | lwc1 $f28,FP28_OFFSET*4(a1) |
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306 | lwc1 $f29,FP29_OFFSET*4(a1) |
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307 | lwc1 $f30,FP30_OFFSET*4(a1) |
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308 | lwc1 $f31,FP31_OFFSET*4(a1) |
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309 | j ra |
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310 | nop |
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311 | .set at |
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312 | ENDFRAME(_CPU_Context_restore_fp) |
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313 | |
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314 | /* _CPU_Context_switch |
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315 | * |
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316 | * This routine performs a normal non-FP context switch. |
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317 | */ |
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318 | |
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319 | /* void _CPU_Context_switch( |
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320 | * Context_Control *run, |
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321 | * Context_Control *heir |
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322 | * ) |
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323 | * { |
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324 | * } |
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325 | */ |
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326 | |
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327 | FRAME(_CPU_Context_switch,sp,0,ra) |
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328 | |
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329 | mfc0 t0,C0_SR |
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330 | li t1,~SR_IE |
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331 | sd t0,C0_SR_OFFSET*8(a0) /* save status register */ |
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332 | and t0,t1 |
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333 | mtc0 t0,C0_SR /* first disable ie bit (recommended) */ |
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334 | ori t0,SR_EXL|SR_IE /* enable exception level to disable interrupts */ |
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335 | mtc0 t0,C0_SR |
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336 | |
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337 | sd ra,RA_OFFSET*8(a0) /* save current context */ |
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338 | sd sp,SP_OFFSET*8(a0) |
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339 | sd fp,FP_OFFSET*8(a0) |
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340 | sd s0,S0_OFFSET*8(a0) |
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341 | sd s1,S1_OFFSET*8(a0) |
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342 | sd s2,S2_OFFSET*8(a0) |
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343 | sd s3,S3_OFFSET*8(a0) |
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344 | sd s4,S4_OFFSET*8(a0) |
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345 | sd s5,S5_OFFSET*8(a0) |
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346 | sd s6,S6_OFFSET*8(a0) |
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347 | sd s7,S7_OFFSET*8(a0) |
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348 | dmfc0 t0,C0_EPC |
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349 | sd t0,C0_EPC_OFFSET*8(a0) |
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350 | |
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351 | _CPU_Context_switch_restore: |
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352 | ld s0,S0_OFFSET*8(a1) /* restore context */ |
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353 | ld s1,S1_OFFSET*8(a1) |
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354 | ld s2,S2_OFFSET*8(a1) |
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355 | ld s3,S3_OFFSET*8(a1) |
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356 | ld s4,S4_OFFSET*8(a1) |
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357 | ld s5,S5_OFFSET*8(a1) |
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358 | ld s6,S6_OFFSET*8(a1) |
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359 | ld s7,S7_OFFSET*8(a1) |
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360 | ld fp,FP_OFFSET*8(a1) |
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361 | ld sp,SP_OFFSET*8(a1) |
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362 | ld ra,RA_OFFSET*8(a1) |
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363 | ld t0,C0_EPC_OFFSET*8(a1) |
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364 | dmtc0 t0,C0_EPC |
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365 | ld t0,C0_SR_OFFSET*8(a1) |
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366 | andi t0,SR_EXL |
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367 | bnez t0,_CPU_Context_1 /* set exception level from restore context */ |
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368 | li t0,~SR_EXL |
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369 | mfc0 t1,C0_SR |
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370 | nop |
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371 | and t1,t0 |
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372 | mtc0 t1,C0_SR |
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373 | _CPU_Context_1: |
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374 | j ra |
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375 | nop |
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376 | ENDFRAME(_CPU_Context_switch) |
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377 | |
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378 | /* |
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379 | * _CPU_Context_restore |
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380 | * |
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381 | * This routine is generally used only to restart self in an |
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382 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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383 | * |
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384 | * NOTE: May be unnecessary to reload some registers. |
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385 | */ |
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386 | |
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387 | #if 0 |
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388 | void _CPU_Context_restore( |
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389 | Context_Control *new_context |
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390 | ) |
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391 | { |
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392 | } |
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393 | #endif |
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394 | |
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395 | FRAME(_CPU_Context_restore,sp,0,ra) |
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396 | dadd a1,a0,zero |
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397 | j _CPU_Context_switch_restore |
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398 | nop |
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399 | ENDFRAME(_CPU_Context_restore) |
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400 | |
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401 | EXTERN(_ISR_Nest_level, SZ_INT) |
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402 | EXTERN(_Thread_Dispatch_disable_level,SZ_INT) |
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403 | EXTERN(_Context_Switch_necessary,SZ_INT) |
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404 | EXTERN(_ISR_Signals_to_thread_executing,SZ_INT) |
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405 | .extern _Thread_Dispatch |
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406 | .extern _ISR_Vector_table |
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407 | |
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408 | /* void __ISR_Handler() |
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409 | * |
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410 | * This routine provides the RTEMS interrupt management. |
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411 | * |
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412 | */ |
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413 | |
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414 | #if 0 |
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415 | void _ISR_Handler() |
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416 | { |
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417 | /* |
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418 | * This discussion ignores a lot of the ugly details in a real |
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419 | * implementation such as saving enough registers/state to be |
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420 | * able to do something real. Keep in mind that the goal is |
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421 | * to invoke a user's ISR handler which is written in C and |
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422 | * uses a certain set of registers. |
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423 | * |
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424 | * Also note that the exact order is to a large extent flexible. |
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425 | * Hardware will dictate a sequence for a certain subset of |
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426 | * _ISR_Handler while requirements for setting |
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427 | */ |
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428 | |
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429 | /* |
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430 | * At entry to "common" _ISR_Handler, the vector number must be |
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431 | * available. On some CPUs the hardware puts either the vector |
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432 | * number or the offset into the vector table for this ISR in a |
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433 | * known place. If the hardware does not give us this information, |
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434 | * then the assembly portion of RTEMS for this port will contain |
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435 | * a set of distinct interrupt entry points which somehow place |
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436 | * the vector number in a known place (which is safe if another |
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437 | * interrupt nests this one) and branches to _ISR_Handler. |
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438 | * |
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439 | */ |
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440 | #endif |
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441 | FRAME(_ISR_Handler,sp,0,ra) |
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442 | .set noreorder |
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443 | #if USE_IDTKIT |
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444 | /* IDT/Kit incorrectly adds 4 to EPC before returning. This compensates */ |
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445 | lreg k0, R_EPC*R_SZ(sp) |
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446 | daddiu k0,k0,-4 |
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447 | sreg k0, R_EPC*R_SZ(sp) |
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448 | lreg k0, R_CAUSE*R_SZ(sp) |
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449 | li k1, ~CAUSE_BD |
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450 | and k0, k1 |
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451 | sreg k0, R_CAUSE*R_SZ(sp) |
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452 | #endif |
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453 | |
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454 | /* save registers not already saved by IDT/sim */ |
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455 | stackadd sp,sp,-EXCP_STACK_SIZE /* store ra on the stack */ |
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456 | |
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457 | sreg ra, R_RA*R_SZ(sp) |
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458 | sreg v0, R_V0*R_SZ(sp) |
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459 | sreg v1, R_V1*R_SZ(sp) |
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460 | sreg a0, R_A0*R_SZ(sp) |
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461 | sreg a1, R_A1*R_SZ(sp) |
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462 | sreg a2, R_A2*R_SZ(sp) |
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463 | sreg a3, R_A3*R_SZ(sp) |
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464 | sreg t0, R_T0*R_SZ(sp) |
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465 | sreg t1, R_T1*R_SZ(sp) |
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466 | sreg t2, R_T2*R_SZ(sp) |
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467 | sreg t3, R_T3*R_SZ(sp) |
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468 | sreg t4, R_T4*R_SZ(sp) |
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469 | sreg t5, R_T5*R_SZ(sp) |
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470 | sreg t6, R_T6*R_SZ(sp) |
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471 | sreg t7, R_T7*R_SZ(sp) |
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472 | mflo k0 |
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473 | sreg t8, R_T8*R_SZ(sp) |
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474 | sreg k0, R_MDLO*R_SZ(sp) |
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475 | sreg t9, R_T9*R_SZ(sp) |
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476 | mfhi k0 |
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477 | sreg gp, R_GP*R_SZ(sp) |
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478 | sreg fp, R_FP*R_SZ(sp) |
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479 | sreg k0, R_MDHI*R_SZ(sp) |
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480 | .set noat |
---|
481 | sreg AT, R_AT*R_SZ(sp) |
---|
482 | .set at |
---|
483 | |
---|
484 | stackadd sp,sp,-40 /* store ra on the stack */ |
---|
485 | sd ra,32(sp) |
---|
486 | |
---|
487 | /* determine if an interrupt generated this exception */ |
---|
488 | mfc0 k0,C0_CAUSE |
---|
489 | and k1,k0,CAUSE_EXCMASK |
---|
490 | bnez k1,_ISR_Handler_prom_exit /* not an external interrupt, pass exception to Monitor */ |
---|
491 | mfc0 k1,C0_SR |
---|
492 | and k0,k1 |
---|
493 | and k0,CAUSE_IPMASK |
---|
494 | beq k0,zero,_ISR_Handler_quick_exit /* external interrupt not enabled, ignore */ |
---|
495 | nop |
---|
496 | |
---|
497 | /* |
---|
498 | * save some or all context on stack |
---|
499 | * may need to save some special interrupt information for exit |
---|
500 | * |
---|
501 | * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
---|
502 | * if ( _ISR_Nest_level == 0 ) |
---|
503 | * switch to software interrupt stack |
---|
504 | * #endif |
---|
505 | */ |
---|
506 | #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
---|
507 | lint t0,_ISR_Nest_level |
---|
508 | beq t0, zero, _ISR_Handler_1 |
---|
509 | nop |
---|
510 | /* switch stacks */ |
---|
511 | _ISR_Handler_1: |
---|
512 | #else |
---|
513 | lint t0,_ISR_Nest_level |
---|
514 | #endif |
---|
515 | /* |
---|
516 | * _ISR_Nest_level++; |
---|
517 | */ |
---|
518 | addi t0,t0,1 |
---|
519 | sint t0,_ISR_Nest_level |
---|
520 | /* |
---|
521 | * _Thread_Dispatch_disable_level++; |
---|
522 | */ |
---|
523 | lint t1,_Thread_Dispatch_disable_level |
---|
524 | addi t1,t1,1 |
---|
525 | sint t1,_Thread_Dispatch_disable_level |
---|
526 | #if 0 |
---|
527 | nop |
---|
528 | j _ISR_Handler_4 |
---|
529 | nop |
---|
530 | /* |
---|
531 | * while ( interrupts_pending(cause_reg) ) { |
---|
532 | * vector = BITFIELD_TO_INDEX(cause_reg); |
---|
533 | * (*_ISR_Vector_table[ vector ])( vector ); |
---|
534 | * } |
---|
535 | */ |
---|
536 | _ISR_Handler_2: |
---|
537 | /* software interrupt priorities can be applied here */ |
---|
538 | li t1,-1 |
---|
539 | /* convert bit field into interrupt index */ |
---|
540 | _ISR_Handler_3: |
---|
541 | andi t2,t0,1 |
---|
542 | addi t1,1 |
---|
543 | beql t2,zero,_ISR_Handler_3 |
---|
544 | dsrl t0,1 |
---|
545 | li t1,7 |
---|
546 | dsll t1,3 /* convert index to byte offset (*8) */ |
---|
547 | la t3,_ISR_Vector_table |
---|
548 | intadd t1,t3 |
---|
549 | lint t1,(t1) |
---|
550 | jalr t1 |
---|
551 | nop |
---|
552 | j _ISR_Handler_5 |
---|
553 | nop |
---|
554 | _ISR_Handler_4: |
---|
555 | mfc0 t0,C0_CAUSE |
---|
556 | andi t0,CAUSE_IPMASK |
---|
557 | bne t0,zero,_ISR_Handler_2 |
---|
558 | dsrl t0,t0,8 |
---|
559 | _ISR_Handler_5: |
---|
560 | #else |
---|
561 | nop |
---|
562 | li t1,7 |
---|
563 | dsll t1,t1,SZ_INT_POW2 |
---|
564 | la t3,_ISR_Vector_table |
---|
565 | intadd t1,t3 |
---|
566 | lint t1,(t1) |
---|
567 | jalr t1 |
---|
568 | nop |
---|
569 | #endif |
---|
570 | /* |
---|
571 | * --_ISR_Nest_level; |
---|
572 | */ |
---|
573 | lint t2,_ISR_Nest_level |
---|
574 | addi t2,t2,-1 |
---|
575 | sint t2,_ISR_Nest_level |
---|
576 | /* |
---|
577 | * --_Thread_Dispatch_disable_level; |
---|
578 | */ |
---|
579 | lint t1,_Thread_Dispatch_disable_level |
---|
580 | addi t1,t1,-1 |
---|
581 | sint t1,_Thread_Dispatch_disable_level |
---|
582 | /* |
---|
583 | * if ( _Thread_Dispatch_disable_level || _ISR_Nest_level ) |
---|
584 | * goto the label "exit interrupt (simple case)" |
---|
585 | */ |
---|
586 | or t0,t2,t1 |
---|
587 | bne t0,zero,_ISR_Handler_exit |
---|
588 | nop |
---|
589 | /* |
---|
590 | * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
---|
591 | * restore stack |
---|
592 | * #endif |
---|
593 | * |
---|
594 | * if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing ) |
---|
595 | * goto the label "exit interrupt (simple case)" |
---|
596 | */ |
---|
597 | lint t0,_Context_Switch_necessary |
---|
598 | lint t1,_ISR_Signals_to_thread_executing |
---|
599 | or t0,t0,t1 |
---|
600 | beq t0,zero,_ISR_Handler_exit |
---|
601 | nop |
---|
602 | |
---|
603 | /* |
---|
604 | * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch |
---|
605 | */ |
---|
606 | jal _Thread_Dispatch |
---|
607 | nop |
---|
608 | /* |
---|
609 | * prepare to get out of interrupt |
---|
610 | * return from interrupt (maybe to _ISR_Dispatch) |
---|
611 | * |
---|
612 | * LABEL "exit interrupt (simple case): |
---|
613 | * prepare to get out of interrupt |
---|
614 | * return from interrupt |
---|
615 | */ |
---|
616 | _ISR_Handler_exit: |
---|
617 | ld ra,32(sp) |
---|
618 | stackadd sp,sp,40 |
---|
619 | |
---|
620 | /* restore interrupt context from stack */ |
---|
621 | lreg k0, R_MDLO*R_SZ(sp) |
---|
622 | mtlo k0 |
---|
623 | lreg k0, R_MDHI*R_SZ(sp) |
---|
624 | lreg a2, R_A2*R_SZ(sp) |
---|
625 | mthi k0 |
---|
626 | lreg a3, R_A3*R_SZ(sp) |
---|
627 | lreg t0, R_T0*R_SZ(sp) |
---|
628 | lreg t1, R_T1*R_SZ(sp) |
---|
629 | lreg t2, R_T2*R_SZ(sp) |
---|
630 | lreg t3, R_T3*R_SZ(sp) |
---|
631 | lreg t4, R_T4*R_SZ(sp) |
---|
632 | lreg t5, R_T5*R_SZ(sp) |
---|
633 | lreg t6, R_T6*R_SZ(sp) |
---|
634 | lreg t7, R_T7*R_SZ(sp) |
---|
635 | lreg t8, R_T8*R_SZ(sp) |
---|
636 | lreg t9, R_T9*R_SZ(sp) |
---|
637 | lreg gp, R_GP*R_SZ(sp) |
---|
638 | lreg fp, R_FP*R_SZ(sp) |
---|
639 | lreg ra, R_RA*R_SZ(sp) |
---|
640 | lreg a0, R_A0*R_SZ(sp) |
---|
641 | lreg a1, R_A1*R_SZ(sp) |
---|
642 | lreg v1, R_V1*R_SZ(sp) |
---|
643 | lreg v0, R_V0*R_SZ(sp) |
---|
644 | .set noat |
---|
645 | lreg AT, R_AT*R_SZ(sp) |
---|
646 | .set at |
---|
647 | |
---|
648 | stackadd sp,sp,EXCP_STACK_SIZE /* store ra on the stack */ |
---|
649 | |
---|
650 | #if USE_IDTKIT |
---|
651 | /* we handled exception, so return non-zero value */ |
---|
652 | li v0,1 |
---|
653 | #endif |
---|
654 | |
---|
655 | _ISR_Handler_quick_exit: |
---|
656 | #ifdef USE_IDTKIT |
---|
657 | j ra |
---|
658 | #else |
---|
659 | eret |
---|
660 | #endif |
---|
661 | nop |
---|
662 | |
---|
663 | _ISR_Handler_prom_exit: |
---|
664 | #ifdef CPU_R3000 |
---|
665 | la k0, (R_VEC+((48)*8)) |
---|
666 | #endif |
---|
667 | |
---|
668 | #ifdef CPU_R4000 |
---|
669 | la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ |
---|
670 | #endif |
---|
671 | j k0 |
---|
672 | nop |
---|
673 | |
---|
674 | .set reorder |
---|
675 | |
---|
676 | ENDFRAME(_ISR_Handler) |
---|
677 | |
---|
678 | |
---|
679 | FRAME(mips_enable_interrupts,sp,0,ra) |
---|
680 | mfc0 t0,C0_SR /* get status reg */ |
---|
681 | nop |
---|
682 | or t0,t0,a0 |
---|
683 | mtc0 t0,C0_SR /* save updated status reg */ |
---|
684 | j ra |
---|
685 | nop |
---|
686 | ENDFRAME(mips_enable_interrupts) |
---|
687 | |
---|
688 | FRAME(mips_disable_interrupts,sp,0,ra) |
---|
689 | mfc0 v0,C0_SR /* get status reg */ |
---|
690 | li t1,SR_IMASK /* t1 = load interrupt mask word */ |
---|
691 | not t0,t1 /* t0 = ~t1 */ |
---|
692 | and t0,v0 /* clear imask bits */ |
---|
693 | mtc0 t0,C0_SR /* save status reg */ |
---|
694 | and v0,t1 /* mask return value (only return imask bits) */ |
---|
695 | jr ra |
---|
696 | nop |
---|
697 | ENDFRAME(mips_disable_interrupts) |
---|
698 | |
---|
699 | FRAME(mips_enable_global_interrupts,sp,0,ra) |
---|
700 | mfc0 t0,C0_SR /* get status reg */ |
---|
701 | nop |
---|
702 | ori t0,SR_IE |
---|
703 | mtc0 t0,C0_SR /* save updated status reg */ |
---|
704 | j ra |
---|
705 | nop |
---|
706 | ENDFRAME(mips_enable_global_interrupts) |
---|
707 | |
---|
708 | FRAME(mips_disable_global_interrupts,sp,0,ra) |
---|
709 | li t1,SR_IE |
---|
710 | mfc0 t0,C0_SR /* get status reg */ |
---|
711 | not t1 |
---|
712 | and t0,t1 |
---|
713 | mtc0 t0,C0_SR /* save updated status reg */ |
---|
714 | j ra |
---|
715 | nop |
---|
716 | ENDFRAME(mips_disable_global_interrupts) |
---|
717 | |
---|
718 | /* return the value of the status register in v0. Used for debugging */ |
---|
719 | FRAME(mips_get_sr,sp,0,ra) |
---|
720 | mfc0 v0,C0_SR |
---|
721 | j ra |
---|
722 | nop |
---|
723 | ENDFRAME(mips_get_sr) |
---|
724 | |
---|
725 | FRAME(mips_break,sp,0,ra) |
---|
726 | #if 1 |
---|
727 | break 0x0 |
---|
728 | j mips_break |
---|
729 | #else |
---|
730 | j ra |
---|
731 | #endif |
---|
732 | nop |
---|
733 | ENDFRAME(mips_break) |
---|
734 | |
---|
735 | /*PAGE |
---|
736 | * |
---|
737 | * _CPU_Internal_threads_Idle_thread_body |
---|
738 | * |
---|
739 | * NOTES: |
---|
740 | * |
---|
741 | * 1. This is the same as the regular CPU independent algorithm. |
---|
742 | * |
---|
743 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
---|
744 | * instruction, then don't forget to put it in an infinite loop. |
---|
745 | * |
---|
746 | * 3. Be warned. Some processors with onboard DMA have been known |
---|
747 | * to stop the DMA if the CPU were put in IDLE mode. This might |
---|
748 | * also be a problem with other on-chip peripherals. So use this |
---|
749 | * hook with caution. |
---|
750 | */ |
---|
751 | |
---|
752 | FRAME(_CPU_Thread_Idle_body,sp,0,ra) |
---|
753 | wait /* enter low power mode */ |
---|
754 | j _CPU_Thread_Idle_body |
---|
755 | nop |
---|
756 | ENDFRAME(_CPU_Thread_Idle_body) |
---|
757 | |
---|
758 | #define VEC_CODE_LENGTH 10*4 |
---|
759 | |
---|
760 | /************************************************************************** |
---|
761 | ** |
---|
762 | ** init_exc_vecs() - moves the exception code into the addresses |
---|
763 | ** reserved for exception vectors |
---|
764 | ** |
---|
765 | ** UTLB Miss exception vector at address 0x80000000 |
---|
766 | ** |
---|
767 | ** General exception vector at address 0x80000080 |
---|
768 | ** |
---|
769 | ** RESET exception vector is at address 0xbfc00000 |
---|
770 | ** |
---|
771 | ***************************************************************************/ |
---|
772 | |
---|
773 | #define INITEXCFRM ((2*4)+4) /* ra + 2 arguments */ |
---|
774 | FRAME(init_exc_vecs,sp,0,ra) |
---|
775 | /* This code yanked from SIM */ |
---|
776 | #if defined(CPU_R3000) |
---|
777 | .set noreorder |
---|
778 | la t1,exc_utlb_code |
---|
779 | la t2,exc_norm_code |
---|
780 | li t3,UT_VEC |
---|
781 | li t4,E_VEC |
---|
782 | li t5,VEC_CODE_LENGTH |
---|
783 | 1: |
---|
784 | lw t6,0(t1) |
---|
785 | lw t7,0(t2) |
---|
786 | sw t6,0(t3) |
---|
787 | sw t7,0(t4) |
---|
788 | addiu t1,4 |
---|
789 | addiu t3,4 |
---|
790 | addiu t4,4 |
---|
791 | subu t5,4 |
---|
792 | bne t5,zero,1b |
---|
793 | addiu t2,4 |
---|
794 | move t5,ra # assumes clear_cache doesnt use t5 |
---|
795 | li a0,UT_VEC |
---|
796 | jal clear_cache |
---|
797 | li a1,VEC_CODE_LENGTH |
---|
798 | nop |
---|
799 | li a0,E_VEC |
---|
800 | jal clear_cache |
---|
801 | li a1,VEC_CODE_LENGTH |
---|
802 | move ra,t5 # restore ra |
---|
803 | j ra |
---|
804 | nop |
---|
805 | .set reorder |
---|
806 | #endif |
---|
807 | #if defined(CPU_R4000) |
---|
808 | .set reorder |
---|
809 | move t5,ra # assumes clear_cache doesnt use t5 |
---|
810 | |
---|
811 | /* TLB exception vector */ |
---|
812 | la t1,exc_tlb_code |
---|
813 | li t2,T_VEC |K1BASE |
---|
814 | li t3,VEC_CODE_LENGTH |
---|
815 | 1: |
---|
816 | lw t6,0(t1) |
---|
817 | addiu t1,4 |
---|
818 | subu t3,4 |
---|
819 | sw t6,0(t2) |
---|
820 | addiu t2,4 |
---|
821 | bne t3,zero,1b |
---|
822 | |
---|
823 | li a0,T_VEC |
---|
824 | li a1,VEC_CODE_LENGTH |
---|
825 | jal clear_cache |
---|
826 | |
---|
827 | la t1,exc_xtlb_code |
---|
828 | li t2,X_VEC |K1BASE |
---|
829 | li t3,VEC_CODE_LENGTH |
---|
830 | 1: |
---|
831 | lw t6,0(t1) |
---|
832 | addiu t1,4 |
---|
833 | subu t3,4 |
---|
834 | sw t6,0(t2) |
---|
835 | addiu t2,4 |
---|
836 | bne t3,zero,1b |
---|
837 | |
---|
838 | /* extended TLB exception vector */ |
---|
839 | li a0,X_VEC |
---|
840 | li a1,VEC_CODE_LENGTH |
---|
841 | jal clear_cache |
---|
842 | |
---|
843 | /* cache error exception vector */ |
---|
844 | la t1,exc_cache_code |
---|
845 | li t2,C_VEC |K1BASE |
---|
846 | li t3,VEC_CODE_LENGTH |
---|
847 | 1: |
---|
848 | lw t6,0(t1) |
---|
849 | addiu t1,4 |
---|
850 | subu t3,4 |
---|
851 | sw t6,0(t2) |
---|
852 | addiu t2,4 |
---|
853 | bne t3,zero,1b |
---|
854 | |
---|
855 | li a0,C_VEC |
---|
856 | li a1,VEC_CODE_LENGTH |
---|
857 | jal clear_cache |
---|
858 | |
---|
859 | /* normal exception vector */ |
---|
860 | la t1,exc_norm_code |
---|
861 | li t2,E_VEC |K1BASE |
---|
862 | li t3,VEC_CODE_LENGTH |
---|
863 | 1: |
---|
864 | lw t6,0(t1) |
---|
865 | addiu t1,4 |
---|
866 | subu t3,4 |
---|
867 | sw t6,0(t2) |
---|
868 | addiu t2,4 |
---|
869 | bne t3,zero,1b |
---|
870 | |
---|
871 | li a0,E_VEC |
---|
872 | li a1,VEC_CODE_LENGTH |
---|
873 | jal clear_cache |
---|
874 | |
---|
875 | move ra,t5 # restore ra |
---|
876 | j ra |
---|
877 | #endif |
---|
878 | ENDFRAME(init_exc_vecs) |
---|
879 | |
---|
880 | |
---|
881 | #if defined(CPU_R4000) |
---|
882 | FRAME(exc_tlb_code,sp,0,ra) |
---|
883 | #ifdef CPU_R3000 |
---|
884 | la k0, (R_VEC+((48)*8)) |
---|
885 | #endif |
---|
886 | |
---|
887 | #ifdef CPU_R4000 |
---|
888 | la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ |
---|
889 | #endif |
---|
890 | j k0 |
---|
891 | nop |
---|
892 | |
---|
893 | ENDFRAME(exc_tlb_code) |
---|
894 | |
---|
895 | |
---|
896 | FRAME(exc_xtlb_code,sp,0,ra) |
---|
897 | #ifdef CPU_R3000 |
---|
898 | la k0, (R_VEC+((48)*8)) |
---|
899 | #endif |
---|
900 | |
---|
901 | #ifdef CPU_R4000 |
---|
902 | la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ |
---|
903 | #endif |
---|
904 | j k0 |
---|
905 | nop |
---|
906 | |
---|
907 | ENDFRAME(exc_xtlb_code) |
---|
908 | |
---|
909 | |
---|
910 | FRAME(exc_cache_code,sp,0,ra) |
---|
911 | #ifdef CPU_R3000 |
---|
912 | la k0, (R_VEC+((48)*8)) |
---|
913 | #endif |
---|
914 | |
---|
915 | #ifdef CPU_R4000 |
---|
916 | la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ |
---|
917 | #endif |
---|
918 | j k0 |
---|
919 | nop |
---|
920 | |
---|
921 | ENDFRAME(exc_cache_code) |
---|
922 | |
---|
923 | |
---|
924 | FRAME(exc_norm_code,sp,0,ra) |
---|
925 | la k0, _ISR_Handler /* generic external int hndlr */ |
---|
926 | j k0 |
---|
927 | nop |
---|
928 | subu sp, EXCP_STACK_SIZE /* set up local stack frame */ |
---|
929 | ENDFRAME(exc_norm_code) |
---|
930 | #endif |
---|
931 | |
---|
932 | /************************************************************************** |
---|
933 | ** |
---|
934 | ** enable_int(mask) - enables interrupts - mask is positioned so it only |
---|
935 | ** needs to be or'ed into the status reg. This |
---|
936 | ** also does some other things !!!! caution should |
---|
937 | ** be used if invoking this while in the middle |
---|
938 | ** of a debugging session where the client may have |
---|
939 | ** nested interrupts. |
---|
940 | ** |
---|
941 | ****************************************************************************/ |
---|
942 | FRAME(enable_int,sp,0,ra) |
---|
943 | .set noreorder |
---|
944 | mfc0 t0,C0_SR |
---|
945 | or a0,1 |
---|
946 | or t0,a0 |
---|
947 | mtc0 t0,C0_SR |
---|
948 | j ra |
---|
949 | nop |
---|
950 | .set reorder |
---|
951 | ENDFRAME(enable_int) |
---|
952 | |
---|
953 | |
---|
954 | /*************************************************************************** |
---|
955 | ** |
---|
956 | ** disable_int(mask) - disable the interrupt - mask is the complement |
---|
957 | ** of the bits to be cleared - i.e. to clear ext int |
---|
958 | ** 5 the mask would be - 0xffff7fff |
---|
959 | ** |
---|
960 | ****************************************************************************/ |
---|
961 | FRAME(disable_int,sp,0,ra) |
---|
962 | .set noreorder |
---|
963 | mfc0 t0,C0_SR |
---|
964 | nop |
---|
965 | and t0,a0 |
---|
966 | mtc0 t0,C0_SR |
---|
967 | j ra |
---|
968 | nop |
---|
969 | ENDFRAME(disable_int) |
---|
970 | |
---|
971 | |
---|