1 | /* |
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2 | * Mips CPU Dependent Source |
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3 | * |
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4 | * Author: Craig Lebakken <craigl@transition.com> |
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5 | * |
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6 | * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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7 | * |
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8 | * To anyone who acknowledges that this file is provided "AS IS" |
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9 | * without any express or implied warranty: |
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10 | * permission to use, copy, modify, and distribute this file |
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11 | * for any purpose is hereby granted without fee, provided that |
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12 | * the above copyright notice and this notice appears in all |
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13 | * copies, and that the name of Transition Networks not be used in |
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14 | * advertising or publicity pertaining to distribution of the |
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15 | * software without specific, written prior permission. |
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16 | * Transition Networks makes no representations about the suitability |
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17 | * of this software for any purpose. |
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18 | * |
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19 | * Derived from source copyrighted as follows: |
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20 | * |
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21 | * COPYRIGHT (c) 1989-1999. |
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22 | * On-Line Applications Research Corporation (OAR). |
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23 | * |
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24 | * The license and distribution terms for this file may be |
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25 | * found in the file LICENSE in this distribution or at |
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26 | * http://www.rtems.com/license/LICENSE. |
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27 | * |
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28 | * $Id$ |
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29 | */ |
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30 | |
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31 | /* |
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32 | * Rather than deleting this, it is commented out to (hopefully) help |
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33 | * the submitter send updates. |
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34 | * |
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35 | * static char _sccsid[] = "@(#)cpu.c 08/20/96 1.5\n"; |
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36 | */ |
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37 | |
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38 | #include <rtems/system.h> |
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39 | #include <rtems/score/isr.h> |
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40 | #include <rtems/score/wkspace.h> |
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41 | |
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42 | |
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43 | /* _CPU_Initialize |
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44 | * |
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45 | * This routine performs processor dependent initialization. |
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46 | * |
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47 | * INPUT PARAMETERS: |
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48 | * cpu_table - CPU table to initialize |
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49 | * thread_dispatch - address of disptaching routine |
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50 | */ |
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51 | |
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52 | |
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53 | void null_handler( void ) |
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54 | { |
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55 | } |
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56 | |
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57 | |
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58 | void _CPU_Initialize( |
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59 | rtems_cpu_table *cpu_table, |
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60 | void (*thread_dispatch) /* ignored on this CPU */ |
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61 | ) |
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62 | { |
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63 | unsigned int i = ISR_NUMBER_OF_VECTORS; |
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64 | |
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65 | while ( i-- ) |
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66 | { |
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67 | _ISR_Vector_table[i] = (ISR_Handler_entry)null_handler; |
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68 | } |
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69 | |
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70 | /* |
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71 | * The thread_dispatch argument is the address of the entry point |
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72 | * for the routine called at the end of an ISR once it has been |
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73 | * decided a context switch is necessary. On some compilation |
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74 | * systems it is difficult to call a high-level language routine |
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75 | * from assembly. This allows us to trick these systems. |
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76 | * |
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77 | * If you encounter this problem save the entry point in a CPU |
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78 | * dependent variable. |
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79 | */ |
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80 | |
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81 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
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82 | |
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83 | /* |
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84 | * If there is not an easy way to initialize the FP context |
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85 | * during Context_Initialize, then it is usually easier to |
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86 | * save an "uninitialized" FP context here and copy it to |
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87 | * the task's during Context_Initialize. |
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88 | */ |
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89 | |
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90 | /* FP context initialization support goes here */ |
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91 | |
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92 | _CPU_Table = *cpu_table; |
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93 | |
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94 | } |
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95 | |
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96 | /*PAGE |
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97 | * |
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98 | * _CPU_ISR_Get_level |
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99 | */ |
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100 | |
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101 | #if 0 /* located in cpu_asm.S */ |
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102 | unsigned32 _CPU_ISR_Get_level( void ) |
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103 | { |
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104 | /* |
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105 | * This routine returns the current interrupt level. |
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106 | */ |
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107 | } |
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108 | #endif |
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109 | |
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110 | /*PAGE |
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111 | * |
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112 | * _CPU_ISR_install_raw_handler |
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113 | */ |
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114 | |
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115 | void _CPU_ISR_install_raw_handler( |
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116 | unsigned32 vector, |
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117 | proc_ptr new_handler, |
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118 | proc_ptr *old_handler |
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119 | ) |
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120 | { |
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121 | /* |
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122 | * This is where we install the interrupt handler into the "raw" interrupt |
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123 | * table used by the CPU to dispatch interrupt handlers. |
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124 | */ |
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125 | |
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126 | #if 0 /* not necessary */ |
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127 | /* use IDT/Sim to set interrupt vector. Needed to co-exist with debugger. */ |
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128 | add_ext_int_func( vector, new_handler ); |
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129 | #endif |
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130 | } |
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131 | |
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132 | /*PAGE |
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133 | * |
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134 | * _CPU_ISR_install_vector |
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135 | * |
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136 | * This kernel routine installs the RTEMS handler for the |
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137 | * specified vector. |
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138 | * |
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139 | * Input parameters: |
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140 | * vector - interrupt vector number |
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141 | * old_handler - former ISR for this vector number |
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142 | * new_handler - replacement ISR for this vector number |
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143 | * |
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144 | * Output parameters: NONE |
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145 | * |
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146 | */ |
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147 | |
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148 | void _CPU_ISR_install_vector( |
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149 | unsigned32 vector, |
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150 | proc_ptr new_handler, |
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151 | proc_ptr *old_handler |
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152 | ) |
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153 | { |
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154 | *old_handler = _ISR_Vector_table[ vector ]; |
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155 | |
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156 | /* |
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157 | * If the interrupt vector table is a table of pointer to isr entry |
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158 | * points, then we need to install the appropriate RTEMS interrupt |
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159 | * handler for this vector number. |
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160 | */ |
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161 | |
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162 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler ); |
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163 | |
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164 | /* |
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165 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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166 | * be used by the _ISR_Handler so the user gets control. |
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167 | */ |
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168 | |
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169 | _ISR_Vector_table[ vector ] = new_handler; |
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170 | } |
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171 | |
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172 | /*PAGE |
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173 | * |
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174 | * _CPU_Install_interrupt_stack |
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175 | */ |
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176 | |
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177 | void _CPU_Install_interrupt_stack( void ) |
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178 | { |
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179 | /* we don't support this yet */ |
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180 | } |
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181 | |
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182 | /*PAGE |
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183 | * |
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184 | * _CPU_Internal_threads_Idle_thread_body |
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185 | * |
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186 | * NOTES: |
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187 | * |
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188 | * 1. This is the same as the regular CPU independent algorithm. |
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189 | * |
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190 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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191 | * instruction, then don't forget to put it in an infinite loop. |
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192 | * |
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193 | * 3. Be warned. Some processors with onboard DMA have been known |
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194 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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195 | * also be a problem with other on-chip peripherals. So use this |
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196 | * hook with caution. |
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197 | */ |
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198 | |
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199 | #if 0 /* located in cpu_asm.S */ |
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200 | void _CPU_Thread_Idle_body( void ) |
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201 | { |
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202 | |
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203 | for( ; ; ) |
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204 | /* insert your "halt" instruction here */ ; |
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205 | } |
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206 | #endif |
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207 | |
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208 | extern void mips_break( int error ); |
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209 | |
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210 | #include <stdio.h> |
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211 | |
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212 | void mips_fatal_error( int error ) |
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213 | { |
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214 | printf("fatal error 0x%x %d\n",error,error); |
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215 | mips_break( error ); |
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216 | } |
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