1 | /** |
---|
2 | * @file rtems/score/mips.h |
---|
3 | */ |
---|
4 | |
---|
5 | /* |
---|
6 | * COPYRIGHT (c) 1989-2001. |
---|
7 | * On-Line Applications Research Corporation (OAR). |
---|
8 | * |
---|
9 | * The license and distribution terms for this file may be |
---|
10 | * found in the file LICENSE in this distribution or at |
---|
11 | * http://www.rtems.com/license/LICENSE. |
---|
12 | * |
---|
13 | * $Id$ |
---|
14 | */ |
---|
15 | |
---|
16 | #ifndef _RTEMS_SCORE_MIPS_H |
---|
17 | #define _RTEMS_SCORE_MIPS_H |
---|
18 | |
---|
19 | #ifdef __cplusplus |
---|
20 | extern "C" { |
---|
21 | #endif |
---|
22 | |
---|
23 | #ifndef ASM |
---|
24 | #include <rtems/mips/idtcpu.h> |
---|
25 | #endif |
---|
26 | |
---|
27 | /* |
---|
28 | * SR bits that enable/disable interrupts |
---|
29 | * |
---|
30 | * NOTE: XXX what about SR_ERL? |
---|
31 | */ |
---|
32 | |
---|
33 | #if (__mips == 3) || (__mips == 32) |
---|
34 | #ifdef ASM |
---|
35 | #define SR_INTERRUPT_ENABLE_BITS 0x01 |
---|
36 | #else |
---|
37 | #define SR_INTERRUPT_ENABLE_BITS SR_IE |
---|
38 | #endif |
---|
39 | |
---|
40 | #elif __mips == 1 |
---|
41 | #define SR_INTERRUPT_ENABLE_BITS SR_IEC |
---|
42 | |
---|
43 | #else |
---|
44 | #error "mips interrupt enable bits: unknown architecture level!" |
---|
45 | #endif |
---|
46 | |
---|
47 | /* |
---|
48 | * This file contains the information required to build |
---|
49 | * RTEMS for a particular member of the "no cpu" |
---|
50 | * family when executing in protected mode. It does |
---|
51 | * this by setting variables to indicate which implementation |
---|
52 | * dependent features are present in a particular member |
---|
53 | * of the family. |
---|
54 | */ |
---|
55 | |
---|
56 | #if defined(__mips_soft_float) |
---|
57 | #define MIPS_HAS_FPU 0 |
---|
58 | #else |
---|
59 | #define MIPS_HAS_FPU 1 |
---|
60 | #endif |
---|
61 | |
---|
62 | |
---|
63 | #if (__mips == 1) |
---|
64 | #define CPU_MODEL_NAME "ISA Level 1 or 2" |
---|
65 | #elif (__mips == 3) || (__mips == 32) |
---|
66 | #if defined(__mips64) |
---|
67 | #define CPU_MODEL_NAME "ISA Level 4" |
---|
68 | #else |
---|
69 | #define CPU_MODEL_NAME "ISA Level 3" |
---|
70 | #endif |
---|
71 | #else |
---|
72 | #error "Unknown MIPS ISA level" |
---|
73 | #endif |
---|
74 | |
---|
75 | /* |
---|
76 | * Define the name of the CPU family. |
---|
77 | */ |
---|
78 | |
---|
79 | #define CPU_NAME "MIPS" |
---|
80 | |
---|
81 | /* |
---|
82 | * RTEMS Vector numbers for exception conditions. This is a direct |
---|
83 | * map to the causes. |
---|
84 | */ |
---|
85 | |
---|
86 | #define MIPS_EXCEPTION_BASE 0 |
---|
87 | |
---|
88 | #define MIPS_EXCEPTION_INT MIPS_EXCEPTION_BASE+0 |
---|
89 | #define MIPS_EXCEPTION_MOD MIPS_EXCEPTION_BASE+1 |
---|
90 | #define MIPS_EXCEPTION_TLBL MIPS_EXCEPTION_BASE+2 |
---|
91 | #define MIPS_EXCEPTION_TLBS MIPS_EXCEPTION_BASE+3 |
---|
92 | #define MIPS_EXCEPTION_ADEL MIPS_EXCEPTION_BASE+4 |
---|
93 | #define MIPS_EXCEPTION_ADES MIPS_EXCEPTION_BASE+5 |
---|
94 | #define MIPS_EXCEPTION_IBE MIPS_EXCEPTION_BASE+6 |
---|
95 | #define MIPS_EXCEPTION_DBE MIPS_EXCEPTION_BASE+7 |
---|
96 | #define MIPS_EXCEPTION_SYSCALL MIPS_EXCEPTION_BASE+8 |
---|
97 | #define MIPS_EXCEPTION_BREAK MIPS_EXCEPTION_BASE+9 |
---|
98 | #define MIPS_EXCEPTION_RI MIPS_EXCEPTION_BASE+10 |
---|
99 | #define MIPS_EXCEPTION_CPU MIPS_EXCEPTION_BASE+11 |
---|
100 | #define MIPS_EXCEPTION_OVERFLOW MIPS_EXCEPTION_BASE+12 |
---|
101 | #define MIPS_EXCEPTION_TRAP MIPS_EXCEPTION_BASE+13 |
---|
102 | #define MIPS_EXCEPTION_VCEI MIPS_EXCEPTION_BASE+14 |
---|
103 | /* FPE only on mips2 and higher */ |
---|
104 | #define MIPS_EXCEPTION_FPE MIPS_EXCEPTION_BASE+15 |
---|
105 | #define MIPS_EXCEPTION_C2E MIPS_EXCEPTION_BASE+16 |
---|
106 | /* 17-22 reserved */ |
---|
107 | #define MIPS_EXCEPTION_WATCH MIPS_EXCEPTION_BASE+23 |
---|
108 | /* 24-30 reserved */ |
---|
109 | #define MIPS_EXCEPTION_VCED MIPS_EXCEPTION_BASE+31 |
---|
110 | |
---|
111 | #define MIPS_INTERRUPT_BASE MIPS_EXCEPTION_BASE+32 |
---|
112 | |
---|
113 | /* |
---|
114 | * Some macros to access registers |
---|
115 | */ |
---|
116 | |
---|
117 | #define mips_get_sr( _x ) \ |
---|
118 | do { \ |
---|
119 | asm volatile( "mfc0 %0, $12; nop" : "=r" (_x) : ); \ |
---|
120 | } while (0) |
---|
121 | |
---|
122 | #define mips_set_sr( _x ) \ |
---|
123 | do { \ |
---|
124 | register unsigned int __x = (_x); \ |
---|
125 | asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \ |
---|
126 | } while (0) |
---|
127 | |
---|
128 | |
---|
129 | /* |
---|
130 | * Access the Cause register |
---|
131 | */ |
---|
132 | |
---|
133 | #define mips_get_cause( _x ) \ |
---|
134 | do { \ |
---|
135 | asm volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \ |
---|
136 | } while (0) |
---|
137 | |
---|
138 | |
---|
139 | #define mips_set_cause( _x ) \ |
---|
140 | do { \ |
---|
141 | register unsigned int __x = (_x); \ |
---|
142 | asm volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \ |
---|
143 | } while (0) |
---|
144 | |
---|
145 | |
---|
146 | |
---|
147 | |
---|
148 | /* |
---|
149 | * Access the Debug Cache Invalidate Control register |
---|
150 | */ |
---|
151 | |
---|
152 | #define mips_get_dcic( _x ) \ |
---|
153 | do { \ |
---|
154 | asm volatile( "mfc0 %0, $7; nop" : "=r" (_x) : ); \ |
---|
155 | } while (0) |
---|
156 | |
---|
157 | |
---|
158 | #define mips_set_dcic( _x ) \ |
---|
159 | do { \ |
---|
160 | register unsigned int __x = (_x); \ |
---|
161 | asm volatile( "mtc0 %0, $7; nop" : : "r" (__x) ); \ |
---|
162 | } while (0) |
---|
163 | |
---|
164 | |
---|
165 | |
---|
166 | |
---|
167 | /* |
---|
168 | * Access the Breakpoint Program Counter & Mask registers |
---|
169 | * (_x for BPC, _y for mask) |
---|
170 | */ |
---|
171 | |
---|
172 | #define mips_get_bpcrm( _x, _y ) \ |
---|
173 | do { \ |
---|
174 | asm volatile( "mfc0 %0, $3; nop" : "=r" (_x) : ); \ |
---|
175 | asm volatile( "mfc0 %0, $11; nop" : "=r" (_y) : ); \ |
---|
176 | } while (0) |
---|
177 | |
---|
178 | |
---|
179 | #define mips_set_bpcrm( _x, _y ) \ |
---|
180 | do { \ |
---|
181 | register unsigned int __x = (_x); \ |
---|
182 | register unsigned int __y = (_y); \ |
---|
183 | asm volatile( "mtc0 %0, $11; nop" : : "r" (__y) ); \ |
---|
184 | asm volatile( "mtc0 %0, $3; nop" : : "r" (__x) ); \ |
---|
185 | } while (0) |
---|
186 | |
---|
187 | |
---|
188 | |
---|
189 | |
---|
190 | |
---|
191 | |
---|
192 | /* |
---|
193 | * Access the Breakpoint Data Address & Mask registers |
---|
194 | * (_x for BDA, _y for mask) |
---|
195 | */ |
---|
196 | |
---|
197 | #define mips_get_bdarm( _x, _y ) \ |
---|
198 | do { \ |
---|
199 | asm volatile( "mfc0 %0, $5; nop" : "=r" (_x) : ); \ |
---|
200 | asm volatile( "mfc0 %0, $9; nop" : "=r" (_y) : ); \ |
---|
201 | } while (0) |
---|
202 | |
---|
203 | |
---|
204 | #define mips_set_bdarm( _x, _y ) \ |
---|
205 | do { \ |
---|
206 | register unsigned int __x = (_x); \ |
---|
207 | register unsigned int __y = (_y); \ |
---|
208 | asm volatile( "mtc0 %0, $9; nop" : : "r" (__y) ); \ |
---|
209 | asm volatile( "mtc0 %0, $5; nop" : : "r" (__x) ); \ |
---|
210 | } while (0) |
---|
211 | |
---|
212 | |
---|
213 | |
---|
214 | |
---|
215 | |
---|
216 | |
---|
217 | |
---|
218 | /* |
---|
219 | * Access FCR31 |
---|
220 | */ |
---|
221 | |
---|
222 | #if ( MIPS_HAS_FPU == 1 ) |
---|
223 | |
---|
224 | #define mips_get_fcr31( _x ) \ |
---|
225 | do { \ |
---|
226 | asm volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \ |
---|
227 | } while(0) |
---|
228 | |
---|
229 | |
---|
230 | #define mips_set_fcr31( _x ) \ |
---|
231 | do { \ |
---|
232 | register unsigned int __x = (_x); \ |
---|
233 | asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \ |
---|
234 | } while(0) |
---|
235 | |
---|
236 | #else |
---|
237 | |
---|
238 | #define mips_get_fcr31( _x ) |
---|
239 | #define mips_set_fcr31( _x ) |
---|
240 | |
---|
241 | #endif |
---|
242 | |
---|
243 | /* |
---|
244 | * Manipulate interrupt mask |
---|
245 | * |
---|
246 | * mips_unmask_interrupt( _mask) |
---|
247 | * enables interrupts - mask is positioned so it only needs to be or'ed |
---|
248 | * into the status reg. This also does some other things !!!! Caution |
---|
249 | * should be used if invoking this while in the middle of a debugging |
---|
250 | * session where the client may have nested interrupts. |
---|
251 | * |
---|
252 | * mips_mask_interrupt( _mask ) |
---|
253 | * disable the interrupt - mask is the complement of the bits to be |
---|
254 | * cleared - i.e. to clear ext int 5 the mask would be - 0xffff7fff |
---|
255 | * |
---|
256 | * |
---|
257 | * NOTE: mips_mask_interrupt() used to be disable_int(). |
---|
258 | * mips_unmask_interrupt() used to be enable_int(). |
---|
259 | * |
---|
260 | */ |
---|
261 | |
---|
262 | #define mips_enable_in_interrupt_mask( _mask ) \ |
---|
263 | do { \ |
---|
264 | unsigned int _sr; \ |
---|
265 | mips_get_sr( _sr ); \ |
---|
266 | _sr |= (_mask); \ |
---|
267 | mips_set_sr( _sr ); \ |
---|
268 | } while (0) |
---|
269 | |
---|
270 | #define mips_disable_in_interrupt_mask( _mask ) \ |
---|
271 | do { \ |
---|
272 | unsigned int _sr; \ |
---|
273 | mips_get_sr( _sr ); \ |
---|
274 | _sr &= ~(_mask); \ |
---|
275 | mips_set_sr( _sr ); \ |
---|
276 | } while (0) |
---|
277 | |
---|
278 | #ifdef __cplusplus |
---|
279 | } |
---|
280 | #endif |
---|
281 | |
---|
282 | #endif /* ! _INCLUDE_MIPS_h */ |
---|
283 | /* end of include file */ |
---|