source: rtems/cpukit/score/cpu/mips/rtems/score/mips.h @ 32f415d

4.104.114.84.95
Last change on this file since 32f415d was 32f415d, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 13, 2000 at 6:09:48 PM

2000-12-13 Joel Sherrill <joel@…>

  • cpu_asm.h: Removed.
  • Makefile.am: Remove cpu_asm.h.
  • rtems/score/mips64orion.h: Renamed mips.h.
  • rtems/score/mips.h: New file, formerly mips64orion.h. Header rewritten. (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask, mips_disable_in_interrupt_mask): New macros.
  • rtems/score/Makefile.am: Reflect renaming mips64orion.h.
  • asm.h: Include <mips.h> not <mips64orion.h>. Now includes the few defines that were in <cpu_asm.h>.
  • cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine. MIPS ISA 3 is still in assembly for now. (_CPU_Thread_Idle_body): Rewrote in C.
  • cpu_asm.S: Rewrote file header. (FRAME,ENDFRAME) now in asm.h. (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C. (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C. (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and leaves other bits in SR alone on task switch. (mips_enable_interrupts,mips_disable_interrupts, mips_enable_global_interrupts,mips_disable_global_interrupts, disable_int, enable_int): Removed. (mips_get_sr): Rewritten as C macro. (_CPU_Thread_Idle_body): Rewritten in C. (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and placed in libcpu. (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved to libcpu/mips/shared/interrupts. (general): Cleaned up comment blocks and #if 0 areas.
  • idtcpu.h: Made ifdef report an error.
  • iregdef.h: Removed warning.
  • rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable number defined by libcpu. (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines to access SR. (_CPU_ISR_Set_level): Rewritten as macro for ISA I. (_CPU_Context_Initialize): Honor ISR level in task initialization. (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
  • Property mode set to 100644
File size: 2.5 KB
Line 
1/*  mips.h
2 *
3 *  COPYRIGHT (c) 1989-2000.
4 *  On-Line Applications Research Corporation (OAR).
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.OARcorp.com/rtems/license.html.
9 *
10 *  $Id$
11 */
12/* @(#)mips64orion.h       08/29/96     1.3 */
13
14#ifndef _INCLUDE_MIPS_h
15#define _INCLUDE_MIPS_h
16
17#ifdef __cplusplus
18extern "C" {
19#endif
20
21/*
22 *  This file contains the information required to build
23 *  RTEMS for a particular member of the "no cpu"
24 *  family when executing in protected mode.  It does
25 *  this by setting variables to indicate which implementation
26 *  dependent features are present in a particular member
27 *  of the family.
28 */
29 
30#if defined(__mips_soft_float)
31#define MIPS_HAS_FPU 0
32#else
33#define MIPS_HAS_FPU 1
34#endif
35
36#if (__mips == 1)
37#define CPU_MODEL_NAME  "ISA Level 1 or 2"
38#elif (__mips == 3)
39#if defined(__mips64)
40#define CPU_MODEL_NAME  "ISA Level 4"
41#else
42#define CPU_MODEL_NAME  "ISA Level 3"
43#endif
44#else
45#error "Unknown MIPS ISA level"
46#endif
47
48/*
49 *  Define the name of the CPU family.
50 */
51
52#define CPU_NAME "MIPS"
53
54/*
55 *  Some macros to access registers
56 */
57
58#define mips_get_sr( _x ) \
59  do { \
60    asm volatile( "mfc0 %0, $12; nop" : "=g" (_x) :  ); \
61  } while (0)
62
63#define mips_set_sr( _x ) \
64  do { \
65    unsigned int __x = (_x); \
66    asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \
67  } while (0)
68
69/*
70 *  Manipulate interrupt mask
71 *
72 *  mips_unmask_interrupt( _mask)
73 *    enables interrupts - mask is positioned so it only needs to be or'ed
74 *    into the status reg. This also does some other things !!!! Caution
75 *    should be used if invoking this while in the middle of a debugging
76 *    session where the client may have nested interrupts.
77 *
78 *  mips_mask_interrupt( _mask )
79 *    disable the interrupt - mask is the complement of the bits to be
80 *    cleared - i.e. to clear ext int 5 the mask would be - 0xffff7fff
81 *
82 *
83 *  NOTE: mips_mask_interrupt() used to be disable_int().
84 *        mips_unmask_interrupt() used to be enable_int().
85 *
86 */
87
88#define mips_enable_in_interrupt_mask( _mask ) \
89  do { \
90    unsigned int _sr; \
91    mips_get_sr( _sr ); \
92    _sr |= (_mask) | SR_IEC; \
93    mips_set_sr( _sr ); \
94  } while (0)
95
96#define mips_disable_in_interrupt_mask( _mask ) \
97  do { \
98    unsigned int _sr; \
99    mips_get_sr( _sr ); \
100    _sr &= ~(_mask); \
101    mips_set_sr( _sr ); \
102  } while (0)
103
104#ifdef __cplusplus
105}
106#endif
107
108#endif /* ! _INCLUDE_MIPS_h */
109/* end of include file */
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