source: rtems/cpukit/score/cpu/mips/rtems/score/mips.h @ 1800f717

4.104.114.84.95
Last change on this file since 1800f717 was 1800f717, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 8, 2001 at 6:16:51 PM

2001-01-08 Joel Sherrill <joel@…>

  • idtcpu.h: Commented out definition of "wait". It was stupid to use such a common word as a macro.
  • rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
  • rtems/score/mips.h: Added include of <idtcpu.h>.
  • rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
  • Property mode set to 100644
File size: 2.5 KB
Line 
1/*  mips.h
2 *
3 *  COPYRIGHT (c) 1989-2000.
4 *  On-Line Applications Research Corporation (OAR).
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.OARcorp.com/rtems/license.html.
9 *
10 *  $Id$
11 */
12/* @(#)mips64orion.h       08/29/96     1.3 */
13
14#ifndef _INCLUDE_MIPS_h
15#define _INCLUDE_MIPS_h
16
17#ifdef __cplusplus
18extern "C" {
19#endif
20
21#ifndef ASM
22#include <idtcpu.h>
23#endif
24
25/*
26 *  This file contains the information required to build
27 *  RTEMS for a particular member of the "no cpu"
28 *  family when executing in protected mode.  It does
29 *  this by setting variables to indicate which implementation
30 *  dependent features are present in a particular member
31 *  of the family.
32 */
33 
34#if defined(__mips_soft_float)
35#define MIPS_HAS_FPU 0
36#else
37#define MIPS_HAS_FPU 1
38#endif
39
40#if (__mips == 1)
41#define CPU_MODEL_NAME  "ISA Level 1 or 2"
42#elif (__mips == 3)
43#if defined(__mips64)
44#define CPU_MODEL_NAME  "ISA Level 4"
45#else
46#define CPU_MODEL_NAME  "ISA Level 3"
47#endif
48#else
49#error "Unknown MIPS ISA level"
50#endif
51
52/*
53 *  Define the name of the CPU family.
54 */
55
56#define CPU_NAME "MIPS"
57
58/*
59 *  Some macros to access registers
60 */
61
62#define mips_get_sr( _x ) \
63  do { \
64    asm volatile( "mfc0 %0, $12; nop" : "=g" (_x) :  ); \
65  } while (0)
66
67#define mips_set_sr( _x ) \
68  do { \
69    unsigned int __x = (_x); \
70    asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \
71  } while (0)
72
73/*
74 *  Manipulate interrupt mask
75 *
76 *  mips_unmask_interrupt( _mask)
77 *    enables interrupts - mask is positioned so it only needs to be or'ed
78 *    into the status reg. This also does some other things !!!! Caution
79 *    should be used if invoking this while in the middle of a debugging
80 *    session where the client may have nested interrupts.
81 *
82 *  mips_mask_interrupt( _mask )
83 *    disable the interrupt - mask is the complement of the bits to be
84 *    cleared - i.e. to clear ext int 5 the mask would be - 0xffff7fff
85 *
86 *
87 *  NOTE: mips_mask_interrupt() used to be disable_int().
88 *        mips_unmask_interrupt() used to be enable_int().
89 *
90 */
91
92#define mips_enable_in_interrupt_mask( _mask ) \
93  do { \
94    unsigned int _sr; \
95    mips_get_sr( _sr ); \
96    _sr |= (_mask); \
97    mips_set_sr( _sr ); \
98  } while (0)
99
100#define mips_disable_in_interrupt_mask( _mask ) \
101  do { \
102    unsigned int _sr; \
103    mips_get_sr( _sr ); \
104    _sr &= ~(_mask); \
105    mips_set_sr( _sr ); \
106  } while (0)
107
108#ifdef __cplusplus
109}
110#endif
111
112#endif /* ! _INCLUDE_MIPS_h */
113/* end of include file */
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