source: rtems/cpukit/score/cpu/mips/rtems/score/mips.h @ 16ad7ea

4.104.114.84.95
Last change on this file since 16ad7ea was 16ad7ea, checked in by Joel Sherrill <joel.sherrill@…>, on 01/09/01 at 16:48:26

2001-01-09 Joel Sherrill <joel@…>

  • cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants to make it easier to conditionalize the code for various ISA levels.
  • Property mode set to 100644
File size: 2.8 KB
Line 
1/*  mips.h
2 *
3 *  COPYRIGHT (c) 1989-2000.
4 *  On-Line Applications Research Corporation (OAR).
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.OARcorp.com/rtems/license.html.
9 *
10 *  $Id$
11 */
12/* @(#)mips64orion.h       08/29/96     1.3 */
13
14#ifndef _INCLUDE_MIPS_h
15#define _INCLUDE_MIPS_h
16
17#ifdef __cplusplus
18extern "C" {
19#endif
20
21#ifndef ASM
22#include <idtcpu.h>
23#endif
24
25/*
26 *  SR bits that enable/disable interrupts
27 *
28 *  NOTE: XXX what about SR_ERL?
29 */
30
31#if __mips == 3
32#ifdef ASM
33#define SR_INTERRUPT_ENABLE_BITS 0x03
34#else
35#define SR_INTERRUPT_ENABLE_BITS SR_IE|SR_EXL
36#endif
37#else
38#define SR_INTERRUPT_ENABLE_BITS SR_IEC
39#endif
40
41/*
42 *  This file contains the information required to build
43 *  RTEMS for a particular member of the "no cpu"
44 *  family when executing in protected mode.  It does
45 *  this by setting variables to indicate which implementation
46 *  dependent features are present in a particular member
47 *  of the family.
48 */
49 
50#if defined(__mips_soft_float)
51#define MIPS_HAS_FPU 0
52#else
53#define MIPS_HAS_FPU 1
54#endif
55
56#if (__mips == 1)
57#define CPU_MODEL_NAME  "ISA Level 1 or 2"
58#elif (__mips == 3)
59#if defined(__mips64)
60#define CPU_MODEL_NAME  "ISA Level 4"
61#else
62#define CPU_MODEL_NAME  "ISA Level 3"
63#endif
64#else
65#error "Unknown MIPS ISA level"
66#endif
67
68/*
69 *  Define the name of the CPU family.
70 */
71
72#define CPU_NAME "MIPS"
73
74/*
75 *  Some macros to access registers
76 */
77
78#define mips_get_sr( _x ) \
79  do { \
80    asm volatile( "mfc0 %0, $12; nop" : "=g" (_x) :  ); \
81  } while (0)
82
83#define mips_set_sr( _x ) \
84  do { \
85    unsigned int __x = (_x); \
86    asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \
87  } while (0)
88
89/*
90 *  Manipulate interrupt mask
91 *
92 *  mips_unmask_interrupt( _mask)
93 *    enables interrupts - mask is positioned so it only needs to be or'ed
94 *    into the status reg. This also does some other things !!!! Caution
95 *    should be used if invoking this while in the middle of a debugging
96 *    session where the client may have nested interrupts.
97 *
98 *  mips_mask_interrupt( _mask )
99 *    disable the interrupt - mask is the complement of the bits to be
100 *    cleared - i.e. to clear ext int 5 the mask would be - 0xffff7fff
101 *
102 *
103 *  NOTE: mips_mask_interrupt() used to be disable_int().
104 *        mips_unmask_interrupt() used to be enable_int().
105 *
106 */
107
108#define mips_enable_in_interrupt_mask( _mask ) \
109  do { \
110    unsigned int _sr; \
111    mips_get_sr( _sr ); \
112    _sr |= (_mask); \
113    mips_set_sr( _sr ); \
114  } while (0)
115
116#define mips_disable_in_interrupt_mask( _mask ) \
117  do { \
118    unsigned int _sr; \
119    mips_get_sr( _sr ); \
120    _sr &= ~(_mask); \
121    mips_set_sr( _sr ); \
122  } while (0)
123
124#ifdef __cplusplus
125}
126#endif
127
128#endif /* ! _INCLUDE_MIPS_h */
129/* end of include file */
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