source: rtems/cpukit/score/cpu/mips/rtems/score/cpu.h @ e2040ba

4.104.114.84.95
Last change on this file since e2040ba was e2040ba, checked in by Joel Sherrill <joel.sherrill@…>, on May 22, 2001 at 10:59:42 PM

2001-05-22 Greg Menke <gregory.menke@…>

  • rtems/score/cpu.h: Add the interrupt stack structure and enhance the context initialization to account for floating point tasks.
  • rtems/score/mips.h: Added the routines mips_set_cause(), mips_get_fcr31(), and mips_set_fcr31().
  • Assisted in design and debug by Joel Sherrill <joel@…>.
  • Property mode set to 100644
File size: 33.1 KB
Line 
1/*
2 *  Mips CPU Dependent Header File
3 *
4 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
5 *           Joel Sherrill <joel@OARcorp.com>.
6 *
7 *    These changes made the code conditional on standard cpp predefines,
8 *    merged the mips1 and mips3 code sequences as much as possible,
9 *    and moved some of the assembly code to C.  Alan did much of the
10 *    initial analysis and rework.  Joel took over from there and
11 *    wrote the JMR3904 BSP so this could be tested.  Joel also
12 *    added the new interrupt vectoring support in libcpu and
13 *    tried to better support the various interrupt controllers.
14 *
15 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
16 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
17 *
18 *    To anyone who acknowledges that this file is provided "AS IS"
19 *    without any express or implied warranty:
20 *      permission to use, copy, modify, and distribute this file
21 *      for any purpose is hereby granted without fee, provided that
22 *      the above copyright notice and this notice appears in all
23 *      copies, and that the name of Transition Networks not be used in
24 *      advertising or publicity pertaining to distribution of the
25 *      software without specific, written prior permission.
26 *      Transition Networks makes no representations about the suitability
27 *      of this software for any purpose.
28 *
29 *  COPYRIGHT (c) 1989-2001.
30 *  On-Line Applications Research Corporation (OAR).
31 *
32 *  The license and distribution terms for this file may be
33 *  found in the file LICENSE in this distribution or at
34 *  http://www.OARcorp.com/rtems/license.html.
35 *
36 *  $Id$
37 */
38
39#ifndef __CPU_h
40#define __CPU_h
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
46#include <rtems/score/mips.h>       /* pick up machine definitions */
47#ifndef ASM
48#include <rtems/score/mipstypes.h>
49#endif
50
51/* conditional compilation parameters */
52
53/*
54 *  Should the calls to _Thread_Enable_dispatch be inlined?
55 *
56 *  If TRUE, then they are inlined.
57 *  If FALSE, then a subroutine call is made.
58 *
59 *  Basically this is an example of the classic trade-off of size
60 *  versus speed.  Inlining the call (TRUE) typically increases the
61 *  size of RTEMS while speeding up the enabling of dispatching.
62 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
63 *  only be 0 or 1 unless you are in an interrupt handler and that
64 *  interrupt handler invokes the executive.]  When not inlined
65 *  something calls _Thread_Enable_dispatch which in turns calls
66 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
67 *  one subroutine call is avoided entirely.]
68 */
69
70#define CPU_INLINE_ENABLE_DISPATCH       TRUE
71
72/*
73 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
74 *  be unrolled one time?  In unrolled each iteration of the loop examines
75 *  two "nodes" on the chain being searched.  Otherwise, only one node
76 *  is examined per iteration.
77 *
78 *  If TRUE, then the loops are unrolled.
79 *  If FALSE, then the loops are not unrolled.
80 *
81 *  The primary factor in making this decision is the cost of disabling
82 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
83 *  body of the loop.  On some CPUs, the flash is more expensive than
84 *  one iteration of the loop body.  In this case, it might be desirable
85 *  to unroll the loop.  It is important to note that on some CPUs, this
86 *  code is the longest interrupt disable period in RTEMS.  So it is
87 *  necessary to strike a balance when setting this parameter.
88 */
89
90#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
91
92/*
93 *  Does RTEMS manage a dedicated interrupt stack in software?
94 *
95 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
96 *  If FALSE, nothing is done.
97 *
98 *  If the CPU supports a dedicated interrupt stack in hardware,
99 *  then it is generally the responsibility of the BSP to allocate it
100 *  and set it up.
101 *
102 *  If the CPU does not support a dedicated interrupt stack, then
103 *  the porter has two options: (1) execute interrupts on the
104 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
105 *  interrupt stack.
106 *
107 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
108 *
109 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
110 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
111 *  possible that both are FALSE for a particular CPU.  Although it
112 *  is unclear what that would imply about the interrupt processing
113 *  procedure on that CPU.
114 */
115
116#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
117
118/*
119 *  Does this CPU have hardware support for a dedicated interrupt stack?
120 *
121 *  If TRUE, then it must be installed during initialization.
122 *  If FALSE, then no installation is performed.
123 *
124 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
125 *
126 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
127 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
128 *  possible that both are FALSE for a particular CPU.  Although it
129 *  is unclear what that would imply about the interrupt processing
130 *  procedure on that CPU.
131 */
132
133#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
134
135/*
136 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
137 *
138 *  If TRUE, then the memory is allocated during initialization.
139 *  If FALSE, then the memory is allocated during initialization.
140 *
141 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
142 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
143 */
144
145#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
146
147/*
148 *  Does the RTEMS invoke the user's ISR with the vector number and
149 *  a pointer to the saved interrupt frame (1) or just the vector
150 *  number (0)?
151 *
152 */
153
154#define CPU_ISR_PASSES_FRAME_POINTER 1
155
156
157
158/*
159 *  Does the CPU have hardware floating point?
160 *
161 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
162 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
163 *
164 *  If there is a FP coprocessor such as the i387 or mc68881, then
165 *  the answer is TRUE.
166 *
167 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
168 *  It indicates whether or not this CPU model has FP support.  For
169 *  example, it would be possible to have an i386_nofp CPU model
170 *  which set this to false to indicate that you have an i386 without
171 *  an i387 and wish to leave floating point support out of RTEMS.
172 */
173
174#if ( MIPS_HAS_FPU == 1 )
175#define CPU_HARDWARE_FP     TRUE
176#else
177#define CPU_HARDWARE_FP     FALSE
178#endif
179
180/*
181 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
182 *
183 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
184 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
185 *
186 *  So far, the only CPU in which this option has been used is the
187 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
188 *  floating point registers to perform integer multiplies.  If
189 *  a function which you would not think utilize the FP unit DOES,
190 *  then one can not easily predict which tasks will use the FP hardware.
191 *  In this case, this option should be TRUE.
192 *
193 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
194 */
195
196#define CPU_ALL_TASKS_ARE_FP    FALSE
197
198/*
199 *  Should the IDLE task have a floating point context?
200 *
201 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
202 *  and it has a floating point context which is switched in and out.
203 *  If FALSE, then the IDLE task does not have a floating point context.
204 *
205 *  Setting this to TRUE negatively impacts the time required to preempt
206 *  the IDLE task from an interrupt because the floating point context
207 *  must be saved as part of the preemption.
208 */
209
210#define CPU_IDLE_TASK_IS_FP      FALSE
211
212/*
213 *  Should the saving of the floating point registers be deferred
214 *  until a context switch is made to another different floating point
215 *  task?
216 *
217 *  If TRUE, then the floating point context will not be stored until
218 *  necessary.  It will remain in the floating point registers and not
219 *  disturned until another floating point task is switched to.
220 *
221 *  If FALSE, then the floating point context is saved when a floating
222 *  point task is switched out and restored when the next floating point
223 *  task is restored.  The state of the floating point registers between
224 *  those two operations is not specified.
225 *
226 *  If the floating point context does NOT have to be saved as part of
227 *  interrupt dispatching, then it should be safe to set this to TRUE.
228 *
229 *  Setting this flag to TRUE results in using a different algorithm
230 *  for deciding when to save and restore the floating point context.
231 *  The deferred FP switch algorithm minimizes the number of times
232 *  the FP context is saved and restored.  The FP context is not saved
233 *  until a context switch is made to another, different FP task.
234 *  Thus in a system with only one FP task, the FP context will never
235 *  be saved or restored.
236 */
237
238#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
239
240/*
241 *  Does this port provide a CPU dependent IDLE task implementation?
242 *
243 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
244 *  must be provided and is the default IDLE thread body instead of
245 *  _Internal_threads_Idle_thread_body.
246 *
247 *  If FALSE, then use the generic IDLE thread body if the BSP does
248 *  not provide one.
249 *
250 *  This is intended to allow for supporting processors which have
251 *  a low power or idle mode.  When the IDLE thread is executed, then
252 *  the CPU can be powered down.
253 *
254 *  The order of precedence for selecting the IDLE thread body is:
255 *
256 *    1.  BSP provided
257 *    2.  CPU dependent (if provided)
258 *    3.  generic (if no BSP and no CPU dependent)
259 */
260
261/* we can use the low power wait instruction for the IDLE thread */
262#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
263
264/*
265 *  Does the stack grow up (toward higher addresses) or down
266 *  (toward lower addresses)?
267 *
268 *  If TRUE, then the grows upward.
269 *  If FALSE, then the grows toward smaller addresses.
270 */
271
272/* our stack grows down */
273#define CPU_STACK_GROWS_UP               FALSE
274
275/*
276 *  The following is the variable attribute used to force alignment
277 *  of critical RTEMS structures.  On some processors it may make
278 *  sense to have these aligned on tighter boundaries than
279 *  the minimum requirements of the compiler in order to have as
280 *  much of the critical data area as possible in a cache line.
281 *
282 *  The placement of this macro in the declaration of the variables
283 *  is based on the syntactically requirements of the GNU C
284 *  "__attribute__" extension.  For example with GNU C, use
285 *  the following to force a structures to a 32 byte boundary.
286 *
287 *      __attribute__ ((aligned (32)))
288 *
289 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
290 *         To benefit from using this, the data must be heavily
291 *         used so it will stay in the cache and used frequently enough
292 *         in the executive to justify turning this on.
293 */
294
295/* our cache line size is 16 bytes */
296#if __GNUC__
297#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
298#else
299#define CPU_STRUCTURE_ALIGNMENT
300#endif
301
302/*
303 *  Define what is required to specify how the network to host conversion
304 *  routines are handled.
305 */
306
307#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
308#define CPU_BIG_ENDIAN                           TRUE
309#define CPU_LITTLE_ENDIAN                        FALSE
310
311/*
312 *  The following defines the number of bits actually used in the
313 *  interrupt field of the task mode.  How those bits map to the
314 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
315 */
316
317#define CPU_MODES_INTERRUPT_MASK   0x00000001
318
319/*
320 *  Processor defined structures
321 *
322 *  Examples structures include the descriptor tables from the i386
323 *  and the processor control structure on the i960ca.
324 */
325
326/* may need to put some structures here.  */
327
328/*
329 * Contexts
330 *
331 *  Generally there are 2 types of context to save.
332 *     1. Interrupt registers to save
333 *     2. Task level registers to save
334 *
335 *  This means we have the following 3 context items:
336 *     1. task level context stuff::  Context_Control
337 *     2. floating point task stuff:: Context_Control_fp
338 *     3. special interrupt level context :: Context_Control_interrupt
339 *
340 *  On some processors, it is cost-effective to save only the callee
341 *  preserved registers during a task context switch.  This means
342 *  that the ISR code needs to save those registers which do not
343 *  persist across function calls.  It is not mandatory to make this
344 *  distinctions between the caller/callee saves registers for the
345 *  purpose of minimizing context saved during task switch and on interrupts.
346 *  If the cost of saving extra registers is minimal, simplicity is the
347 *  choice.  Save the same context on interrupt entry as for tasks in
348 *  this case.
349 *
350 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
351 *  care should be used in designing the context area.
352 *
353 *  On some CPUs with hardware floating point support, the Context_Control_fp
354 *  structure will not be used or it simply consist of an array of a
355 *  fixed number of bytes.   This is done when the floating point context
356 *  is dumped by a "FP save context" type instruction and the format
357 *  is not really defined by the CPU.  In this case, there is no need
358 *  to figure out the exact format -- only the size.  Of course, although
359 *  this is enough information for RTEMS, it is probably not enough for
360 *  a debugger such as gdb.  But that is another problem.
361 */
362
363/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
364#if __mips == 1
365#define __MIPS_REGISTER_TYPE     unsigned32
366#define __MIPS_FPU_REGISTER_TYPE unsigned32
367#elif __mips == 3
368#define __MIPS_REGISTER_TYPE     unsigned64
369#define __MIPS_FPU_REGISTER_TYPE unsigned64
370#else
371#error "mips register size: unknown architecture level!!"
372#endif
373typedef struct {
374    __MIPS_REGISTER_TYPE s0;
375    __MIPS_REGISTER_TYPE s1;
376    __MIPS_REGISTER_TYPE s2;
377    __MIPS_REGISTER_TYPE s3;
378    __MIPS_REGISTER_TYPE s4;
379    __MIPS_REGISTER_TYPE s5;
380    __MIPS_REGISTER_TYPE s6;
381    __MIPS_REGISTER_TYPE s7;
382    __MIPS_REGISTER_TYPE sp;
383    __MIPS_REGISTER_TYPE fp;
384    __MIPS_REGISTER_TYPE ra;
385    __MIPS_REGISTER_TYPE c0_sr;
386/*    __MIPS_REGISTER_TYPE c0_epc; */
387} Context_Control;
388
389/* WARNING: If this structure is modified, the constants in cpu.h
390 *          must also be updated.
391 */
392
393typedef struct {
394#if ( CPU_HARDWARE_FP == TRUE )
395    __MIPS_FPU_REGISTER_TYPE fp0;
396    __MIPS_FPU_REGISTER_TYPE fp1;
397    __MIPS_FPU_REGISTER_TYPE fp2;
398    __MIPS_FPU_REGISTER_TYPE fp3;
399    __MIPS_FPU_REGISTER_TYPE fp4;
400    __MIPS_FPU_REGISTER_TYPE fp5;
401    __MIPS_FPU_REGISTER_TYPE fp6;
402    __MIPS_FPU_REGISTER_TYPE fp7;
403    __MIPS_FPU_REGISTER_TYPE fp8;
404    __MIPS_FPU_REGISTER_TYPE fp9;
405    __MIPS_FPU_REGISTER_TYPE fp10;
406    __MIPS_FPU_REGISTER_TYPE fp11;
407    __MIPS_FPU_REGISTER_TYPE fp12;
408    __MIPS_FPU_REGISTER_TYPE fp13;
409    __MIPS_FPU_REGISTER_TYPE fp14;
410    __MIPS_FPU_REGISTER_TYPE fp15;
411    __MIPS_FPU_REGISTER_TYPE fp16;
412    __MIPS_FPU_REGISTER_TYPE fp17;
413    __MIPS_FPU_REGISTER_TYPE fp18;
414    __MIPS_FPU_REGISTER_TYPE fp19;
415    __MIPS_FPU_REGISTER_TYPE fp20;
416    __MIPS_FPU_REGISTER_TYPE fp21;
417    __MIPS_FPU_REGISTER_TYPE fp22;
418    __MIPS_FPU_REGISTER_TYPE fp23;
419    __MIPS_FPU_REGISTER_TYPE fp24;
420    __MIPS_FPU_REGISTER_TYPE fp25;
421    __MIPS_FPU_REGISTER_TYPE fp26;
422    __MIPS_FPU_REGISTER_TYPE fp27;
423    __MIPS_FPU_REGISTER_TYPE fp28;
424    __MIPS_FPU_REGISTER_TYPE fp29;
425    __MIPS_FPU_REGISTER_TYPE fp30;
426    __MIPS_FPU_REGISTER_TYPE fp31;
427#endif
428} Context_Control_fp;
429
430
431
432
433
434/*
435 This struct reflects the stack frame employed in ISR_Handler.  Note
436 that the ISR routine doesn't save all registers to this frame, so
437 cpu_asm.S should be consulted to see if the registers you're
438 interested in are actually there.
439*/
440
441typedef struct
442{
443#if __mips == 1
444      unsigned int regs[80];
445#endif
446#if  __mips == 3
447      unsigned int regs[94];
448#endif
449} CPU_Interrupt_frame;
450
451
452/*
453 *  The following table contains the information required to configure
454 *  the mips processor specific parameters.
455 */
456
457typedef struct {
458  void       (*pretasking_hook)( void );
459  void       (*predriver_hook)( void );
460  void       (*postdriver_hook)( void );
461  void       (*idle_task)( void );
462  boolean      do_zero_of_workspace;
463  unsigned32   idle_task_stack_size;
464  unsigned32   interrupt_stack_size;
465  unsigned32   extra_mpci_receive_server_stack;
466  void *     (*stack_allocate_hook)( unsigned32 );
467  void       (*stack_free_hook)( void* );
468  /* end of fields required on all CPUs */
469
470  unsigned32   clicks_per_microsecond;
471}   rtems_cpu_table;
472
473/*
474 *  Macros to access required entires in the CPU Table are in
475 *  the file rtems/system.h.
476 */
477
478/*
479 *  Macros to access MIPS specific additions to the CPU Table
480 */
481
482#define rtems_cpu_configuration_get_clicks_per_microsecond() \
483   (_CPU_Table.clicks_per_microsecond)
484
485/*
486 *  This variable is optional.  It is used on CPUs on which it is difficult
487 *  to generate an "uninitialized" FP context.  It is filled in by
488 *  _CPU_Initialize and copied into the task's FP context area during
489 *  _CPU_Context_Initialize.
490 */
491
492SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
493
494/*
495 *  On some CPUs, RTEMS supports a software managed interrupt stack.
496 *  This stack is allocated by the Interrupt Manager and the switch
497 *  is performed in _ISR_Handler.  These variables contain pointers
498 *  to the lowest and highest addresses in the chunk of memory allocated
499 *  for the interrupt stack.  Since it is unknown whether the stack
500 *  grows up or down (in general), this give the CPU dependent
501 *  code the option of picking the version it wants to use.
502 *
503 *  NOTE: These two variables are required if the macro
504 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
505 */
506
507SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
508SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
509
510/*
511 *  With some compilation systems, it is difficult if not impossible to
512 *  call a high-level language routine from assembly language.  This
513 *  is especially true of commercial Ada compilers and name mangling
514 *  C++ ones.  This variable can be optionally defined by the CPU porter
515 *  and contains the address of the routine _Thread_Dispatch.  This
516 *  can make it easier to invoke that routine at the end of the interrupt
517 *  sequence (if a dispatch is necessary).
518 *
519
520SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
521 *
522 *  NOTE: Not needed on this port.
523 */
524
525/*
526 *  Nothing prevents the porter from declaring more CPU specific variables.
527 */
528
529/* XXX: if needed, put more variables here */
530
531/*
532 *  The size of the floating point context area.  On some CPUs this
533 *  will not be a "sizeof" because the format of the floating point
534 *  area is not defined -- only the size is.  This is usually on
535 *  CPUs with a "floating point save context" instruction.
536 */
537
538#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
539
540/*
541 *  Amount of extra stack (above minimum stack size) required by
542 *  system initialization thread.  Remember that in a multiprocessor
543 *  system the system intialization thread becomes the MP server thread.
544 */
545
546#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
547
548/*
549 *  This defines the number of entries in the ISR_Vector_table managed
550 *  by RTEMS.
551 */
552
553extern unsigned int mips_interrupt_number_of_vectors;
554#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (mips_interrupt_number_of_vectors)
555#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
556
557/*
558 *  Should be large enough to run all RTEMS tests.  This insures
559 *  that a "reasonable" small application should not have any problems.
560 */
561
562#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(unsigned32))
563
564/*
565 *  CPU's worst alignment requirement for data types on a byte boundary.  This
566 *  alignment does not take into account the requirements for the stack.
567 */
568
569#define CPU_ALIGNMENT              8
570
571/*
572 *  This number corresponds to the byte alignment requirement for the
573 *  heap handler.  This alignment requirement may be stricter than that
574 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
575 *  common for the heap to follow the same alignment requirement as
576 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
577 *  then this should be set to CPU_ALIGNMENT.
578 *
579 *  NOTE:  This does not have to be a power of 2.  It does have to
580 *         be greater or equal to than CPU_ALIGNMENT.
581 */
582
583#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
584
585/*
586 *  This number corresponds to the byte alignment requirement for memory
587 *  buffers allocated by the partition manager.  This alignment requirement
588 *  may be stricter than that for the data types alignment specified by
589 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
590 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
591 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
592 *
593 *  NOTE:  This does not have to be a power of 2.  It does have to
594 *         be greater or equal to than CPU_ALIGNMENT.
595 */
596
597#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
598
599/*
600 *  This number corresponds to the byte alignment requirement for the
601 *  stack.  This alignment requirement may be stricter than that for the
602 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
603 *  is strict enough for the stack, then this should be set to 0.
604 *
605 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
606 */
607
608#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
609
610/*
611 *  ISR handler macros
612 */
613
614/*
615 *  Support routine to initialize the RTEMS vector table after it is allocated.
616 */
617
618#define _CPU_Initialize_vectors()
619
620/*
621 *  Disable all interrupts for an RTEMS critical section.  The previous
622 *  level is returned in _level.
623 */
624
625#define _CPU_ISR_Disable( _level ) \
626  do { \
627    mips_get_sr( _level ); \
628    mips_set_sr( (_level) & ~SR_INTERRUPT_ENABLE_BITS ); \
629  } while(0)
630
631/*
632 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
633 *  This indicates the end of an RTEMS critical section.  The parameter
634 *  _level is not modified.
635 */
636
637#define _CPU_ISR_Enable( _level )  \
638  do { \
639    mips_set_sr(_level); \
640  } while(0)
641
642/*
643 *  This temporarily restores the interrupt to _level before immediately
644 *  disabling them again.  This is used to divide long RTEMS critical
645 *  sections into two or more parts.  The parameter _level is not
646 * modified.
647 */
648
649#define _CPU_ISR_Flash( _xlevel ) \
650  do { \
651    unsigned int _scratch; \
652    _CPU_ISR_Enable( _xlevel ); \
653    _CPU_ISR_Disable( _scratch ); \
654  } while(0)
655
656/*
657 *  Map interrupt level in task mode onto the hardware that the CPU
658 *  actually provides.  Currently, interrupt levels which do not
659 *  map onto the CPU in a generic fashion are undefined.  Someday,
660 *  it would be nice if these were "mapped" by the application
661 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
662 *  8 - 255 would be available for bsp/application specific meaning.
663 *  This could be used to manage a programmable interrupt controller
664 *  via the rtems_task_mode directive.
665 *
666 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
667 *  manipulates the IEC.
668 */
669
670unsigned32 _CPU_ISR_Get_level( void );  /* in cpu.c */
671
672void _CPU_ISR_Set_level( unsigned32 );  /* in cpu.c */
673
674/* end of ISR handler macros */
675
676/* Context handler macros */
677
678/*
679 *  Initialize the context to a state suitable for starting a
680 *  task after a context restore operation.  Generally, this
681 *  involves:
682 *
683 *     - setting a starting address
684 *     - preparing the stack
685 *     - preparing the stack and frame pointers
686 *     - setting the proper interrupt level in the context
687 *     - initializing the floating point context
688 *
689 *  This routine generally does not set any unnecessary register
690 *  in the context.  The state of the "general data" registers is
691 *  undefined at task start time.
692 *
693 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
694 *        point thread.  This is typically only used on CPUs where the
695 *        FPU may be easily disabled by software such as on the SPARC
696 *        where the PSR contains an enable FPU bit.
697 */
698
699#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
700                                 _isr, _entry_point, _is_fp ) \
701  { \
702        unsigned32 _stack_tmp = \
703           (unsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
704        _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
705        (_the_context)->sp = _stack_tmp; \
706        (_the_context)->fp = _stack_tmp; \
707        (_the_context)->ra = (unsigned64)_entry_point; \
708        (_the_context)->c0_sr = ((_the_context)->c0_sr & 0x0fff0000) | \
709                                ((_isr)?0xff00:0xff01) | \
710                                ((_is_fp)?0x20000000:0x10000000); \
711  }
712
713/*
714 *  This routine is responsible for somehow restarting the currently
715 *  executing task.  If you are lucky, then all that is necessary
716 *  is restoring the context.  Otherwise, there will need to be
717 *  a special assembly routine which does something special in this
718 *  case.  Context_Restore should work most of the time.  It will
719 *  not work if restarting self conflicts with the stack frame
720 *  assumptions of restoring a context.
721 */
722
723#define _CPU_Context_Restart_self( _the_context ) \
724   _CPU_Context_restore( (_the_context) );
725
726/*
727 *  The purpose of this macro is to allow the initial pointer into
728 *  A floating point context area (used to save the floating point
729 *  context) to be at an arbitrary place in the floating point
730 *  context area.
731 *
732 *  This is necessary because some FP units are designed to have
733 *  their context saved as a stack which grows into lower addresses.
734 *  Other FP units can be saved by simply moving registers into offsets
735 *  from the base of the context area.  Finally some FP units provide
736 *  a "dump context" instruction which could fill in from high to low
737 *  or low to high based on the whim of the CPU designers.
738 */
739
740#define _CPU_Context_Fp_start( _base, _offset ) \
741   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
742
743/*
744 *  This routine initializes the FP context area passed to it to.
745 *  There are a few standard ways in which to initialize the
746 *  floating point context.  The code included for this macro assumes
747 *  that this is a CPU in which a "initial" FP context was saved into
748 *  _CPU_Null_fp_context and it simply copies it to the destination
749 *  context passed to it.
750 *
751 *  Other models include (1) not doing anything, and (2) putting
752 *  a "null FP status word" in the correct place in the FP context.
753 */
754
755#if ( CPU_HARDWARE_FP == TRUE )
756#define _CPU_Context_Initialize_fp( _destination ) \
757  { \
758   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
759  }
760#endif
761
762/* end of Context handler macros */
763
764/* Fatal Error manager macros */
765
766/*
767 *  This routine copies _error into a known place -- typically a stack
768 *  location or a register, optionally disables interrupts, and
769 *  halts/stops the CPU.
770 */
771
772#define _CPU_Fatal_halt( _error ) \
773  do { \
774    unsigned int _level; \
775    _CPU_ISR_Disable(_level); \
776    loop: goto loop; \
777  } while (0)
778
779
780extern void mips_break( int error );
781
782/* Bitfield handler macros */
783
784/*
785 *  This routine sets _output to the bit number of the first bit
786 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
787 *  This type may be either 16 or 32 bits wide although only the 16
788 *  least significant bits will be used.
789 *
790 *  There are a number of variables in using a "find first bit" type
791 *  instruction.
792 *
793 *    (1) What happens when run on a value of zero?
794 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
795 *    (3) The numbering may be zero or one based.
796 *    (4) The "find first bit" instruction may search from MSB or LSB.
797 *
798 *  RTEMS guarantees that (1) will never happen so it is not a concern.
799 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
800 *  _CPU_Priority_bits_index().  These three form a set of routines
801 *  which must logically operate together.  Bits in the _value are
802 *  set and cleared based on masks built by _CPU_Priority_mask().
803 *  The basic major and minor values calculated by _Priority_Major()
804 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
805 *  to properly range between the values returned by the "find first bit"
806 *  instruction.  This makes it possible for _Priority_Get_highest() to
807 *  calculate the major and directly index into the minor table.
808 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
809 *  is the first bit found.
810 *
811 *  This entire "find first bit" and mapping process depends heavily
812 *  on the manner in which a priority is broken into a major and minor
813 *  components with the major being the 4 MSB of a priority and minor
814 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
815 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
816 *  to the lowest priority.
817 *
818 *  If your CPU does not have a "find first bit" instruction, then
819 *  there are ways to make do without it.  Here are a handful of ways
820 *  to implement this in software:
821 *
822 *    - a series of 16 bit test instructions
823 *    - a "binary search using if's"
824 *    - _number = 0
825 *      if _value > 0x00ff
826 *        _value >>=8
827 *        _number = 8;
828 *
829 *      if _value > 0x0000f
830 *        _value >=8
831 *        _number += 4
832 *
833 *      _number += bit_set_table[ _value ]
834 *
835 *    where bit_set_table[ 16 ] has values which indicate the first
836 *      bit set
837 */
838
839#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
840#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
841
842#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
843
844#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
845  { \
846    (_output) = 0;   /* do something to prevent warnings */ \
847  }
848
849#endif
850
851/* end of Bitfield handler macros */
852
853/*
854 *  This routine builds the mask which corresponds to the bit fields
855 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
856 *  for that routine.
857 */
858
859#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
860
861#define _CPU_Priority_Mask( _bit_number ) \
862  ( 1 << (_bit_number) )
863
864#endif
865
866/*
867 *  This routine translates the bit numbers returned by
868 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
869 *  a major or minor component of a priority.  See the discussion
870 *  for that routine.
871 */
872
873#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
874
875#define _CPU_Priority_bits_index( _priority ) \
876  (_priority)
877
878#endif
879
880/* end of Priority handler macros */
881
882/* functions */
883
884/*
885 *  _CPU_Initialize
886 *
887 *  This routine performs CPU dependent initialization.
888 */
889
890void _CPU_Initialize(
891  rtems_cpu_table  *cpu_table,
892  void      (*thread_dispatch)
893);
894
895/*
896 *  _CPU_ISR_install_raw_handler
897 *
898 *  This routine installs a "raw" interrupt handler directly into the
899 *  processor's vector table.
900 */
901
902void _CPU_ISR_install_raw_handler(
903  unsigned32  vector,
904  proc_ptr    new_handler,
905  proc_ptr   *old_handler
906);
907
908/*
909 *  _CPU_ISR_install_vector
910 *
911 *  This routine installs an interrupt vector.
912 */
913
914void _CPU_ISR_install_vector(
915  unsigned32  vector,
916  proc_ptr    new_handler,
917  proc_ptr   *old_handler
918);
919
920/*
921 *  _CPU_Install_interrupt_stack
922 *
923 *  This routine installs the hardware interrupt stack pointer.
924 *
925 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
926 *         is TRUE.
927 */
928
929void _CPU_Install_interrupt_stack( void );
930
931/*
932 *  _CPU_Internal_threads_Idle_thread_body
933 *
934 *  This routine is the CPU dependent IDLE thread body.
935 *
936 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
937 *         is TRUE.
938 */
939
940void _CPU_Thread_Idle_body( void );
941
942/*
943 *  _CPU_Context_switch
944 *
945 *  This routine switches from the run context to the heir context.
946 */
947
948void _CPU_Context_switch(
949  Context_Control  *run,
950  Context_Control  *heir
951);
952
953/*
954 *  _CPU_Context_restore
955 *
956 *  This routine is generally used only to restart self in an
957 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
958 *
959 *  NOTE: May be unnecessary to reload some registers.
960 */
961
962void _CPU_Context_restore(
963  Context_Control *new_context
964);
965
966/*
967 *  _CPU_Context_save_fp
968 *
969 *  This routine saves the floating point context passed to it.
970 */
971
972void _CPU_Context_save_fp(
973  void **fp_context_ptr
974);
975
976/*
977 *  _CPU_Context_restore_fp
978 *
979 *  This routine restores the floating point context passed to it.
980 */
981
982void _CPU_Context_restore_fp(
983  void **fp_context_ptr
984);
985
986/*  The following routine swaps the endian format of an unsigned int.
987 *  It must be static because it is referenced indirectly.
988 *
989 *  This version will work on any processor, but if there is a better
990 *  way for your CPU PLEASE use it.  The most common way to do this is to:
991 *
992 *     swap least significant two bytes with 16-bit rotate
993 *     swap upper and lower 16-bits
994 *     swap most significant two bytes with 16-bit rotate
995 *
996 *  Some CPUs have special instructions which swap a 32-bit quantity in
997 *  a single instruction (e.g. i486).  It is probably best to avoid
998 *  an "endian swapping control bit" in the CPU.  One good reason is
999 *  that interrupts would probably have to be disabled to insure that
1000 *  an interrupt does not try to access the same "chunk" with the wrong
1001 *  endian.  Another good reason is that on some CPUs, the endian bit
1002 *  endianness for ALL fetches -- both code and data -- so the code
1003 *  will be fetched incorrectly.
1004 */
1005
1006static inline unsigned int CPU_swap_u32(
1007  unsigned int value
1008)
1009{
1010  unsigned32 byte1, byte2, byte3, byte4, swapped;
1011
1012  byte4 = (value >> 24) & 0xff;
1013  byte3 = (value >> 16) & 0xff;
1014  byte2 = (value >> 8)  & 0xff;
1015  byte1 =  value        & 0xff;
1016
1017  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1018  return( swapped );
1019}
1020
1021#define CPU_swap_u16( value ) \
1022  (((value&0xff) << 8) | ((value >> 8)&0xff))
1023
1024#ifdef __cplusplus
1025}
1026#endif
1027
1028#endif
Note: See TracBrowser for help on using the repository browser.