source: rtems/cpukit/score/cpu/mips/rtems/score/cpu.h @ 9b4422a2

4.11
Last change on this file since 9b4422a2 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on May 3, 2012 at 3:09:24 PM

Remove All CVS Id Strings Possible Using a Script

Script does what is expected and tries to do it as
smartly as possible.

+ remove occurrences of two blank comment lines

next to each other after Id string line removed.

+ remove entire comment blocks which only exited to

contain CVS Ids

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1/**
2 *  @file
3 * 
4 *  Mips CPU Dependent Header File
5 *
6 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
7 *           Joel Sherrill <joel@OARcorp.com>.
8 *
9 *    These changes made the code conditional on standard cpp predefines,
10 *    merged the mips1 and mips3 code sequences as much as possible,
11 *    and moved some of the assembly code to C.  Alan did much of the
12 *    initial analysis and rework.  Joel took over from there and
13 *    wrote the JMR3904 BSP so this could be tested.  Joel also
14 *    added the new interrupt vectoring support in libcpu and
15 *    tried to better support the various interrupt controllers.
16 *
17 */
18
19/*
20 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
21 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
22 *
23 *    To anyone who acknowledges that this file is provided "AS IS"
24 *    without any express or implied warranty:
25 *      permission to use, copy, modify, and distribute this file
26 *      for any purpose is hereby granted without fee, provided that
27 *      the above copyright notice and this notice appears in all
28 *      copies, and that the name of Transition Networks not be used in
29 *      advertising or publicity pertaining to distribution of the
30 *      software without specific, written prior permission.
31 *      Transition Networks makes no representations about the suitability
32 *      of this software for any purpose.
33 *
34 *  COPYRIGHT (c) 1989-2012.
35 *  On-Line Applications Research Corporation (OAR).
36 *
37 *  The license and distribution terms for this file may be
38 *  found in the file LICENSE in this distribution or at
39 *  http://www.rtems.com/license/LICENSE.
40 */
41
42#ifndef _RTEMS_SCORE_CPU_H
43#define _RTEMS_SCORE_CPU_H
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49#include <rtems/score/types.h>
50#include <rtems/score/mips.h>
51
52/* conditional compilation parameters */
53
54/*
55 *  Should the calls to _Thread_Enable_dispatch be inlined?
56 *
57 *  If TRUE, then they are inlined.
58 *  If FALSE, then a subroutine call is made.
59 *
60 *  Basically this is an example of the classic trade-off of size
61 *  versus speed.  Inlining the call (TRUE) typically increases the
62 *  size of RTEMS while speeding up the enabling of dispatching.
63 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
64 *  only be 0 or 1 unless you are in an interrupt handler and that
65 *  interrupt handler invokes the executive.]  When not inlined
66 *  something calls _Thread_Enable_dispatch which in turns calls
67 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
68 *  one subroutine call is avoided entirely.]
69 */
70
71#define CPU_INLINE_ENABLE_DISPATCH       FALSE
72
73/*
74 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
75 *  be unrolled one time?  In unrolled each iteration of the loop examines
76 *  two "nodes" on the chain being searched.  Otherwise, only one node
77 *  is examined per iteration.
78 *
79 *  If TRUE, then the loops are unrolled.
80 *  If FALSE, then the loops are not unrolled.
81 *
82 *  The primary factor in making this decision is the cost of disabling
83 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
84 *  body of the loop.  On some CPUs, the flash is more expensive than
85 *  one iteration of the loop body.  In this case, it might be desirable
86 *  to unroll the loop.  It is important to note that on some CPUs, this
87 *  code is the longest interrupt disable period in RTEMS.  So it is
88 *  necessary to strike a balance when setting this parameter.
89 */
90
91#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
92
93/*
94 *  Does RTEMS manage a dedicated interrupt stack in software?
95 *
96 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
97 *  If FALSE, nothing is done.
98 *
99 *  If the CPU supports a dedicated interrupt stack in hardware,
100 *  then it is generally the responsibility of the BSP to allocate it
101 *  and set it up.
102 *
103 *  If the CPU does not support a dedicated interrupt stack, then
104 *  the porter has two options: (1) execute interrupts on the
105 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
106 *  interrupt stack.
107 *
108 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
109 *
110 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
111 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
112 *  possible that both are FALSE for a particular CPU.  Although it
113 *  is unclear what that would imply about the interrupt processing
114 *  procedure on that CPU.
115 */
116
117#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
118
119/*
120 *  Does the CPU follow the simple vectored interrupt model?
121 *
122 *  If TRUE, then RTEMS allocates the vector table it internally manages.
123 *  If FALSE, then the BSP is assumed to allocate and manage the vector
124 *  table
125 *
126 *  MIPS Specific Information:
127 *
128 *  XXX document implementation including references if appropriate
129 */
130#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
131
132/*
133 *  Does this CPU have hardware support for a dedicated interrupt stack?
134 *
135 *  If TRUE, then it must be installed during initialization.
136 *  If FALSE, then no installation is performed.
137 *
138 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
139 *
140 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
141 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
142 *  possible that both are FALSE for a particular CPU.  Although it
143 *  is unclear what that would imply about the interrupt processing
144 *  procedure on that CPU.
145 */
146
147#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
148
149/*
150 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
151 *
152 *  If TRUE, then the memory is allocated during initialization.
153 *  If FALSE, then the memory is allocated during initialization.
154 *
155 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
156 */
157
158#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
159
160/*
161 *  Does the RTEMS invoke the user's ISR with the vector number and
162 *  a pointer to the saved interrupt frame (1) or just the vector
163 *  number (0)?
164 *
165 */
166
167#define CPU_ISR_PASSES_FRAME_POINTER 1
168
169
170
171/*
172 *  Does the CPU have hardware floating point?
173 *
174 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
175 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
176 *
177 *  If there is a FP coprocessor such as the i387 or mc68881, then
178 *  the answer is TRUE.
179 *
180 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
181 *  It indicates whether or not this CPU model has FP support.  For
182 *  example, it would be possible to have an i386_nofp CPU model
183 *  which set this to false to indicate that you have an i386 without
184 *  an i387 and wish to leave floating point support out of RTEMS.
185 */
186
187#if ( MIPS_HAS_FPU == 1 )
188#define CPU_HARDWARE_FP     TRUE
189#else
190#define CPU_HARDWARE_FP     FALSE
191#endif
192
193/*
194 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
195 *
196 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
197 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
198 *
199 *  So far, the only CPU in which this option has been used is the
200 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
201 *  floating point registers to perform integer multiplies.  If
202 *  a function which you would not think utilize the FP unit DOES,
203 *  then one can not easily predict which tasks will use the FP hardware.
204 *  In this case, this option should be TRUE.
205 *
206 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
207 *
208 *  Mips Note: It appears the GCC can implicitly generate FPU
209 *  and Altivec instructions when you least expect them.  So make
210 *  all tasks floating point.
211 */
212
213#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
214
215/*
216 *  Should the IDLE task have a floating point context?
217 *
218 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
219 *  and it has a floating point context which is switched in and out.
220 *  If FALSE, then the IDLE task does not have a floating point context.
221 *
222 *  Setting this to TRUE negatively impacts the time required to preempt
223 *  the IDLE task from an interrupt because the floating point context
224 *  must be saved as part of the preemption.
225 */
226
227#define CPU_IDLE_TASK_IS_FP      FALSE
228
229/*
230 *  Should the saving of the floating point registers be deferred
231 *  until a context switch is made to another different floating point
232 *  task?
233 *
234 *  If TRUE, then the floating point context will not be stored until
235 *  necessary.  It will remain in the floating point registers and not
236 *  disturned until another floating point task is switched to.
237 *
238 *  If FALSE, then the floating point context is saved when a floating
239 *  point task is switched out and restored when the next floating point
240 *  task is restored.  The state of the floating point registers between
241 *  those two operations is not specified.
242 *
243 *  If the floating point context does NOT have to be saved as part of
244 *  interrupt dispatching, then it should be safe to set this to TRUE.
245 *
246 *  Setting this flag to TRUE results in using a different algorithm
247 *  for deciding when to save and restore the floating point context.
248 *  The deferred FP switch algorithm minimizes the number of times
249 *  the FP context is saved and restored.  The FP context is not saved
250 *  until a context switch is made to another, different FP task.
251 *  Thus in a system with only one FP task, the FP context will never
252 *  be saved or restored.
253 */
254
255#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
256
257/*
258 *  Does this port provide a CPU dependent IDLE task implementation?
259 *
260 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
261 *  must be provided and is the default IDLE thread body instead of
262 *  _Internal_threads_Idle_thread_body.
263 *
264 *  If FALSE, then use the generic IDLE thread body if the BSP does
265 *  not provide one.
266 *
267 *  This is intended to allow for supporting processors which have
268 *  a low power or idle mode.  When the IDLE thread is executed, then
269 *  the CPU can be powered down.
270 *
271 *  The order of precedence for selecting the IDLE thread body is:
272 *
273 *    1.  BSP provided
274 *    2.  CPU dependent (if provided)
275 *    3.  generic (if no BSP and no CPU dependent)
276 */
277
278/* we can use the low power wait instruction for the IDLE thread */
279#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
280
281/*
282 *  Does the stack grow up (toward higher addresses) or down
283 *  (toward lower addresses)?
284 *
285 *  If TRUE, then the grows upward.
286 *  If FALSE, then the grows toward smaller addresses.
287 */
288
289/* our stack grows down */
290#define CPU_STACK_GROWS_UP               FALSE
291
292/*
293 *  The following is the variable attribute used to force alignment
294 *  of critical RTEMS structures.  On some processors it may make
295 *  sense to have these aligned on tighter boundaries than
296 *  the minimum requirements of the compiler in order to have as
297 *  much of the critical data area as possible in a cache line.
298 *
299 *  The placement of this macro in the declaration of the variables
300 *  is based on the syntactically requirements of the GNU C
301 *  "__attribute__" extension.  For example with GNU C, use
302 *  the following to force a structures to a 32 byte boundary.
303 *
304 *      __attribute__ ((aligned (32)))
305 *
306 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
307 *         To benefit from using this, the data must be heavily
308 *         used so it will stay in the cache and used frequently enough
309 *         in the executive to justify turning this on.
310 */
311
312/* our cache line size is 16 bytes */
313#if __GNUC__
314#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
315#else
316#define CPU_STRUCTURE_ALIGNMENT
317#endif
318
319#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
320
321/*
322 *  Define what is required to specify how the network to host conversion
323 *  routines are handled.
324 */
325
326/* __MIPSEB__ or __MIPSEL__ is defined by GCC based on -EB or -EL command line options */
327#if defined(__MIPSEB__)
328#define CPU_BIG_ENDIAN                           TRUE
329#define CPU_LITTLE_ENDIAN                        FALSE
330#elif defined(__MIPSEL__)
331#define CPU_BIG_ENDIAN                           FALSE
332#define CPU_LITTLE_ENDIAN                        TRUE
333#else
334#error "Unknown endianness"
335#endif
336
337/*
338 *  The following defines the number of bits actually used in the
339 *  interrupt field of the task mode.  How those bits map to the
340 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
341 */
342
343#define CPU_MODES_INTERRUPT_MASK   0x000000ff
344
345/*
346 *  Processor defined structures
347 *
348 *  Examples structures include the descriptor tables from the i386
349 *  and the processor control structure on the i960ca.
350 */
351
352/* may need to put some structures here.  */
353
354/*
355 * Contexts
356 *
357 *  Generally there are 2 types of context to save.
358 *     1. Interrupt registers to save
359 *     2. Task level registers to save
360 *
361 *  This means we have the following 3 context items:
362 *     1. task level context stuff::  Context_Control
363 *     2. floating point task stuff:: Context_Control_fp
364 *     3. special interrupt level context :: Context_Control_interrupt
365 *
366 *  On some processors, it is cost-effective to save only the callee
367 *  preserved registers during a task context switch.  This means
368 *  that the ISR code needs to save those registers which do not
369 *  persist across function calls.  It is not mandatory to make this
370 *  distinctions between the caller/callee saves registers for the
371 *  purpose of minimizing context saved during task switch and on interrupts.
372 *  If the cost of saving extra registers is minimal, simplicity is the
373 *  choice.  Save the same context on interrupt entry as for tasks in
374 *  this case.
375 *
376 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
377 *  care should be used in designing the context area.
378 *
379 *  On some CPUs with hardware floating point support, the Context_Control_fp
380 *  structure will not be used or it simply consist of an array of a
381 *  fixed number of bytes.   This is done when the floating point context
382 *  is dumped by a "FP save context" type instruction and the format
383 *  is not really defined by the CPU.  In this case, there is no need
384 *  to figure out the exact format -- only the size.  Of course, although
385 *  this is enough information for RTEMS, it is probably not enough for
386 *  a debugger such as gdb.  But that is another problem.
387 */
388
389#ifndef ASM
390
391/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
392#if (__mips == 1) || (__mips == 32)
393#define __MIPS_REGISTER_TYPE     uint32_t
394#define __MIPS_FPU_REGISTER_TYPE uint32_t
395#elif __mips == 3
396#define __MIPS_REGISTER_TYPE     uint64_t
397#define __MIPS_FPU_REGISTER_TYPE uint64_t
398#else
399#error "mips register size: unknown architecture level!!"
400#endif
401typedef struct {
402    __MIPS_REGISTER_TYPE s0;
403    __MIPS_REGISTER_TYPE s1;
404    __MIPS_REGISTER_TYPE s2;
405    __MIPS_REGISTER_TYPE s3;
406    __MIPS_REGISTER_TYPE s4;
407    __MIPS_REGISTER_TYPE s5;
408    __MIPS_REGISTER_TYPE s6;
409    __MIPS_REGISTER_TYPE s7;
410    __MIPS_REGISTER_TYPE sp;
411    __MIPS_REGISTER_TYPE fp;
412    __MIPS_REGISTER_TYPE ra;
413    __MIPS_REGISTER_TYPE c0_sr;
414    __MIPS_REGISTER_TYPE c0_epc;
415} Context_Control;
416
417#define _CPU_Context_Get_SP( _context ) \
418  (uintptr_t) (_context)->sp
419
420/* WARNING: If this structure is modified, the constants in cpu.h
421 *          must also be updated.
422 */
423
424typedef struct {
425#if ( CPU_HARDWARE_FP == TRUE )
426    __MIPS_FPU_REGISTER_TYPE fp0;
427    __MIPS_FPU_REGISTER_TYPE fp1;
428    __MIPS_FPU_REGISTER_TYPE fp2;
429    __MIPS_FPU_REGISTER_TYPE fp3;
430    __MIPS_FPU_REGISTER_TYPE fp4;
431    __MIPS_FPU_REGISTER_TYPE fp5;
432    __MIPS_FPU_REGISTER_TYPE fp6;
433    __MIPS_FPU_REGISTER_TYPE fp7;
434    __MIPS_FPU_REGISTER_TYPE fp8;
435    __MIPS_FPU_REGISTER_TYPE fp9;
436    __MIPS_FPU_REGISTER_TYPE fp10;
437    __MIPS_FPU_REGISTER_TYPE fp11;
438    __MIPS_FPU_REGISTER_TYPE fp12;
439    __MIPS_FPU_REGISTER_TYPE fp13;
440    __MIPS_FPU_REGISTER_TYPE fp14;
441    __MIPS_FPU_REGISTER_TYPE fp15;
442    __MIPS_FPU_REGISTER_TYPE fp16;
443    __MIPS_FPU_REGISTER_TYPE fp17;
444    __MIPS_FPU_REGISTER_TYPE fp18;
445    __MIPS_FPU_REGISTER_TYPE fp19;
446    __MIPS_FPU_REGISTER_TYPE fp20;
447    __MIPS_FPU_REGISTER_TYPE fp21;
448    __MIPS_FPU_REGISTER_TYPE fp22;
449    __MIPS_FPU_REGISTER_TYPE fp23;
450    __MIPS_FPU_REGISTER_TYPE fp24;
451    __MIPS_FPU_REGISTER_TYPE fp25;
452    __MIPS_FPU_REGISTER_TYPE fp26;
453    __MIPS_FPU_REGISTER_TYPE fp27;
454    __MIPS_FPU_REGISTER_TYPE fp28;
455    __MIPS_FPU_REGISTER_TYPE fp29;
456    __MIPS_FPU_REGISTER_TYPE fp30;
457    __MIPS_FPU_REGISTER_TYPE fp31;
458    uint32_t fpcs;
459#endif
460} Context_Control_fp;
461
462/*
463 *  This struct reflects the stack frame employed in ISR_Handler.  Note
464 *  that the ISR routine save some of the registers to this frame for
465 *  all interrupts and exceptions.  Other registers are saved only on
466 *  exceptions, while others are not touched at all.  The untouched
467 *  registers are not normally disturbed by high-level language
468 *  programs so they can be accessed when required.
469 *
470 *  The registers and their ordering in this struct must directly
471 *  correspond to the layout and ordering of * shown in iregdef.h,
472 *  as cpu_asm.S uses those definitions to fill the stack frame.
473 *  This struct provides access to the stack frame for C code.
474 *
475 *  Similarly, this structure is used by debugger stubs and exception
476 *  processing routines so be careful when changing the format.
477 *
478 *  NOTE: The comments with this structure and cpu_asm.S should be kept
479 *        in sync.  When in doubt, look in the  code to see if the
480 *        registers you're interested in are actually treated as expected.
481 *        The order of the first portion of this structure follows the
482 *        order of registers expected by gdb.
483 */
484
485typedef struct
486{
487  __MIPS_REGISTER_TYPE  r0;       /*  0 -- NOT FILLED IN */
488  __MIPS_REGISTER_TYPE  at;       /*  1 -- saved always */
489  __MIPS_REGISTER_TYPE  v0;       /*  2 -- saved always */
490  __MIPS_REGISTER_TYPE  v1;       /*  3 -- saved always */
491  __MIPS_REGISTER_TYPE  a0;       /*  4 -- saved always */
492  __MIPS_REGISTER_TYPE  a1;       /*  5 -- saved always */
493  __MIPS_REGISTER_TYPE  a2;       /*  6 -- saved always */
494  __MIPS_REGISTER_TYPE  a3;       /*  7 -- saved always */
495  __MIPS_REGISTER_TYPE  t0;       /*  8 -- saved always */
496  __MIPS_REGISTER_TYPE  t1;       /*  9 -- saved always */
497  __MIPS_REGISTER_TYPE  t2;       /* 10 -- saved always */
498  __MIPS_REGISTER_TYPE  t3;       /* 11 -- saved always */
499  __MIPS_REGISTER_TYPE  t4;       /* 12 -- saved always */
500  __MIPS_REGISTER_TYPE  t5;       /* 13 -- saved always */
501  __MIPS_REGISTER_TYPE  t6;       /* 14 -- saved always */
502  __MIPS_REGISTER_TYPE  t7;       /* 15 -- saved always */
503  __MIPS_REGISTER_TYPE  s0;       /* 16 -- saved on exceptions */
504  __MIPS_REGISTER_TYPE  s1;       /* 17 -- saved on exceptions */
505  __MIPS_REGISTER_TYPE  s2;       /* 18 -- saved on exceptions */
506  __MIPS_REGISTER_TYPE  s3;       /* 19 -- saved on exceptions */
507  __MIPS_REGISTER_TYPE  s4;       /* 20 -- saved on exceptions */
508  __MIPS_REGISTER_TYPE  s5;       /* 21 -- saved on exceptions */
509  __MIPS_REGISTER_TYPE  s6;       /* 22 -- saved on exceptions */
510  __MIPS_REGISTER_TYPE  s7;       /* 23 -- saved on exceptions */
511  __MIPS_REGISTER_TYPE  t8;       /* 24 -- saved always */
512  __MIPS_REGISTER_TYPE  t9;       /* 25 -- saved always */
513  __MIPS_REGISTER_TYPE  k0;       /* 26 -- NOT FILLED IN, kernel tmp reg */
514  __MIPS_REGISTER_TYPE  k1;       /* 27 -- NOT FILLED IN, kernel tmp reg */
515  __MIPS_REGISTER_TYPE  gp;       /* 28 -- saved always */
516  __MIPS_REGISTER_TYPE  sp;       /* 29 -- saved on exceptions NOT RESTORED */
517  __MIPS_REGISTER_TYPE  fp;       /* 30 -- saved always */
518  __MIPS_REGISTER_TYPE  ra;       /* 31 -- saved always */
519  __MIPS_REGISTER_TYPE  c0_sr;    /* 32 -- saved always, some bits are */
520                                  /*    manipulated per-thread          */
521  __MIPS_REGISTER_TYPE  mdlo;     /* 33 -- saved always */
522  __MIPS_REGISTER_TYPE  mdhi;     /* 34 -- saved always */
523  __MIPS_REGISTER_TYPE  badvaddr; /* 35 -- saved on exceptions, read-only */
524  __MIPS_REGISTER_TYPE  cause;    /* 36 -- saved on exceptions NOT restored */
525  __MIPS_REGISTER_TYPE  epc;      /* 37 -- saved always, read-only register */
526                                  /*        but logically restored */
527  __MIPS_FPU_REGISTER_TYPE f0;    /* 38 -- saved if FP enabled */
528  __MIPS_FPU_REGISTER_TYPE f1;    /* 39 -- saved if FP enabled */
529  __MIPS_FPU_REGISTER_TYPE f2;    /* 40 -- saved if FP enabled */
530  __MIPS_FPU_REGISTER_TYPE f3;    /* 41 -- saved if FP enabled */
531  __MIPS_FPU_REGISTER_TYPE f4;    /* 42 -- saved if FP enabled */
532  __MIPS_FPU_REGISTER_TYPE f5;    /* 43 -- saved if FP enabled */
533  __MIPS_FPU_REGISTER_TYPE f6;    /* 44 -- saved if FP enabled */
534  __MIPS_FPU_REGISTER_TYPE f7;    /* 45 -- saved if FP enabled */
535  __MIPS_FPU_REGISTER_TYPE f8;    /* 46 -- saved if FP enabled */
536  __MIPS_FPU_REGISTER_TYPE f9;    /* 47 -- saved if FP enabled */
537  __MIPS_FPU_REGISTER_TYPE f10;   /* 48 -- saved if FP enabled */
538  __MIPS_FPU_REGISTER_TYPE f11;   /* 49 -- saved if FP enabled */
539  __MIPS_FPU_REGISTER_TYPE f12;   /* 50 -- saved if FP enabled */
540  __MIPS_FPU_REGISTER_TYPE f13;   /* 51 -- saved if FP enabled */
541  __MIPS_FPU_REGISTER_TYPE f14;   /* 52 -- saved if FP enabled */
542  __MIPS_FPU_REGISTER_TYPE f15;   /* 53 -- saved if FP enabled */
543  __MIPS_FPU_REGISTER_TYPE f16;   /* 54 -- saved if FP enabled */
544  __MIPS_FPU_REGISTER_TYPE f17;   /* 55 -- saved if FP enabled */
545  __MIPS_FPU_REGISTER_TYPE f18;   /* 56 -- saved if FP enabled */
546  __MIPS_FPU_REGISTER_TYPE f19;   /* 57 -- saved if FP enabled */
547  __MIPS_FPU_REGISTER_TYPE f20;   /* 58 -- saved if FP enabled */
548  __MIPS_FPU_REGISTER_TYPE f21;   /* 59 -- saved if FP enabled */
549  __MIPS_FPU_REGISTER_TYPE f22;   /* 60 -- saved if FP enabled */
550  __MIPS_FPU_REGISTER_TYPE f23;   /* 61 -- saved if FP enabled */
551  __MIPS_FPU_REGISTER_TYPE f24;   /* 62 -- saved if FP enabled */
552  __MIPS_FPU_REGISTER_TYPE f25;   /* 63 -- saved if FP enabled */
553  __MIPS_FPU_REGISTER_TYPE f26;   /* 64 -- saved if FP enabled */
554  __MIPS_FPU_REGISTER_TYPE f27;   /* 65 -- saved if FP enabled */
555  __MIPS_FPU_REGISTER_TYPE f28;   /* 66 -- saved if FP enabled */
556  __MIPS_FPU_REGISTER_TYPE f29;   /* 67 -- saved if FP enabled */
557  __MIPS_FPU_REGISTER_TYPE f30;   /* 68 -- saved if FP enabled */
558  __MIPS_FPU_REGISTER_TYPE f31;   /* 69 -- saved if FP enabled */
559  __MIPS_REGISTER_TYPE     fcsr;  /* 70 -- saved on exceptions */
560                                  /*    (oddly not documented on MGV) */
561  __MIPS_REGISTER_TYPE     feir;  /* 71 -- saved on exceptions */
562                                  /*    (oddly not documented on MGV) */
563
564  /* GDB does not seem to care about anything past this point */
565
566  __MIPS_REGISTER_TYPE  tlbhi;    /* 72 - NOT FILLED IN, doesn't exist on */
567                                  /*         all MIPS CPUs (at least MGV) */
568#if __mips == 1
569  __MIPS_REGISTER_TYPE  tlblo;    /* 73 - NOT FILLED IN, doesn't exist on */
570                                  /*         all MIPS CPUs (at least MGV) */
571#endif
572#if  (__mips == 3) || (__mips == 32)
573  __MIPS_REGISTER_TYPE  tlblo0;   /* 73 - NOT FILLED IN, doesn't exist on */
574                                  /*         all MIPS CPUs (at least MGV) */
575#endif
576
577  __MIPS_REGISTER_TYPE  inx;      /* 74 -- NOT FILLED IN, doesn't exist on */
578                                  /*         all MIPS CPUs (at least MGV) */
579  __MIPS_REGISTER_TYPE  rand;     /* 75 -- NOT FILLED IN, doesn't exist on */
580                                  /*         all MIPS CPUs (at least MGV) */
581  __MIPS_REGISTER_TYPE  ctxt;     /* 76 -- NOT FILLED IN, doesn't exist on */
582                                  /*         all MIPS CPUs (at least MGV) */
583  __MIPS_REGISTER_TYPE  exctype;  /* 77 -- NOT FILLED IN (not enough info) */
584  __MIPS_REGISTER_TYPE  mode;     /* 78 -- NOT FILLED IN (not enough info) */
585  __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
586  __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
587  /* end of __mips == 1 so NREGS == 81 */
588#if  (__mips == 3) || (__mips == 32)
589  __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
590  __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
591  __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
592  __MIPS_REGISTER_TYPE  count;    /* 84 -- NOT FILLED IN */
593  __MIPS_REGISTER_TYPE  compare;  /* 85 -- NOT FILLED IN */
594  __MIPS_REGISTER_TYPE  config;   /* 86 -- NOT FILLED IN */
595  __MIPS_REGISTER_TYPE  lladdr;   /* 87 -- NOT FILLED IN */
596  __MIPS_REGISTER_TYPE  watchlo;  /* 88 -- NOT FILLED IN */
597  __MIPS_REGISTER_TYPE  watchhi;  /* 89 -- NOT FILLED IN */
598  __MIPS_REGISTER_TYPE  ecc;      /* 90 -- NOT FILLED IN */
599  __MIPS_REGISTER_TYPE  cacheerr; /* 91 -- NOT FILLED IN */
600  __MIPS_REGISTER_TYPE  taglo;    /* 92 -- NOT FILLED IN */
601  __MIPS_REGISTER_TYPE  taghi;    /* 93 -- NOT FILLED IN */
602  __MIPS_REGISTER_TYPE  errpc;    /* 94 -- NOT FILLED IN */
603  __MIPS_REGISTER_TYPE  xctxt;    /* 95 -- NOT FILLED IN */
604 /* end of __mips == 3 so NREGS == 96 */
605#endif
606
607} CPU_Interrupt_frame;
608
609/*
610 *  This variable is optional.  It is used on CPUs on which it is difficult
611 *  to generate an "uninitialized" FP context.  It is filled in by
612 *  _CPU_Initialize and copied into the task's FP context area during
613 *  _CPU_Context_Initialize.
614 */
615
616SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
617
618/*
619 *  Nothing prevents the porter from declaring more CPU specific variables.
620 */
621
622/* XXX: if needed, put more variables here */
623
624/*
625 *  The size of the floating point context area.  On some CPUs this
626 *  will not be a "sizeof" because the format of the floating point
627 *  area is not defined -- only the size is.  This is usually on
628 *  CPUs with a "floating point save context" instruction.
629 */
630
631#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
632
633/*
634 *  Amount of extra stack (above minimum stack size) required by
635 *  system initialization thread.  Remember that in a multiprocessor
636 *  system the system intialization thread becomes the MP server thread.
637 */
638
639#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
640
641/*
642 *  This defines the number of entries in the ISR_Vector_table managed
643 *  by RTEMS.
644 */
645
646extern unsigned int mips_interrupt_number_of_vectors;
647#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (mips_interrupt_number_of_vectors)
648#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
649
650/*
651 *  Should be large enough to run all RTEMS tests.  This ensures
652 *  that a "reasonable" small application should not have any problems.
653 */
654
655#define CPU_STACK_MINIMUM_SIZE          (8 * 1024)
656
657/*
658 *  CPU's worst alignment requirement for data types on a byte boundary.  This
659 *  alignment does not take into account the requirements for the stack.
660 */
661
662#define CPU_ALIGNMENT              8
663
664/*
665 *  This number corresponds to the byte alignment requirement for the
666 *  heap handler.  This alignment requirement may be stricter than that
667 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
668 *  common for the heap to follow the same alignment requirement as
669 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
670 *  then this should be set to CPU_ALIGNMENT.
671 *
672 *  NOTE:  This does not have to be a power of 2.  It does have to
673 *         be greater or equal to than CPU_ALIGNMENT.
674 */
675
676#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
677
678/*
679 *  This number corresponds to the byte alignment requirement for memory
680 *  buffers allocated by the partition manager.  This alignment requirement
681 *  may be stricter than that for the data types alignment specified by
682 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
683 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
684 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
685 *
686 *  NOTE:  This does not have to be a power of 2.  It does have to
687 *         be greater or equal to than CPU_ALIGNMENT.
688 */
689
690#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
691
692/*
693 *  This number corresponds to the byte alignment requirement for the
694 *  stack.  This alignment requirement may be stricter than that for the
695 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
696 *  is strict enough for the stack, then this should be set to 0.
697 *
698 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
699 */
700
701#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
702
703/*
704 *  ISR handler macros
705 */
706
707/*
708 *  Support routine to initialize the RTEMS vector table after it is allocated.
709 */
710
711#define _CPU_Initialize_vectors()
712
713/*
714 *  Declare the function that is present in the shared libcpu directory,
715 *  that returns the processor dependent interrupt mask.
716 */
717
718uint32_t mips_interrupt_mask( void );
719
720/*
721 *  Disable all interrupts for an RTEMS critical section.  The previous
722 *  level is returned in _level.
723 */
724
725#define _CPU_ISR_Disable( _level ) \
726  do { \
727    unsigned int _scratch; \
728    mips_get_sr( _scratch ); \
729    mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
730    _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
731  } while(0)
732
733/*
734 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
735 *  This indicates the end of an RTEMS critical section.  The parameter
736 *  _level is not modified.
737 */
738
739#define _CPU_ISR_Enable( _level )  \
740  do { \
741    unsigned int _scratch; \
742    mips_get_sr( _scratch ); \
743    mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
744  } while(0)
745
746/*
747 *  This temporarily restores the interrupt to _level before immediately
748 *  disabling them again.  This is used to divide long RTEMS critical
749 *  sections into two or more parts.  The parameter _level is not
750 *  modified.
751 */
752
753#define _CPU_ISR_Flash( _xlevel ) \
754  do { \
755    unsigned int _scratch2 = _xlevel; \
756    _CPU_ISR_Enable( _scratch2 ); \
757    _CPU_ISR_Disable( _scratch2 ); \
758    _xlevel = _scratch2; \
759  } while(0)
760
761/*
762 *  Map interrupt level in task mode onto the hardware that the CPU
763 *  actually provides.  Currently, interrupt levels which do not
764 *  map onto the CPU in a generic fashion are undefined.  Someday,
765 *  it would be nice if these were "mapped" by the application
766 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
767 *  8 - 255 would be available for bsp/application specific meaning.
768 *  This could be used to manage a programmable interrupt controller
769 *  via the rtems_task_mode directive.
770 *
771 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
772 *  manipulates the IEC.
773 */
774
775uint32_t   _CPU_ISR_Get_level( void );  /* in cpu.c */
776
777void _CPU_ISR_Set_level( uint32_t   );  /* in cpu.c */
778
779/* end of ISR handler macros */
780
781/* Context handler macros */
782
783/*
784 *  Initialize the context to a state suitable for starting a
785 *  task after a context restore operation.  Generally, this
786 *  involves:
787 *
788 *     - setting a starting address
789 *     - preparing the stack
790 *     - preparing the stack and frame pointers
791 *     - setting the proper interrupt level in the context
792 *     - initializing the floating point context
793 *
794 *  This routine generally does not set any unnecessary register
795 *  in the context.  The state of the "general data" registers is
796 *  undefined at task start time.
797 *
798 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
799 *        point thread.  This is typically only used on CPUs where the
800 *        FPU may be easily disabled by software such as on the SPARC
801 *        where the PSR contains an enable FPU bit.
802 *
803 *  The per-thread status register holds the interrupt enable, FP enable
804 *  and global interrupt enable for that thread.  It means each thread can
805 *  enable its own set of interrupts.  If interrupts are disabled, RTEMS
806 *  can still dispatch via blocking calls.  This is the function of the
807 *  "Interrupt Level", and on the MIPS, it controls the IEC bit and all
808 *  the hardware interrupts as defined in the SR.  Software ints
809 *  are automatically enabled for all threads, as they will only occur under
810 *  program control anyhow.  Besides, the interrupt level parm is only 8 bits,
811 *  and controlling the software ints plus the others would require 9.
812 *
813 *  If the Interrupt Level is 0, all ints are on.  Otherwise, the
814 *  Interrupt Level should supply a bit pattern to impose on the SR
815 *  interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6
816 *  apply to the SR register Intr bits from bit 10 thru bit 15.  Bit 7 of
817 *  the Interrupt Level parameter is unused at this time.
818 *
819 *  These are the only per-thread SR bits, the others are maintained
820 *  globally & explicitly preserved by the Context Switch code in cpu_asm.s
821 */
822
823
824#if (__mips == 3) || (__mips == 32)
825#define _INTON          SR_IE
826#if __mips_fpr==64
827#define _EXTRABITS      SR_FR
828#else
829#define _EXTRABITS      0
830#endif /* __mips_fpr==64 */
831#endif /* __mips == 3 */
832#if __mips == 1
833#define _INTON          SR_IEC
834#define _EXTRABITS      0  /* make sure we're in user mode on MIPS1 processors */
835#endif /* __mips == 1 */
836
837
838void _CPU_Context_Initialize(
839  Context_Control  *the_context,
840  uintptr_t        *stack_base,
841  uint32_t          size,
842  uint32_t          new_level,
843  void             *entry_point,
844  bool              is_fp
845);
846
847
848/*
849 *  This routine is responsible for somehow restarting the currently
850 *  executing task.  If you are lucky, then all that is necessary
851 *  is restoring the context.  Otherwise, there will need to be
852 *  a special assembly routine which does something special in this
853 *  case.  Context_Restore should work most of the time.  It will
854 *  not work if restarting self conflicts with the stack frame
855 *  assumptions of restoring a context.
856 */
857
858#define _CPU_Context_Restart_self( _the_context ) \
859   _CPU_Context_restore( (_the_context) );
860
861/*
862 *  The purpose of this macro is to allow the initial pointer into
863 *  A floating point context area (used to save the floating point
864 *  context) to be at an arbitrary place in the floating point
865 *  context area.
866 *
867 *  This is necessary because some FP units are designed to have
868 *  their context saved as a stack which grows into lower addresses.
869 *  Other FP units can be saved by simply moving registers into offsets
870 *  from the base of the context area.  Finally some FP units provide
871 *  a "dump context" instruction which could fill in from high to low
872 *  or low to high based on the whim of the CPU designers.
873 */
874
875#define _CPU_Context_Fp_start( _base, _offset ) \
876   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
877
878/*
879 *  This routine initializes the FP context area passed to it to.
880 *  There are a few standard ways in which to initialize the
881 *  floating point context.  The code included for this macro assumes
882 *  that this is a CPU in which a "initial" FP context was saved into
883 *  _CPU_Null_fp_context and it simply copies it to the destination
884 *  context passed to it.
885 *
886 *  Other models include (1) not doing anything, and (2) putting
887 *  a "null FP status word" in the correct place in the FP context.
888 */
889
890#if ( CPU_HARDWARE_FP == TRUE )
891#define _CPU_Context_Initialize_fp( _destination ) \
892  { \
893   *(*(_destination)) = _CPU_Null_fp_context; \
894  }
895#endif
896
897/* end of Context handler macros */
898
899/* Fatal Error manager macros */
900
901/*
902 *  This routine copies _error into a known place -- typically a stack
903 *  location or a register, optionally disables interrupts, and
904 *  halts/stops the CPU.
905 */
906
907#define _CPU_Fatal_halt( _error ) \
908  do { \
909    unsigned int _level; \
910    _CPU_ISR_Disable(_level); \
911    loop: goto loop; \
912  } while (0)
913
914
915extern void mips_break( int error );
916
917/* Bitfield handler macros */
918
919/*
920 *  This routine sets _output to the bit number of the first bit
921 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Control.
922 *  This type may be either 16 or 32 bits wide although only the 16
923 *  least significant bits will be used.
924 *
925 *  There are a number of variables in using a "find first bit" type
926 *  instruction.
927 *
928 *    (1) What happens when run on a value of zero?
929 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
930 *    (3) The numbering may be zero or one based.
931 *    (4) The "find first bit" instruction may search from MSB or LSB.
932 *
933 *  RTEMS guarantees that (1) will never happen so it is not a concern.
934 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
935 *  _CPU_Priority_bits_index().  These three form a set of routines
936 *  which must logically operate together.  Bits in the _value are
937 *  set and cleared based on masks built by _CPU_Priority_mask().
938 *  The basic major and minor values calculated by _Priority_Major()
939 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
940 *  to properly range between the values returned by the "find first bit"
941 *  instruction.  This makes it possible for _Priority_Get_highest() to
942 *  calculate the major and directly index into the minor table.
943 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
944 *  is the first bit found.
945 *
946 *  This entire "find first bit" and mapping process depends heavily
947 *  on the manner in which a priority is broken into a major and minor
948 *  components with the major being the 4 MSB of a priority and minor
949 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
950 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
951 *  to the lowest priority.
952 *
953 *  If your CPU does not have a "find first bit" instruction, then
954 *  there are ways to make do without it.  Here are a handful of ways
955 *  to implement this in software:
956 *
957 *    - a series of 16 bit test instructions
958 *    - a "binary search using if's"
959 *    - _number = 0
960 *      if _value > 0x00ff
961 *        _value >>=8
962 *        _number = 8;
963 *
964 *      if _value > 0x0000f
965 *        _value >=8
966 *        _number += 4
967 *
968 *      _number += bit_set_table[ _value ]
969 *
970 *    where bit_set_table[ 16 ] has values which indicate the first
971 *      bit set
972 */
973
974#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
975#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
976
977#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
978
979#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
980  { \
981    (_output) = 0;   /* do something to prevent warnings */ \
982  }
983
984#endif
985
986/* end of Bitfield handler macros */
987
988/*
989 *  This routine builds the mask which corresponds to the bit fields
990 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
991 *  for that routine.
992 */
993
994#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
995
996#define _CPU_Priority_Mask( _bit_number ) \
997  ( 1 << (_bit_number) )
998
999#endif
1000
1001/*
1002 *  This routine translates the bit numbers returned by
1003 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
1004 *  a major or minor component of a priority.  See the discussion
1005 *  for that routine.
1006 */
1007
1008#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1009
1010#define _CPU_Priority_bits_index( _priority ) \
1011  (_priority)
1012
1013#endif
1014
1015/* end of Priority handler macros */
1016
1017/* functions */
1018
1019/*
1020 *  _CPU_Initialize
1021 *
1022 *  This routine performs CPU dependent initialization.
1023 */
1024
1025void _CPU_Initialize(void);
1026
1027/*
1028 *  _CPU_ISR_install_raw_handler
1029 *
1030 *  This routine installs a "raw" interrupt handler directly into the
1031 *  processor's vector table.
1032 */
1033
1034void _CPU_ISR_install_raw_handler(
1035  uint32_t    vector,
1036  proc_ptr    new_handler,
1037  proc_ptr   *old_handler
1038);
1039
1040/*
1041 *  _CPU_ISR_install_vector
1042 *
1043 *  This routine installs an interrupt vector.
1044 */
1045
1046void _CPU_ISR_install_vector(
1047  uint32_t    vector,
1048  proc_ptr    new_handler,
1049  proc_ptr   *old_handler
1050);
1051
1052/*
1053 *  _CPU_Install_interrupt_stack
1054 *
1055 *  This routine installs the hardware interrupt stack pointer.
1056 *
1057 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1058 *         is TRUE.
1059 */
1060
1061void _CPU_Install_interrupt_stack( void );
1062
1063/*
1064 *  _CPU_Internal_threads_Idle_thread_body
1065 *
1066 *  This routine is the CPU dependent IDLE thread body.
1067 *
1068 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1069 *         is TRUE.
1070 */
1071
1072void *_CPU_Thread_Idle_body( uintptr_t ignored );
1073
1074/*
1075 *  _CPU_Context_switch
1076 *
1077 *  This routine switches from the run context to the heir context.
1078 */
1079
1080void _CPU_Context_switch(
1081  Context_Control  *run,
1082  Context_Control  *heir
1083);
1084
1085/*
1086 *  _CPU_Context_restore
1087 *
1088 *  This routine is generally used only to restart self in an
1089 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1090 *
1091 *  NOTE: May be unnecessary to reload some registers.
1092 */
1093
1094void _CPU_Context_restore(
1095  Context_Control *new_context
1096) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1097
1098/*
1099 *  _CPU_Context_save_fp
1100 *
1101 *  This routine saves the floating point context passed to it.
1102 */
1103
1104void _CPU_Context_save_fp(
1105  Context_Control_fp **fp_context_ptr
1106);
1107
1108/*
1109 *  _CPU_Context_restore_fp
1110 *
1111 *  This routine restores the floating point context passed to it.
1112 */
1113
1114void _CPU_Context_restore_fp(
1115  Context_Control_fp **fp_context_ptr
1116);
1117
1118/*  The following routine swaps the endian format of an unsigned int.
1119 *  It must be static because it is referenced indirectly.
1120 *
1121 *  This version will work on any processor, but if there is a better
1122 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1123 *
1124 *     swap least significant two bytes with 16-bit rotate
1125 *     swap upper and lower 16-bits
1126 *     swap most significant two bytes with 16-bit rotate
1127 *
1128 *  Some CPUs have special instructions which swap a 32-bit quantity in
1129 *  a single instruction (e.g. i486).  It is probably best to avoid
1130 *  an "endian swapping control bit" in the CPU.  One good reason is
1131 *  that interrupts would probably have to be disabled to ensure that
1132 *  an interrupt does not try to access the same "chunk" with the wrong
1133 *  endian.  Another good reason is that on some CPUs, the endian bit
1134 *  endianness for ALL fetches -- both code and data -- so the code
1135 *  will be fetched incorrectly.
1136 */
1137
1138static inline uint32_t CPU_swap_u32(
1139  uint32_t value
1140)
1141{
1142  uint32_t   byte1, byte2, byte3, byte4, swapped;
1143
1144  byte4 = (value >> 24) & 0xff;
1145  byte3 = (value >> 16) & 0xff;
1146  byte2 = (value >> 8)  & 0xff;
1147  byte1 =  value        & 0xff;
1148
1149  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1150  return( swapped );
1151}
1152
1153#define CPU_swap_u16( value ) \
1154  (((value&0xff) << 8) | ((value >> 8)&0xff))
1155
1156
1157#endif
1158
1159
1160
1161#ifdef __cplusplus
1162}
1163#endif
1164
1165#endif
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