source: rtems/cpukit/score/cpu/mips/rtems/score/cpu.h @ 4ef13360

4.11
Last change on this file since 4ef13360 was 4ef13360, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 29, 2010 at 5:51:56 PM

2010-07-29 Gedare Bloom <giddyup44@…>

PR 1635/cpukit

  • rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority handling, to isolate the bitmap implementation of priorities in the supercore so that priority management is a little more modular. This change is in anticipation of scheduler implementations that can select how they manage tracking priority levels / finding the highest priority ready task. Note that most of the changes here are simple renaming, to clarify the use of the bitmap-based priority management.
  • Property mode set to 100644
File size: 41.0 KB
Line 
1/*
2 *  Mips CPU Dependent Header File
3 *
4 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
5 *           Joel Sherrill <joel@OARcorp.com>.
6 *
7 *    These changes made the code conditional on standard cpp predefines,
8 *    merged the mips1 and mips3 code sequences as much as possible,
9 *    and moved some of the assembly code to C.  Alan did much of the
10 *    initial analysis and rework.  Joel took over from there and
11 *    wrote the JMR3904 BSP so this could be tested.  Joel also
12 *    added the new interrupt vectoring support in libcpu and
13 *    tried to better support the various interrupt controllers.
14 *
15 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
16 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
17 *
18 *    To anyone who acknowledges that this file is provided "AS IS"
19 *    without any express or implied warranty:
20 *      permission to use, copy, modify, and distribute this file
21 *      for any purpose is hereby granted without fee, provided that
22 *      the above copyright notice and this notice appears in all
23 *      copies, and that the name of Transition Networks not be used in
24 *      advertising or publicity pertaining to distribution of the
25 *      software without specific, written prior permission.
26 *      Transition Networks makes no representations about the suitability
27 *      of this software for any purpose.
28 *
29 *  COPYRIGHT (c) 1989-2006.
30 *  On-Line Applications Research Corporation (OAR).
31 *
32 *  The license and distribution terms for this file may be
33 *  found in the file LICENSE in this distribution or at
34 *  http://www.rtems.com/license/LICENSE.
35 *
36 *  $Id$
37 */
38
39#ifndef _RTEMS_SCORE_CPU_H
40#define _RTEMS_SCORE_CPU_H
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
46#include <rtems/score/types.h>
47#include <rtems/score/mips.h>
48
49/* conditional compilation parameters */
50
51/*
52 *  Should the calls to _Thread_Enable_dispatch be inlined?
53 *
54 *  If TRUE, then they are inlined.
55 *  If FALSE, then a subroutine call is made.
56 *
57 *  Basically this is an example of the classic trade-off of size
58 *  versus speed.  Inlining the call (TRUE) typically increases the
59 *  size of RTEMS while speeding up the enabling of dispatching.
60 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
61 *  only be 0 or 1 unless you are in an interrupt handler and that
62 *  interrupt handler invokes the executive.]  When not inlined
63 *  something calls _Thread_Enable_dispatch which in turns calls
64 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
65 *  one subroutine call is avoided entirely.]
66 */
67
68#define CPU_INLINE_ENABLE_DISPATCH       FALSE
69
70/*
71 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
72 *  be unrolled one time?  In unrolled each iteration of the loop examines
73 *  two "nodes" on the chain being searched.  Otherwise, only one node
74 *  is examined per iteration.
75 *
76 *  If TRUE, then the loops are unrolled.
77 *  If FALSE, then the loops are not unrolled.
78 *
79 *  The primary factor in making this decision is the cost of disabling
80 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
81 *  body of the loop.  On some CPUs, the flash is more expensive than
82 *  one iteration of the loop body.  In this case, it might be desirable
83 *  to unroll the loop.  It is important to note that on some CPUs, this
84 *  code is the longest interrupt disable period in RTEMS.  So it is
85 *  necessary to strike a balance when setting this parameter.
86 */
87
88#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
89
90/*
91 *  Does RTEMS manage a dedicated interrupt stack in software?
92 *
93 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
94 *  If FALSE, nothing is done.
95 *
96 *  If the CPU supports a dedicated interrupt stack in hardware,
97 *  then it is generally the responsibility of the BSP to allocate it
98 *  and set it up.
99 *
100 *  If the CPU does not support a dedicated interrupt stack, then
101 *  the porter has two options: (1) execute interrupts on the
102 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
103 *  interrupt stack.
104 *
105 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
106 *
107 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
108 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
109 *  possible that both are FALSE for a particular CPU.  Although it
110 *  is unclear what that would imply about the interrupt processing
111 *  procedure on that CPU.
112 */
113
114#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
115
116/*
117 *  Does the CPU follow the simple vectored interrupt model?
118 *
119 *  If TRUE, then RTEMS allocates the vector table it internally manages.
120 *  If FALSE, then the BSP is assumed to allocate and manage the vector
121 *  table
122 *
123 *  MIPS Specific Information:
124 *
125 *  XXX document implementation including references if appropriate
126 */
127#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
128
129/*
130 *  Does this CPU have hardware support for a dedicated interrupt stack?
131 *
132 *  If TRUE, then it must be installed during initialization.
133 *  If FALSE, then no installation is performed.
134 *
135 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
136 *
137 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
138 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
139 *  possible that both are FALSE for a particular CPU.  Although it
140 *  is unclear what that would imply about the interrupt processing
141 *  procedure on that CPU.
142 */
143
144#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
145
146/*
147 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
148 *
149 *  If TRUE, then the memory is allocated during initialization.
150 *  If FALSE, then the memory is allocated during initialization.
151 *
152 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
153 */
154
155#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
156
157/*
158 *  Does the RTEMS invoke the user's ISR with the vector number and
159 *  a pointer to the saved interrupt frame (1) or just the vector
160 *  number (0)?
161 *
162 */
163
164#define CPU_ISR_PASSES_FRAME_POINTER 1
165
166
167
168/*
169 *  Does the CPU have hardware floating point?
170 *
171 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
172 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
173 *
174 *  If there is a FP coprocessor such as the i387 or mc68881, then
175 *  the answer is TRUE.
176 *
177 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
178 *  It indicates whether or not this CPU model has FP support.  For
179 *  example, it would be possible to have an i386_nofp CPU model
180 *  which set this to false to indicate that you have an i386 without
181 *  an i387 and wish to leave floating point support out of RTEMS.
182 */
183
184#if ( MIPS_HAS_FPU == 1 )
185#define CPU_HARDWARE_FP     TRUE
186#else
187#define CPU_HARDWARE_FP     FALSE
188#endif
189
190/*
191 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
192 *
193 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
194 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
195 *
196 *  So far, the only CPU in which this option has been used is the
197 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
198 *  floating point registers to perform integer multiplies.  If
199 *  a function which you would not think utilize the FP unit DOES,
200 *  then one can not easily predict which tasks will use the FP hardware.
201 *  In this case, this option should be TRUE.
202 *
203 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
204 */
205
206#define CPU_ALL_TASKS_ARE_FP    FALSE
207
208/*
209 *  Should the IDLE task have a floating point context?
210 *
211 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
212 *  and it has a floating point context which is switched in and out.
213 *  If FALSE, then the IDLE task does not have a floating point context.
214 *
215 *  Setting this to TRUE negatively impacts the time required to preempt
216 *  the IDLE task from an interrupt because the floating point context
217 *  must be saved as part of the preemption.
218 */
219
220#define CPU_IDLE_TASK_IS_FP      FALSE
221
222/*
223 *  Should the saving of the floating point registers be deferred
224 *  until a context switch is made to another different floating point
225 *  task?
226 *
227 *  If TRUE, then the floating point context will not be stored until
228 *  necessary.  It will remain in the floating point registers and not
229 *  disturned until another floating point task is switched to.
230 *
231 *  If FALSE, then the floating point context is saved when a floating
232 *  point task is switched out and restored when the next floating point
233 *  task is restored.  The state of the floating point registers between
234 *  those two operations is not specified.
235 *
236 *  If the floating point context does NOT have to be saved as part of
237 *  interrupt dispatching, then it should be safe to set this to TRUE.
238 *
239 *  Setting this flag to TRUE results in using a different algorithm
240 *  for deciding when to save and restore the floating point context.
241 *  The deferred FP switch algorithm minimizes the number of times
242 *  the FP context is saved and restored.  The FP context is not saved
243 *  until a context switch is made to another, different FP task.
244 *  Thus in a system with only one FP task, the FP context will never
245 *  be saved or restored.
246 */
247
248#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
249
250/*
251 *  Does this port provide a CPU dependent IDLE task implementation?
252 *
253 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
254 *  must be provided and is the default IDLE thread body instead of
255 *  _Internal_threads_Idle_thread_body.
256 *
257 *  If FALSE, then use the generic IDLE thread body if the BSP does
258 *  not provide one.
259 *
260 *  This is intended to allow for supporting processors which have
261 *  a low power or idle mode.  When the IDLE thread is executed, then
262 *  the CPU can be powered down.
263 *
264 *  The order of precedence for selecting the IDLE thread body is:
265 *
266 *    1.  BSP provided
267 *    2.  CPU dependent (if provided)
268 *    3.  generic (if no BSP and no CPU dependent)
269 */
270
271/* we can use the low power wait instruction for the IDLE thread */
272#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
273
274/*
275 *  Does the stack grow up (toward higher addresses) or down
276 *  (toward lower addresses)?
277 *
278 *  If TRUE, then the grows upward.
279 *  If FALSE, then the grows toward smaller addresses.
280 */
281
282/* our stack grows down */
283#define CPU_STACK_GROWS_UP               FALSE
284
285/*
286 *  The following is the variable attribute used to force alignment
287 *  of critical RTEMS structures.  On some processors it may make
288 *  sense to have these aligned on tighter boundaries than
289 *  the minimum requirements of the compiler in order to have as
290 *  much of the critical data area as possible in a cache line.
291 *
292 *  The placement of this macro in the declaration of the variables
293 *  is based on the syntactically requirements of the GNU C
294 *  "__attribute__" extension.  For example with GNU C, use
295 *  the following to force a structures to a 32 byte boundary.
296 *
297 *      __attribute__ ((aligned (32)))
298 *
299 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
300 *         To benefit from using this, the data must be heavily
301 *         used so it will stay in the cache and used frequently enough
302 *         in the executive to justify turning this on.
303 */
304
305/* our cache line size is 16 bytes */
306#if __GNUC__
307#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
308#else
309#define CPU_STRUCTURE_ALIGNMENT
310#endif
311
312/*
313 *  Define what is required to specify how the network to host conversion
314 *  routines are handled.
315 */
316
317/* __MIPSEB__ or __MIPSEL__ is defined by GCC based on -EB or -EL command line options */
318#if defined(__MIPSEB__)
319#define CPU_BIG_ENDIAN                           TRUE
320#define CPU_LITTLE_ENDIAN                        FALSE
321#elif defined(__MIPSEL__)
322#define CPU_BIG_ENDIAN                           FALSE
323#define CPU_LITTLE_ENDIAN                        TRUE
324#else
325#error "Unknown endianness"
326#endif
327
328/*
329 *  The following defines the number of bits actually used in the
330 *  interrupt field of the task mode.  How those bits map to the
331 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
332 */
333
334#define CPU_MODES_INTERRUPT_MASK   0x000000ff
335
336/*
337 *  Processor defined structures
338 *
339 *  Examples structures include the descriptor tables from the i386
340 *  and the processor control structure on the i960ca.
341 */
342
343/* may need to put some structures here.  */
344
345/*
346 * Contexts
347 *
348 *  Generally there are 2 types of context to save.
349 *     1. Interrupt registers to save
350 *     2. Task level registers to save
351 *
352 *  This means we have the following 3 context items:
353 *     1. task level context stuff::  Context_Control
354 *     2. floating point task stuff:: Context_Control_fp
355 *     3. special interrupt level context :: Context_Control_interrupt
356 *
357 *  On some processors, it is cost-effective to save only the callee
358 *  preserved registers during a task context switch.  This means
359 *  that the ISR code needs to save those registers which do not
360 *  persist across function calls.  It is not mandatory to make this
361 *  distinctions between the caller/callee saves registers for the
362 *  purpose of minimizing context saved during task switch and on interrupts.
363 *  If the cost of saving extra registers is minimal, simplicity is the
364 *  choice.  Save the same context on interrupt entry as for tasks in
365 *  this case.
366 *
367 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
368 *  care should be used in designing the context area.
369 *
370 *  On some CPUs with hardware floating point support, the Context_Control_fp
371 *  structure will not be used or it simply consist of an array of a
372 *  fixed number of bytes.   This is done when the floating point context
373 *  is dumped by a "FP save context" type instruction and the format
374 *  is not really defined by the CPU.  In this case, there is no need
375 *  to figure out the exact format -- only the size.  Of course, although
376 *  this is enough information for RTEMS, it is probably not enough for
377 *  a debugger such as gdb.  But that is another problem.
378 */
379
380#ifndef ASM
381
382/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
383#if (__mips == 1) || (__mips == 32)
384#define __MIPS_REGISTER_TYPE     uint32_t
385#define __MIPS_FPU_REGISTER_TYPE uint32_t
386#elif __mips == 3
387#define __MIPS_REGISTER_TYPE     uint64_t
388#define __MIPS_FPU_REGISTER_TYPE uint64_t
389#else
390#error "mips register size: unknown architecture level!!"
391#endif
392typedef struct {
393    __MIPS_REGISTER_TYPE s0;
394    __MIPS_REGISTER_TYPE s1;
395    __MIPS_REGISTER_TYPE s2;
396    __MIPS_REGISTER_TYPE s3;
397    __MIPS_REGISTER_TYPE s4;
398    __MIPS_REGISTER_TYPE s5;
399    __MIPS_REGISTER_TYPE s6;
400    __MIPS_REGISTER_TYPE s7;
401    __MIPS_REGISTER_TYPE sp;
402    __MIPS_REGISTER_TYPE fp;
403    __MIPS_REGISTER_TYPE ra;
404    __MIPS_REGISTER_TYPE c0_sr;
405    __MIPS_REGISTER_TYPE c0_epc;
406} Context_Control;
407
408#define _CPU_Context_Get_SP( _context ) \
409  (uintptr_t) (_context)->sp
410
411/* WARNING: If this structure is modified, the constants in cpu.h
412 *          must also be updated.
413 */
414
415typedef struct {
416#if ( CPU_HARDWARE_FP == TRUE )
417    __MIPS_FPU_REGISTER_TYPE fp0;
418    __MIPS_FPU_REGISTER_TYPE fp1;
419    __MIPS_FPU_REGISTER_TYPE fp2;
420    __MIPS_FPU_REGISTER_TYPE fp3;
421    __MIPS_FPU_REGISTER_TYPE fp4;
422    __MIPS_FPU_REGISTER_TYPE fp5;
423    __MIPS_FPU_REGISTER_TYPE fp6;
424    __MIPS_FPU_REGISTER_TYPE fp7;
425    __MIPS_FPU_REGISTER_TYPE fp8;
426    __MIPS_FPU_REGISTER_TYPE fp9;
427    __MIPS_FPU_REGISTER_TYPE fp10;
428    __MIPS_FPU_REGISTER_TYPE fp11;
429    __MIPS_FPU_REGISTER_TYPE fp12;
430    __MIPS_FPU_REGISTER_TYPE fp13;
431    __MIPS_FPU_REGISTER_TYPE fp14;
432    __MIPS_FPU_REGISTER_TYPE fp15;
433    __MIPS_FPU_REGISTER_TYPE fp16;
434    __MIPS_FPU_REGISTER_TYPE fp17;
435    __MIPS_FPU_REGISTER_TYPE fp18;
436    __MIPS_FPU_REGISTER_TYPE fp19;
437    __MIPS_FPU_REGISTER_TYPE fp20;
438    __MIPS_FPU_REGISTER_TYPE fp21;
439    __MIPS_FPU_REGISTER_TYPE fp22;
440    __MIPS_FPU_REGISTER_TYPE fp23;
441    __MIPS_FPU_REGISTER_TYPE fp24;
442    __MIPS_FPU_REGISTER_TYPE fp25;
443    __MIPS_FPU_REGISTER_TYPE fp26;
444    __MIPS_FPU_REGISTER_TYPE fp27;
445    __MIPS_FPU_REGISTER_TYPE fp28;
446    __MIPS_FPU_REGISTER_TYPE fp29;
447    __MIPS_FPU_REGISTER_TYPE fp30;
448    __MIPS_FPU_REGISTER_TYPE fp31;
449    uint32_t fpcs;
450#endif
451} Context_Control_fp;
452
453/*
454 *  This struct reflects the stack frame employed in ISR_Handler.  Note
455 *  that the ISR routine save some of the registers to this frame for
456 *  all interrupts and exceptions.  Other registers are saved only on
457 *  exceptions, while others are not touched at all.  The untouched
458 *  registers are not normally disturbed by high-level language
459 *  programs so they can be accessed when required.
460 *
461 *  The registers and their ordering in this struct must directly
462 *  correspond to the layout and ordering of * shown in iregdef.h,
463 *  as cpu_asm.S uses those definitions to fill the stack frame.
464 *  This struct provides access to the stack frame for C code.
465 *
466 *  Similarly, this structure is used by debugger stubs and exception
467 *  processing routines so be careful when changing the format.
468 *
469 *  NOTE: The comments with this structure and cpu_asm.S should be kept
470 *        in sync.  When in doubt, look in the  code to see if the
471 *        registers you're interested in are actually treated as expected.
472 *        The order of the first portion of this structure follows the
473 *        order of registers expected by gdb.
474 */
475
476typedef struct
477{
478  __MIPS_REGISTER_TYPE  r0;       /*  0 -- NOT FILLED IN */
479  __MIPS_REGISTER_TYPE  at;       /*  1 -- saved always */
480  __MIPS_REGISTER_TYPE  v0;       /*  2 -- saved always */
481  __MIPS_REGISTER_TYPE  v1;       /*  3 -- saved always */
482  __MIPS_REGISTER_TYPE  a0;       /*  4 -- saved always */
483  __MIPS_REGISTER_TYPE  a1;       /*  5 -- saved always */
484  __MIPS_REGISTER_TYPE  a2;       /*  6 -- saved always */
485  __MIPS_REGISTER_TYPE  a3;       /*  7 -- saved always */
486  __MIPS_REGISTER_TYPE  t0;       /*  8 -- saved always */
487  __MIPS_REGISTER_TYPE  t1;       /*  9 -- saved always */
488  __MIPS_REGISTER_TYPE  t2;       /* 10 -- saved always */
489  __MIPS_REGISTER_TYPE  t3;       /* 11 -- saved always */
490  __MIPS_REGISTER_TYPE  t4;       /* 12 -- saved always */
491  __MIPS_REGISTER_TYPE  t5;       /* 13 -- saved always */
492  __MIPS_REGISTER_TYPE  t6;       /* 14 -- saved always */
493  __MIPS_REGISTER_TYPE  t7;       /* 15 -- saved always */
494  __MIPS_REGISTER_TYPE  s0;       /* 16 -- saved on exceptions */
495  __MIPS_REGISTER_TYPE  s1;       /* 17 -- saved on exceptions */
496  __MIPS_REGISTER_TYPE  s2;       /* 18 -- saved on exceptions */
497  __MIPS_REGISTER_TYPE  s3;       /* 19 -- saved on exceptions */
498  __MIPS_REGISTER_TYPE  s4;       /* 20 -- saved on exceptions */
499  __MIPS_REGISTER_TYPE  s5;       /* 21 -- saved on exceptions */
500  __MIPS_REGISTER_TYPE  s6;       /* 22 -- saved on exceptions */
501  __MIPS_REGISTER_TYPE  s7;       /* 23 -- saved on exceptions */
502  __MIPS_REGISTER_TYPE  t8;       /* 24 -- saved always */
503  __MIPS_REGISTER_TYPE  t9;       /* 25 -- saved always */
504  __MIPS_REGISTER_TYPE  k0;       /* 26 -- NOT FILLED IN, kernel tmp reg */
505  __MIPS_REGISTER_TYPE  k1;       /* 27 -- NOT FILLED IN, kernel tmp reg */
506  __MIPS_REGISTER_TYPE  gp;       /* 28 -- saved always */
507  __MIPS_REGISTER_TYPE  sp;       /* 29 -- saved on exceptions NOT RESTORED */
508  __MIPS_REGISTER_TYPE  fp;       /* 30 -- saved always */
509  __MIPS_REGISTER_TYPE  ra;       /* 31 -- saved always */
510  __MIPS_REGISTER_TYPE  c0_sr;    /* 32 -- saved always, some bits are */
511                                  /*    manipulated per-thread          */
512  __MIPS_REGISTER_TYPE  mdlo;     /* 33 -- saved always */
513  __MIPS_REGISTER_TYPE  mdhi;     /* 34 -- saved always */
514  __MIPS_REGISTER_TYPE  badvaddr; /* 35 -- saved on exceptions, read-only */
515  __MIPS_REGISTER_TYPE  cause;    /* 36 -- saved on exceptions NOT restored */
516  __MIPS_REGISTER_TYPE  epc;      /* 37 -- saved always, read-only register */
517                                  /*        but logically restored */
518  __MIPS_FPU_REGISTER_TYPE f0;    /* 38 -- saved if FP enabled */
519  __MIPS_FPU_REGISTER_TYPE f1;    /* 39 -- saved if FP enabled */
520  __MIPS_FPU_REGISTER_TYPE f2;    /* 40 -- saved if FP enabled */
521  __MIPS_FPU_REGISTER_TYPE f3;    /* 41 -- saved if FP enabled */
522  __MIPS_FPU_REGISTER_TYPE f4;    /* 42 -- saved if FP enabled */
523  __MIPS_FPU_REGISTER_TYPE f5;    /* 43 -- saved if FP enabled */
524  __MIPS_FPU_REGISTER_TYPE f6;    /* 44 -- saved if FP enabled */
525  __MIPS_FPU_REGISTER_TYPE f7;    /* 45 -- saved if FP enabled */
526  __MIPS_FPU_REGISTER_TYPE f8;    /* 46 -- saved if FP enabled */
527  __MIPS_FPU_REGISTER_TYPE f9;    /* 47 -- saved if FP enabled */
528  __MIPS_FPU_REGISTER_TYPE f10;   /* 48 -- saved if FP enabled */
529  __MIPS_FPU_REGISTER_TYPE f11;   /* 49 -- saved if FP enabled */
530  __MIPS_FPU_REGISTER_TYPE f12;   /* 50 -- saved if FP enabled */
531  __MIPS_FPU_REGISTER_TYPE f13;   /* 51 -- saved if FP enabled */
532  __MIPS_FPU_REGISTER_TYPE f14;   /* 52 -- saved if FP enabled */
533  __MIPS_FPU_REGISTER_TYPE f15;   /* 53 -- saved if FP enabled */
534  __MIPS_FPU_REGISTER_TYPE f16;   /* 54 -- saved if FP enabled */
535  __MIPS_FPU_REGISTER_TYPE f17;   /* 55 -- saved if FP enabled */
536  __MIPS_FPU_REGISTER_TYPE f18;   /* 56 -- saved if FP enabled */
537  __MIPS_FPU_REGISTER_TYPE f19;   /* 57 -- saved if FP enabled */
538  __MIPS_FPU_REGISTER_TYPE f20;   /* 58 -- saved if FP enabled */
539  __MIPS_FPU_REGISTER_TYPE f21;   /* 59 -- saved if FP enabled */
540  __MIPS_FPU_REGISTER_TYPE f22;   /* 60 -- saved if FP enabled */
541  __MIPS_FPU_REGISTER_TYPE f23;   /* 61 -- saved if FP enabled */
542  __MIPS_FPU_REGISTER_TYPE f24;   /* 62 -- saved if FP enabled */
543  __MIPS_FPU_REGISTER_TYPE f25;   /* 63 -- saved if FP enabled */
544  __MIPS_FPU_REGISTER_TYPE f26;   /* 64 -- saved if FP enabled */
545  __MIPS_FPU_REGISTER_TYPE f27;   /* 65 -- saved if FP enabled */
546  __MIPS_FPU_REGISTER_TYPE f28;   /* 66 -- saved if FP enabled */
547  __MIPS_FPU_REGISTER_TYPE f29;   /* 67 -- saved if FP enabled */
548  __MIPS_FPU_REGISTER_TYPE f30;   /* 68 -- saved if FP enabled */
549  __MIPS_FPU_REGISTER_TYPE f31;   /* 69 -- saved if FP enabled */
550  __MIPS_REGISTER_TYPE     fcsr;  /* 70 -- saved on exceptions */
551                                  /*    (oddly not documented on MGV) */
552  __MIPS_REGISTER_TYPE     feir;  /* 71 -- saved on exceptions */
553                                  /*    (oddly not documented on MGV) */
554
555  /* GDB does not seem to care about anything past this point */
556
557  __MIPS_REGISTER_TYPE  tlbhi;    /* 72 - NOT FILLED IN, doesn't exist on */
558                                  /*         all MIPS CPUs (at least MGV) */
559#if __mips == 1
560  __MIPS_REGISTER_TYPE  tlblo;    /* 73 - NOT FILLED IN, doesn't exist on */
561                                  /*         all MIPS CPUs (at least MGV) */
562#endif
563#if  (__mips == 3) || (__mips == 32)
564  __MIPS_REGISTER_TYPE  tlblo0;   /* 73 - NOT FILLED IN, doesn't exist on */
565                                  /*         all MIPS CPUs (at least MGV) */
566#endif
567
568  __MIPS_REGISTER_TYPE  inx;      /* 74 -- NOT FILLED IN, doesn't exist on */
569                                  /*         all MIPS CPUs (at least MGV) */
570  __MIPS_REGISTER_TYPE  rand;     /* 75 -- NOT FILLED IN, doesn't exist on */
571                                  /*         all MIPS CPUs (at least MGV) */
572  __MIPS_REGISTER_TYPE  ctxt;     /* 76 -- NOT FILLED IN, doesn't exist on */
573                                  /*         all MIPS CPUs (at least MGV) */
574  __MIPS_REGISTER_TYPE  exctype;  /* 77 -- NOT FILLED IN (not enough info) */
575  __MIPS_REGISTER_TYPE  mode;     /* 78 -- NOT FILLED IN (not enough info) */
576  __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
577  __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
578  /* end of __mips == 1 so NREGS == 81 */
579#if  (__mips == 3) || (__mips == 32)
580  __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
581  __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
582  __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
583  __MIPS_REGISTER_TYPE  count;    /* 84 -- NOT FILLED IN */
584  __MIPS_REGISTER_TYPE  compare;  /* 85 -- NOT FILLED IN */
585  __MIPS_REGISTER_TYPE  config;   /* 86 -- NOT FILLED IN */
586  __MIPS_REGISTER_TYPE  lladdr;   /* 87 -- NOT FILLED IN */
587  __MIPS_REGISTER_TYPE  watchlo;  /* 88 -- NOT FILLED IN */
588  __MIPS_REGISTER_TYPE  watchhi;  /* 89 -- NOT FILLED IN */
589  __MIPS_REGISTER_TYPE  ecc;      /* 90 -- NOT FILLED IN */
590  __MIPS_REGISTER_TYPE  cacheerr; /* 91 -- NOT FILLED IN */
591  __MIPS_REGISTER_TYPE  taglo;    /* 92 -- NOT FILLED IN */
592  __MIPS_REGISTER_TYPE  taghi;    /* 93 -- NOT FILLED IN */
593  __MIPS_REGISTER_TYPE  errpc;    /* 94 -- NOT FILLED IN */
594  __MIPS_REGISTER_TYPE  xctxt;    /* 95 -- NOT FILLED IN */
595 /* end of __mips == 3 so NREGS == 96 */
596#endif
597
598} CPU_Interrupt_frame;
599
600/*
601 *  This variable is optional.  It is used on CPUs on which it is difficult
602 *  to generate an "uninitialized" FP context.  It is filled in by
603 *  _CPU_Initialize and copied into the task's FP context area during
604 *  _CPU_Context_Initialize.
605 */
606
607SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
608
609/*
610 *  Nothing prevents the porter from declaring more CPU specific variables.
611 */
612
613/* XXX: if needed, put more variables here */
614
615/*
616 *  The size of the floating point context area.  On some CPUs this
617 *  will not be a "sizeof" because the format of the floating point
618 *  area is not defined -- only the size is.  This is usually on
619 *  CPUs with a "floating point save context" instruction.
620 */
621
622#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
623
624/*
625 *  Amount of extra stack (above minimum stack size) required by
626 *  system initialization thread.  Remember that in a multiprocessor
627 *  system the system intialization thread becomes the MP server thread.
628 */
629
630#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
631
632/*
633 *  This defines the number of entries in the ISR_Vector_table managed
634 *  by RTEMS.
635 */
636
637extern unsigned int mips_interrupt_number_of_vectors;
638#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (mips_interrupt_number_of_vectors)
639#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
640
641/*
642 *  Should be large enough to run all RTEMS tests.  This ensures
643 *  that a "reasonable" small application should not have any problems.
644 */
645
646#define CPU_STACK_MINIMUM_SIZE          (8 * 1024)
647
648/*
649 *  CPU's worst alignment requirement for data types on a byte boundary.  This
650 *  alignment does not take into account the requirements for the stack.
651 */
652
653#define CPU_ALIGNMENT              8
654
655/*
656 *  This number corresponds to the byte alignment requirement for the
657 *  heap handler.  This alignment requirement may be stricter than that
658 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
659 *  common for the heap to follow the same alignment requirement as
660 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
661 *  then this should be set to CPU_ALIGNMENT.
662 *
663 *  NOTE:  This does not have to be a power of 2.  It does have to
664 *         be greater or equal to than CPU_ALIGNMENT.
665 */
666
667#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
668
669/*
670 *  This number corresponds to the byte alignment requirement for memory
671 *  buffers allocated by the partition manager.  This alignment requirement
672 *  may be stricter than that for the data types alignment specified by
673 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
674 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
675 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
676 *
677 *  NOTE:  This does not have to be a power of 2.  It does have to
678 *         be greater or equal to than CPU_ALIGNMENT.
679 */
680
681#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
682
683/*
684 *  This number corresponds to the byte alignment requirement for the
685 *  stack.  This alignment requirement may be stricter than that for the
686 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
687 *  is strict enough for the stack, then this should be set to 0.
688 *
689 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
690 */
691
692#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
693
694/*
695 *  ISR handler macros
696 */
697
698/*
699 *  Support routine to initialize the RTEMS vector table after it is allocated.
700 */
701
702#define _CPU_Initialize_vectors()
703
704/*
705 *  Declare the function that is present in the shared libcpu directory,
706 *  that returns the processor dependent interrupt mask.
707 */
708
709uint32_t mips_interrupt_mask( void );
710
711/*
712 *  Disable all interrupts for an RTEMS critical section.  The previous
713 *  level is returned in _level.
714 */
715
716#define _CPU_ISR_Disable( _level ) \
717  do { \
718    unsigned int _scratch; \
719    mips_get_sr( _scratch ); \
720    mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
721    _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
722  } while(0)
723
724/*
725 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
726 *  This indicates the end of an RTEMS critical section.  The parameter
727 *  _level is not modified.
728 */
729
730#define _CPU_ISR_Enable( _level )  \
731  do { \
732    unsigned int _scratch; \
733    mips_get_sr( _scratch ); \
734    mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
735  } while(0)
736
737/*
738 *  This temporarily restores the interrupt to _level before immediately
739 *  disabling them again.  This is used to divide long RTEMS critical
740 *  sections into two or more parts.  The parameter _level is not
741 *  modified.
742 */
743
744#define _CPU_ISR_Flash( _xlevel ) \
745  do { \
746    unsigned int _scratch2 = _xlevel; \
747    _CPU_ISR_Enable( _scratch2 ); \
748    _CPU_ISR_Disable( _scratch2 ); \
749    _xlevel = _scratch2; \
750  } while(0)
751
752/*
753 *  Map interrupt level in task mode onto the hardware that the CPU
754 *  actually provides.  Currently, interrupt levels which do not
755 *  map onto the CPU in a generic fashion are undefined.  Someday,
756 *  it would be nice if these were "mapped" by the application
757 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
758 *  8 - 255 would be available for bsp/application specific meaning.
759 *  This could be used to manage a programmable interrupt controller
760 *  via the rtems_task_mode directive.
761 *
762 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
763 *  manipulates the IEC.
764 */
765
766uint32_t   _CPU_ISR_Get_level( void );  /* in cpu.c */
767
768void _CPU_ISR_Set_level( uint32_t   );  /* in cpu.c */
769
770/* end of ISR handler macros */
771
772/* Context handler macros */
773
774/*
775 *  Initialize the context to a state suitable for starting a
776 *  task after a context restore operation.  Generally, this
777 *  involves:
778 *
779 *     - setting a starting address
780 *     - preparing the stack
781 *     - preparing the stack and frame pointers
782 *     - setting the proper interrupt level in the context
783 *     - initializing the floating point context
784 *
785 *  This routine generally does not set any unnecessary register
786 *  in the context.  The state of the "general data" registers is
787 *  undefined at task start time.
788 *
789 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
790 *        point thread.  This is typically only used on CPUs where the
791 *        FPU may be easily disabled by software such as on the SPARC
792 *        where the PSR contains an enable FPU bit.
793 *
794 *  The per-thread status register holds the interrupt enable, FP enable
795 *  and global interrupt enable for that thread.  It means each thread can
796 *  enable its own set of interrupts.  If interrupts are disabled, RTEMS
797 *  can still dispatch via blocking calls.  This is the function of the
798 *  "Interrupt Level", and on the MIPS, it controls the IEC bit and all
799 *  the hardware interrupts as defined in the SR.  Software ints
800 *  are automatically enabled for all threads, as they will only occur under
801 *  program control anyhow.  Besides, the interrupt level parm is only 8 bits,
802 *  and controlling the software ints plus the others would require 9.
803 *
804 *  If the Interrupt Level is 0, all ints are on.  Otherwise, the
805 *  Interrupt Level should supply a bit pattern to impose on the SR
806 *  interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6
807 *  apply to the SR register Intr bits from bit 10 thru bit 15.  Bit 7 of
808 *  the Interrupt Level parameter is unused at this time.
809 *
810 *  These are the only per-thread SR bits, the others are maintained
811 *  globally & explicitly preserved by the Context Switch code in cpu_asm.s
812 */
813
814
815#if (__mips == 3) || (__mips == 32)
816#define _INTON          SR_IE
817#if __mips_fpr==64
818#define _EXTRABITS      SR_FR
819#else
820#define _EXTRABITS      0
821#endif /* __mips_fpr==64 */
822#endif /* __mips == 3 */
823#if __mips == 1
824#define _INTON          SR_IEC
825#define _EXTRABITS      0  /* make sure we're in user mode on MIPS1 processors */
826#endif /* __mips == 1 */
827
828
829void _CPU_Context_Initialize(
830  Context_Control  *the_context,
831  uintptr_t        *stack_base,
832  uint32_t          size,
833  uint32_t          new_level,
834  void             *entry_point,
835  bool              is_fp
836);
837
838
839/*
840 *  This routine is responsible for somehow restarting the currently
841 *  executing task.  If you are lucky, then all that is necessary
842 *  is restoring the context.  Otherwise, there will need to be
843 *  a special assembly routine which does something special in this
844 *  case.  Context_Restore should work most of the time.  It will
845 *  not work if restarting self conflicts with the stack frame
846 *  assumptions of restoring a context.
847 */
848
849#define _CPU_Context_Restart_self( _the_context ) \
850   _CPU_Context_restore( (_the_context) );
851
852/*
853 *  The purpose of this macro is to allow the initial pointer into
854 *  A floating point context area (used to save the floating point
855 *  context) to be at an arbitrary place in the floating point
856 *  context area.
857 *
858 *  This is necessary because some FP units are designed to have
859 *  their context saved as a stack which grows into lower addresses.
860 *  Other FP units can be saved by simply moving registers into offsets
861 *  from the base of the context area.  Finally some FP units provide
862 *  a "dump context" instruction which could fill in from high to low
863 *  or low to high based on the whim of the CPU designers.
864 */
865
866#define _CPU_Context_Fp_start( _base, _offset ) \
867   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
868
869/*
870 *  This routine initializes the FP context area passed to it to.
871 *  There are a few standard ways in which to initialize the
872 *  floating point context.  The code included for this macro assumes
873 *  that this is a CPU in which a "initial" FP context was saved into
874 *  _CPU_Null_fp_context and it simply copies it to the destination
875 *  context passed to it.
876 *
877 *  Other models include (1) not doing anything, and (2) putting
878 *  a "null FP status word" in the correct place in the FP context.
879 */
880
881#if ( CPU_HARDWARE_FP == TRUE )
882#define _CPU_Context_Initialize_fp( _destination ) \
883  { \
884   *(*(_destination)) = _CPU_Null_fp_context; \
885  }
886#endif
887
888/* end of Context handler macros */
889
890/* Fatal Error manager macros */
891
892/*
893 *  This routine copies _error into a known place -- typically a stack
894 *  location or a register, optionally disables interrupts, and
895 *  halts/stops the CPU.
896 */
897
898#define _CPU_Fatal_halt( _error ) \
899  do { \
900    unsigned int _level; \
901    _CPU_ISR_Disable(_level); \
902    loop: goto loop; \
903  } while (0)
904
905
906extern void mips_break( int error );
907
908/* Bitfield handler macros */
909
910/*
911 *  This routine sets _output to the bit number of the first bit
912 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Control.
913 *  This type may be either 16 or 32 bits wide although only the 16
914 *  least significant bits will be used.
915 *
916 *  There are a number of variables in using a "find first bit" type
917 *  instruction.
918 *
919 *    (1) What happens when run on a value of zero?
920 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
921 *    (3) The numbering may be zero or one based.
922 *    (4) The "find first bit" instruction may search from MSB or LSB.
923 *
924 *  RTEMS guarantees that (1) will never happen so it is not a concern.
925 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
926 *  _CPU_Priority_bits_index().  These three form a set of routines
927 *  which must logically operate together.  Bits in the _value are
928 *  set and cleared based on masks built by _CPU_Priority_mask().
929 *  The basic major and minor values calculated by _Priority_Major()
930 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
931 *  to properly range between the values returned by the "find first bit"
932 *  instruction.  This makes it possible for _Priority_Get_highest() to
933 *  calculate the major and directly index into the minor table.
934 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
935 *  is the first bit found.
936 *
937 *  This entire "find first bit" and mapping process depends heavily
938 *  on the manner in which a priority is broken into a major and minor
939 *  components with the major being the 4 MSB of a priority and minor
940 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
941 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
942 *  to the lowest priority.
943 *
944 *  If your CPU does not have a "find first bit" instruction, then
945 *  there are ways to make do without it.  Here are a handful of ways
946 *  to implement this in software:
947 *
948 *    - a series of 16 bit test instructions
949 *    - a "binary search using if's"
950 *    - _number = 0
951 *      if _value > 0x00ff
952 *        _value >>=8
953 *        _number = 8;
954 *
955 *      if _value > 0x0000f
956 *        _value >=8
957 *        _number += 4
958 *
959 *      _number += bit_set_table[ _value ]
960 *
961 *    where bit_set_table[ 16 ] has values which indicate the first
962 *      bit set
963 */
964
965#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
966#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
967
968#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
969
970#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
971  { \
972    (_output) = 0;   /* do something to prevent warnings */ \
973  }
974
975#endif
976
977/* end of Bitfield handler macros */
978
979/*
980 *  This routine builds the mask which corresponds to the bit fields
981 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
982 *  for that routine.
983 */
984
985#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
986
987#define _CPU_Priority_Mask( _bit_number ) \
988  ( 1 << (_bit_number) )
989
990#endif
991
992/*
993 *  This routine translates the bit numbers returned by
994 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
995 *  a major or minor component of a priority.  See the discussion
996 *  for that routine.
997 */
998
999#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1000
1001#define _CPU_Priority_bits_index( _priority ) \
1002  (_priority)
1003
1004#endif
1005
1006/* end of Priority handler macros */
1007
1008/* functions */
1009
1010/*
1011 *  _CPU_Initialize
1012 *
1013 *  This routine performs CPU dependent initialization.
1014 */
1015
1016void _CPU_Initialize(void);
1017
1018/*
1019 *  _CPU_ISR_install_raw_handler
1020 *
1021 *  This routine installs a "raw" interrupt handler directly into the
1022 *  processor's vector table.
1023 */
1024
1025void _CPU_ISR_install_raw_handler(
1026  uint32_t    vector,
1027  proc_ptr    new_handler,
1028  proc_ptr   *old_handler
1029);
1030
1031/*
1032 *  _CPU_ISR_install_vector
1033 *
1034 *  This routine installs an interrupt vector.
1035 */
1036
1037void _CPU_ISR_install_vector(
1038  uint32_t    vector,
1039  proc_ptr    new_handler,
1040  proc_ptr   *old_handler
1041);
1042
1043/*
1044 *  _CPU_Install_interrupt_stack
1045 *
1046 *  This routine installs the hardware interrupt stack pointer.
1047 *
1048 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1049 *         is TRUE.
1050 */
1051
1052void _CPU_Install_interrupt_stack( void );
1053
1054/*
1055 *  _CPU_Internal_threads_Idle_thread_body
1056 *
1057 *  This routine is the CPU dependent IDLE thread body.
1058 *
1059 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1060 *         is TRUE.
1061 */
1062
1063void *_CPU_Thread_Idle_body( uintptr_t ignored );
1064
1065/*
1066 *  _CPU_Context_switch
1067 *
1068 *  This routine switches from the run context to the heir context.
1069 */
1070
1071void _CPU_Context_switch(
1072  Context_Control  *run,
1073  Context_Control  *heir
1074);
1075
1076/*
1077 *  _CPU_Context_restore
1078 *
1079 *  This routine is generally used only to restart self in an
1080 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1081 *
1082 *  NOTE: May be unnecessary to reload some registers.
1083 */
1084
1085void _CPU_Context_restore(
1086  Context_Control *new_context
1087);
1088
1089/*
1090 *  _CPU_Context_save_fp
1091 *
1092 *  This routine saves the floating point context passed to it.
1093 */
1094
1095void _CPU_Context_save_fp(
1096  Context_Control_fp **fp_context_ptr
1097);
1098
1099/*
1100 *  _CPU_Context_restore_fp
1101 *
1102 *  This routine restores the floating point context passed to it.
1103 */
1104
1105void _CPU_Context_restore_fp(
1106  Context_Control_fp **fp_context_ptr
1107);
1108
1109/*  The following routine swaps the endian format of an unsigned int.
1110 *  It must be static because it is referenced indirectly.
1111 *
1112 *  This version will work on any processor, but if there is a better
1113 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1114 *
1115 *     swap least significant two bytes with 16-bit rotate
1116 *     swap upper and lower 16-bits
1117 *     swap most significant two bytes with 16-bit rotate
1118 *
1119 *  Some CPUs have special instructions which swap a 32-bit quantity in
1120 *  a single instruction (e.g. i486).  It is probably best to avoid
1121 *  an "endian swapping control bit" in the CPU.  One good reason is
1122 *  that interrupts would probably have to be disabled to ensure that
1123 *  an interrupt does not try to access the same "chunk" with the wrong
1124 *  endian.  Another good reason is that on some CPUs, the endian bit
1125 *  endianness for ALL fetches -- both code and data -- so the code
1126 *  will be fetched incorrectly.
1127 */
1128
1129static inline uint32_t CPU_swap_u32(
1130  uint32_t value
1131)
1132{
1133  uint32_t   byte1, byte2, byte3, byte4, swapped;
1134
1135  byte4 = (value >> 24) & 0xff;
1136  byte3 = (value >> 16) & 0xff;
1137  byte2 = (value >> 8)  & 0xff;
1138  byte1 =  value        & 0xff;
1139
1140  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1141  return( swapped );
1142}
1143
1144#define CPU_swap_u16( value ) \
1145  (((value&0xff) << 8) | ((value >> 8)&0xff))
1146
1147
1148#endif
1149
1150
1151
1152#ifdef __cplusplus
1153}
1154#endif
1155
1156#endif
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