source: rtems/cpukit/score/cpu/mips/rtems/score/cpu.h @ 3e5ff08

4.11
Last change on this file since 3e5ff08 was 3e5ff08, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 11, 2012 at 5:30:06 PM

mips/cpu.h: Define CPU_SIMPLE_VECTORED_INTERRUPTS and remove _CPU_ISR_Initialize

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1/**
2 *  @file
3 * 
4 *  Mips CPU Dependent Header File
5 *
6 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
7 *           Joel Sherrill <joel@OARcorp.com>.
8 *
9 *    These changes made the code conditional on standard cpp predefines,
10 *    merged the mips1 and mips3 code sequences as much as possible,
11 *    and moved some of the assembly code to C.  Alan did much of the
12 *    initial analysis and rework.  Joel took over from there and
13 *    wrote the JMR3904 BSP so this could be tested.  Joel also
14 *    added the new interrupt vectoring support in libcpu and
15 *    tried to better support the various interrupt controllers.
16 *
17 */
18
19/*
20 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
21 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
22 *
23 *    To anyone who acknowledges that this file is provided "AS IS"
24 *    without any express or implied warranty:
25 *      permission to use, copy, modify, and distribute this file
26 *      for any purpose is hereby granted without fee, provided that
27 *      the above copyright notice and this notice appears in all
28 *      copies, and that the name of Transition Networks not be used in
29 *      advertising or publicity pertaining to distribution of the
30 *      software without specific, written prior permission.
31 *      Transition Networks makes no representations about the suitability
32 *      of this software for any purpose.
33 *
34 *  COPYRIGHT (c) 1989-2012.
35 *  On-Line Applications Research Corporation (OAR).
36 *
37 *  The license and distribution terms for this file may be
38 *  found in the file LICENSE in this distribution or at
39 *  http://www.rtems.com/license/LICENSE.
40 */
41
42#ifndef _RTEMS_SCORE_CPU_H
43#define _RTEMS_SCORE_CPU_H
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49#include <rtems/score/types.h>
50#include <rtems/score/mips.h>
51
52/* conditional compilation parameters */
53
54/*
55 *  Should the calls to _Thread_Enable_dispatch be inlined?
56 *
57 *  If TRUE, then they are inlined.
58 *  If FALSE, then a subroutine call is made.
59 *
60 *  Basically this is an example of the classic trade-off of size
61 *  versus speed.  Inlining the call (TRUE) typically increases the
62 *  size of RTEMS while speeding up the enabling of dispatching.
63 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
64 *  only be 0 or 1 unless you are in an interrupt handler and that
65 *  interrupt handler invokes the executive.]  When not inlined
66 *  something calls _Thread_Enable_dispatch which in turns calls
67 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
68 *  one subroutine call is avoided entirely.]
69 */
70
71#define CPU_INLINE_ENABLE_DISPATCH       FALSE
72
73/*
74 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
75 *  be unrolled one time?  In unrolled each iteration of the loop examines
76 *  two "nodes" on the chain being searched.  Otherwise, only one node
77 *  is examined per iteration.
78 *
79 *  If TRUE, then the loops are unrolled.
80 *  If FALSE, then the loops are not unrolled.
81 *
82 *  The primary factor in making this decision is the cost of disabling
83 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
84 *  body of the loop.  On some CPUs, the flash is more expensive than
85 *  one iteration of the loop body.  In this case, it might be desirable
86 *  to unroll the loop.  It is important to note that on some CPUs, this
87 *  code is the longest interrupt disable period in RTEMS.  So it is
88 *  necessary to strike a balance when setting this parameter.
89 */
90
91#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
92
93/*
94 *  Does RTEMS manage a dedicated interrupt stack in software?
95 *
96 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
97 *  If FALSE, nothing is done.
98 *
99 *  If the CPU supports a dedicated interrupt stack in hardware,
100 *  then it is generally the responsibility of the BSP to allocate it
101 *  and set it up.
102 *
103 *  If the CPU does not support a dedicated interrupt stack, then
104 *  the porter has two options: (1) execute interrupts on the
105 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
106 *  interrupt stack.
107 *
108 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
109 *
110 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
111 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
112 *  possible that both are FALSE for a particular CPU.  Although it
113 *  is unclear what that would imply about the interrupt processing
114 *  procedure on that CPU.
115 */
116
117#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
118
119/*
120 *  Does the CPU follow the simple vectored interrupt model?
121 *
122 *  If TRUE, then RTEMS allocates the vector table it internally manages.
123 *  If FALSE, then the BSP is assumed to allocate and manage the vector
124 *  table
125 *
126 *  MIPS Specific Information:
127 *
128 *  Up to and including RTEMS 4.10, the MIPS port used simple vectored
129 *  interrupts. But this was changed to the PIC model after 4.10.
130 */
131#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
132
133/*
134 *  Does this CPU have hardware support for a dedicated interrupt stack?
135 *
136 *  If TRUE, then it must be installed during initialization.
137 *  If FALSE, then no installation is performed.
138 *
139 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
140 *
141 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
142 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
143 *  possible that both are FALSE for a particular CPU.  Although it
144 *  is unclear what that would imply about the interrupt processing
145 *  procedure on that CPU.
146 */
147
148#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
149
150/*
151 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
152 *
153 *  If TRUE, then the memory is allocated during initialization.
154 *  If FALSE, then the memory is allocated during initialization.
155 *
156 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
157 */
158
159#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
160
161/*
162 *  Does the RTEMS invoke the user's ISR with the vector number and
163 *  a pointer to the saved interrupt frame (1) or just the vector
164 *  number (0)?
165 *
166 */
167
168#define CPU_ISR_PASSES_FRAME_POINTER 1
169
170
171
172/*
173 *  Does the CPU have hardware floating point?
174 *
175 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
176 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
177 *
178 *  If there is a FP coprocessor such as the i387 or mc68881, then
179 *  the answer is TRUE.
180 *
181 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
182 *  It indicates whether or not this CPU model has FP support.  For
183 *  example, it would be possible to have an i386_nofp CPU model
184 *  which set this to false to indicate that you have an i386 without
185 *  an i387 and wish to leave floating point support out of RTEMS.
186 */
187
188#if ( MIPS_HAS_FPU == 1 )
189#define CPU_HARDWARE_FP     TRUE
190#else
191#define CPU_HARDWARE_FP     FALSE
192#endif
193
194/*
195 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
196 *
197 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
198 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
199 *
200 *  So far, the only CPU in which this option has been used is the
201 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
202 *  floating point registers to perform integer multiplies.  If
203 *  a function which you would not think utilize the FP unit DOES,
204 *  then one can not easily predict which tasks will use the FP hardware.
205 *  In this case, this option should be TRUE.
206 *
207 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
208 *
209 *  Mips Note: It appears the GCC can implicitly generate FPU
210 *  and Altivec instructions when you least expect them.  So make
211 *  all tasks floating point.
212 */
213
214#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
215
216/*
217 *  Should the IDLE task have a floating point context?
218 *
219 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
220 *  and it has a floating point context which is switched in and out.
221 *  If FALSE, then the IDLE task does not have a floating point context.
222 *
223 *  Setting this to TRUE negatively impacts the time required to preempt
224 *  the IDLE task from an interrupt because the floating point context
225 *  must be saved as part of the preemption.
226 */
227
228#define CPU_IDLE_TASK_IS_FP      FALSE
229
230/*
231 *  Should the saving of the floating point registers be deferred
232 *  until a context switch is made to another different floating point
233 *  task?
234 *
235 *  If TRUE, then the floating point context will not be stored until
236 *  necessary.  It will remain in the floating point registers and not
237 *  disturned until another floating point task is switched to.
238 *
239 *  If FALSE, then the floating point context is saved when a floating
240 *  point task is switched out and restored when the next floating point
241 *  task is restored.  The state of the floating point registers between
242 *  those two operations is not specified.
243 *
244 *  If the floating point context does NOT have to be saved as part of
245 *  interrupt dispatching, then it should be safe to set this to TRUE.
246 *
247 *  Setting this flag to TRUE results in using a different algorithm
248 *  for deciding when to save and restore the floating point context.
249 *  The deferred FP switch algorithm minimizes the number of times
250 *  the FP context is saved and restored.  The FP context is not saved
251 *  until a context switch is made to another, different FP task.
252 *  Thus in a system with only one FP task, the FP context will never
253 *  be saved or restored.
254 */
255
256#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
257
258/*
259 *  Does this port provide a CPU dependent IDLE task implementation?
260 *
261 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
262 *  must be provided and is the default IDLE thread body instead of
263 *  _Internal_threads_Idle_thread_body.
264 *
265 *  If FALSE, then use the generic IDLE thread body if the BSP does
266 *  not provide one.
267 *
268 *  This is intended to allow for supporting processors which have
269 *  a low power or idle mode.  When the IDLE thread is executed, then
270 *  the CPU can be powered down.
271 *
272 *  The order of precedence for selecting the IDLE thread body is:
273 *
274 *    1.  BSP provided
275 *    2.  CPU dependent (if provided)
276 *    3.  generic (if no BSP and no CPU dependent)
277 */
278
279/* we can use the low power wait instruction for the IDLE thread */
280#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
281
282/*
283 *  Does the stack grow up (toward higher addresses) or down
284 *  (toward lower addresses)?
285 *
286 *  If TRUE, then the grows upward.
287 *  If FALSE, then the grows toward smaller addresses.
288 */
289
290/* our stack grows down */
291#define CPU_STACK_GROWS_UP               FALSE
292
293/*
294 *  The following is the variable attribute used to force alignment
295 *  of critical RTEMS structures.  On some processors it may make
296 *  sense to have these aligned on tighter boundaries than
297 *  the minimum requirements of the compiler in order to have as
298 *  much of the critical data area as possible in a cache line.
299 *
300 *  The placement of this macro in the declaration of the variables
301 *  is based on the syntactically requirements of the GNU C
302 *  "__attribute__" extension.  For example with GNU C, use
303 *  the following to force a structures to a 32 byte boundary.
304 *
305 *      __attribute__ ((aligned (32)))
306 *
307 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
308 *         To benefit from using this, the data must be heavily
309 *         used so it will stay in the cache and used frequently enough
310 *         in the executive to justify turning this on.
311 */
312
313/* our cache line size is 16 bytes */
314#if __GNUC__
315#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
316#else
317#define CPU_STRUCTURE_ALIGNMENT
318#endif
319
320#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
321
322/*
323 *  Define what is required to specify how the network to host conversion
324 *  routines are handled.
325 */
326
327/* __MIPSEB__ or __MIPSEL__ is defined by GCC based on -EB or -EL command line options */
328#if defined(__MIPSEB__)
329#define CPU_BIG_ENDIAN                           TRUE
330#define CPU_LITTLE_ENDIAN                        FALSE
331#elif defined(__MIPSEL__)
332#define CPU_BIG_ENDIAN                           FALSE
333#define CPU_LITTLE_ENDIAN                        TRUE
334#else
335#error "Unknown endianness"
336#endif
337
338/*
339 *  The following defines the number of bits actually used in the
340 *  interrupt field of the task mode.  How those bits map to the
341 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
342 */
343
344#define CPU_MODES_INTERRUPT_MASK   0x000000ff
345
346/*
347 *  Processor defined structures
348 *
349 *  Examples structures include the descriptor tables from the i386
350 *  and the processor control structure on the i960ca.
351 */
352
353/* may need to put some structures here.  */
354
355/*
356 * Contexts
357 *
358 *  Generally there are 2 types of context to save.
359 *     1. Interrupt registers to save
360 *     2. Task level registers to save
361 *
362 *  This means we have the following 3 context items:
363 *     1. task level context stuff::  Context_Control
364 *     2. floating point task stuff:: Context_Control_fp
365 *     3. special interrupt level context :: Context_Control_interrupt
366 *
367 *  On some processors, it is cost-effective to save only the callee
368 *  preserved registers during a task context switch.  This means
369 *  that the ISR code needs to save those registers which do not
370 *  persist across function calls.  It is not mandatory to make this
371 *  distinctions between the caller/callee saves registers for the
372 *  purpose of minimizing context saved during task switch and on interrupts.
373 *  If the cost of saving extra registers is minimal, simplicity is the
374 *  choice.  Save the same context on interrupt entry as for tasks in
375 *  this case.
376 *
377 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
378 *  care should be used in designing the context area.
379 *
380 *  On some CPUs with hardware floating point support, the Context_Control_fp
381 *  structure will not be used or it simply consist of an array of a
382 *  fixed number of bytes.   This is done when the floating point context
383 *  is dumped by a "FP save context" type instruction and the format
384 *  is not really defined by the CPU.  In this case, there is no need
385 *  to figure out the exact format -- only the size.  Of course, although
386 *  this is enough information for RTEMS, it is probably not enough for
387 *  a debugger such as gdb.  But that is another problem.
388 */
389
390#ifndef ASM
391
392/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
393#if (__mips == 1) || (__mips == 32)
394#define __MIPS_REGISTER_TYPE     uint32_t
395#define __MIPS_FPU_REGISTER_TYPE uint32_t
396#elif __mips == 3
397#define __MIPS_REGISTER_TYPE     uint64_t
398#define __MIPS_FPU_REGISTER_TYPE uint64_t
399#else
400#error "mips register size: unknown architecture level!!"
401#endif
402typedef struct {
403    __MIPS_REGISTER_TYPE s0;
404    __MIPS_REGISTER_TYPE s1;
405    __MIPS_REGISTER_TYPE s2;
406    __MIPS_REGISTER_TYPE s3;
407    __MIPS_REGISTER_TYPE s4;
408    __MIPS_REGISTER_TYPE s5;
409    __MIPS_REGISTER_TYPE s6;
410    __MIPS_REGISTER_TYPE s7;
411    __MIPS_REGISTER_TYPE sp;
412    __MIPS_REGISTER_TYPE fp;
413    __MIPS_REGISTER_TYPE ra;
414    __MIPS_REGISTER_TYPE c0_sr;
415    __MIPS_REGISTER_TYPE c0_epc;
416} Context_Control;
417
418#define _CPU_Context_Get_SP( _context ) \
419  (uintptr_t) (_context)->sp
420
421/* WARNING: If this structure is modified, the constants in cpu.h
422 *          must also be updated.
423 */
424
425typedef struct {
426#if ( CPU_HARDWARE_FP == TRUE )
427    __MIPS_FPU_REGISTER_TYPE fp0;
428    __MIPS_FPU_REGISTER_TYPE fp1;
429    __MIPS_FPU_REGISTER_TYPE fp2;
430    __MIPS_FPU_REGISTER_TYPE fp3;
431    __MIPS_FPU_REGISTER_TYPE fp4;
432    __MIPS_FPU_REGISTER_TYPE fp5;
433    __MIPS_FPU_REGISTER_TYPE fp6;
434    __MIPS_FPU_REGISTER_TYPE fp7;
435    __MIPS_FPU_REGISTER_TYPE fp8;
436    __MIPS_FPU_REGISTER_TYPE fp9;
437    __MIPS_FPU_REGISTER_TYPE fp10;
438    __MIPS_FPU_REGISTER_TYPE fp11;
439    __MIPS_FPU_REGISTER_TYPE fp12;
440    __MIPS_FPU_REGISTER_TYPE fp13;
441    __MIPS_FPU_REGISTER_TYPE fp14;
442    __MIPS_FPU_REGISTER_TYPE fp15;
443    __MIPS_FPU_REGISTER_TYPE fp16;
444    __MIPS_FPU_REGISTER_TYPE fp17;
445    __MIPS_FPU_REGISTER_TYPE fp18;
446    __MIPS_FPU_REGISTER_TYPE fp19;
447    __MIPS_FPU_REGISTER_TYPE fp20;
448    __MIPS_FPU_REGISTER_TYPE fp21;
449    __MIPS_FPU_REGISTER_TYPE fp22;
450    __MIPS_FPU_REGISTER_TYPE fp23;
451    __MIPS_FPU_REGISTER_TYPE fp24;
452    __MIPS_FPU_REGISTER_TYPE fp25;
453    __MIPS_FPU_REGISTER_TYPE fp26;
454    __MIPS_FPU_REGISTER_TYPE fp27;
455    __MIPS_FPU_REGISTER_TYPE fp28;
456    __MIPS_FPU_REGISTER_TYPE fp29;
457    __MIPS_FPU_REGISTER_TYPE fp30;
458    __MIPS_FPU_REGISTER_TYPE fp31;
459    uint32_t fpcs;
460#endif
461} Context_Control_fp;
462
463/*
464 *  This struct reflects the stack frame employed in ISR_Handler.  Note
465 *  that the ISR routine save some of the registers to this frame for
466 *  all interrupts and exceptions.  Other registers are saved only on
467 *  exceptions, while others are not touched at all.  The untouched
468 *  registers are not normally disturbed by high-level language
469 *  programs so they can be accessed when required.
470 *
471 *  The registers and their ordering in this struct must directly
472 *  correspond to the layout and ordering of * shown in iregdef.h,
473 *  as cpu_asm.S uses those definitions to fill the stack frame.
474 *  This struct provides access to the stack frame for C code.
475 *
476 *  Similarly, this structure is used by debugger stubs and exception
477 *  processing routines so be careful when changing the format.
478 *
479 *  NOTE: The comments with this structure and cpu_asm.S should be kept
480 *        in sync.  When in doubt, look in the  code to see if the
481 *        registers you're interested in are actually treated as expected.
482 *        The order of the first portion of this structure follows the
483 *        order of registers expected by gdb.
484 */
485
486typedef struct
487{
488  __MIPS_REGISTER_TYPE  r0;       /*  0 -- NOT FILLED IN */
489  __MIPS_REGISTER_TYPE  at;       /*  1 -- saved always */
490  __MIPS_REGISTER_TYPE  v0;       /*  2 -- saved always */
491  __MIPS_REGISTER_TYPE  v1;       /*  3 -- saved always */
492  __MIPS_REGISTER_TYPE  a0;       /*  4 -- saved always */
493  __MIPS_REGISTER_TYPE  a1;       /*  5 -- saved always */
494  __MIPS_REGISTER_TYPE  a2;       /*  6 -- saved always */
495  __MIPS_REGISTER_TYPE  a3;       /*  7 -- saved always */
496  __MIPS_REGISTER_TYPE  t0;       /*  8 -- saved always */
497  __MIPS_REGISTER_TYPE  t1;       /*  9 -- saved always */
498  __MIPS_REGISTER_TYPE  t2;       /* 10 -- saved always */
499  __MIPS_REGISTER_TYPE  t3;       /* 11 -- saved always */
500  __MIPS_REGISTER_TYPE  t4;       /* 12 -- saved always */
501  __MIPS_REGISTER_TYPE  t5;       /* 13 -- saved always */
502  __MIPS_REGISTER_TYPE  t6;       /* 14 -- saved always */
503  __MIPS_REGISTER_TYPE  t7;       /* 15 -- saved always */
504  __MIPS_REGISTER_TYPE  s0;       /* 16 -- saved on exceptions */
505  __MIPS_REGISTER_TYPE  s1;       /* 17 -- saved on exceptions */
506  __MIPS_REGISTER_TYPE  s2;       /* 18 -- saved on exceptions */
507  __MIPS_REGISTER_TYPE  s3;       /* 19 -- saved on exceptions */
508  __MIPS_REGISTER_TYPE  s4;       /* 20 -- saved on exceptions */
509  __MIPS_REGISTER_TYPE  s5;       /* 21 -- saved on exceptions */
510  __MIPS_REGISTER_TYPE  s6;       /* 22 -- saved on exceptions */
511  __MIPS_REGISTER_TYPE  s7;       /* 23 -- saved on exceptions */
512  __MIPS_REGISTER_TYPE  t8;       /* 24 -- saved always */
513  __MIPS_REGISTER_TYPE  t9;       /* 25 -- saved always */
514  __MIPS_REGISTER_TYPE  k0;       /* 26 -- NOT FILLED IN, kernel tmp reg */
515  __MIPS_REGISTER_TYPE  k1;       /* 27 -- NOT FILLED IN, kernel tmp reg */
516  __MIPS_REGISTER_TYPE  gp;       /* 28 -- saved always */
517  __MIPS_REGISTER_TYPE  sp;       /* 29 -- saved on exceptions NOT RESTORED */
518  __MIPS_REGISTER_TYPE  fp;       /* 30 -- saved always */
519  __MIPS_REGISTER_TYPE  ra;       /* 31 -- saved always */
520  __MIPS_REGISTER_TYPE  c0_sr;    /* 32 -- saved always, some bits are */
521                                  /*    manipulated per-thread          */
522  __MIPS_REGISTER_TYPE  mdlo;     /* 33 -- saved always */
523  __MIPS_REGISTER_TYPE  mdhi;     /* 34 -- saved always */
524  __MIPS_REGISTER_TYPE  badvaddr; /* 35 -- saved on exceptions, read-only */
525  __MIPS_REGISTER_TYPE  cause;    /* 36 -- saved on exceptions NOT restored */
526  __MIPS_REGISTER_TYPE  epc;      /* 37 -- saved always, read-only register */
527                                  /*        but logically restored */
528  __MIPS_FPU_REGISTER_TYPE f0;    /* 38 -- saved if FP enabled */
529  __MIPS_FPU_REGISTER_TYPE f1;    /* 39 -- saved if FP enabled */
530  __MIPS_FPU_REGISTER_TYPE f2;    /* 40 -- saved if FP enabled */
531  __MIPS_FPU_REGISTER_TYPE f3;    /* 41 -- saved if FP enabled */
532  __MIPS_FPU_REGISTER_TYPE f4;    /* 42 -- saved if FP enabled */
533  __MIPS_FPU_REGISTER_TYPE f5;    /* 43 -- saved if FP enabled */
534  __MIPS_FPU_REGISTER_TYPE f6;    /* 44 -- saved if FP enabled */
535  __MIPS_FPU_REGISTER_TYPE f7;    /* 45 -- saved if FP enabled */
536  __MIPS_FPU_REGISTER_TYPE f8;    /* 46 -- saved if FP enabled */
537  __MIPS_FPU_REGISTER_TYPE f9;    /* 47 -- saved if FP enabled */
538  __MIPS_FPU_REGISTER_TYPE f10;   /* 48 -- saved if FP enabled */
539  __MIPS_FPU_REGISTER_TYPE f11;   /* 49 -- saved if FP enabled */
540  __MIPS_FPU_REGISTER_TYPE f12;   /* 50 -- saved if FP enabled */
541  __MIPS_FPU_REGISTER_TYPE f13;   /* 51 -- saved if FP enabled */
542  __MIPS_FPU_REGISTER_TYPE f14;   /* 52 -- saved if FP enabled */
543  __MIPS_FPU_REGISTER_TYPE f15;   /* 53 -- saved if FP enabled */
544  __MIPS_FPU_REGISTER_TYPE f16;   /* 54 -- saved if FP enabled */
545  __MIPS_FPU_REGISTER_TYPE f17;   /* 55 -- saved if FP enabled */
546  __MIPS_FPU_REGISTER_TYPE f18;   /* 56 -- saved if FP enabled */
547  __MIPS_FPU_REGISTER_TYPE f19;   /* 57 -- saved if FP enabled */
548  __MIPS_FPU_REGISTER_TYPE f20;   /* 58 -- saved if FP enabled */
549  __MIPS_FPU_REGISTER_TYPE f21;   /* 59 -- saved if FP enabled */
550  __MIPS_FPU_REGISTER_TYPE f22;   /* 60 -- saved if FP enabled */
551  __MIPS_FPU_REGISTER_TYPE f23;   /* 61 -- saved if FP enabled */
552  __MIPS_FPU_REGISTER_TYPE f24;   /* 62 -- saved if FP enabled */
553  __MIPS_FPU_REGISTER_TYPE f25;   /* 63 -- saved if FP enabled */
554  __MIPS_FPU_REGISTER_TYPE f26;   /* 64 -- saved if FP enabled */
555  __MIPS_FPU_REGISTER_TYPE f27;   /* 65 -- saved if FP enabled */
556  __MIPS_FPU_REGISTER_TYPE f28;   /* 66 -- saved if FP enabled */
557  __MIPS_FPU_REGISTER_TYPE f29;   /* 67 -- saved if FP enabled */
558  __MIPS_FPU_REGISTER_TYPE f30;   /* 68 -- saved if FP enabled */
559  __MIPS_FPU_REGISTER_TYPE f31;   /* 69 -- saved if FP enabled */
560  __MIPS_REGISTER_TYPE     fcsr;  /* 70 -- saved on exceptions */
561                                  /*    (oddly not documented on MGV) */
562  __MIPS_REGISTER_TYPE     feir;  /* 71 -- saved on exceptions */
563                                  /*    (oddly not documented on MGV) */
564
565  /* GDB does not seem to care about anything past this point */
566
567  __MIPS_REGISTER_TYPE  tlbhi;    /* 72 - NOT FILLED IN, doesn't exist on */
568                                  /*         all MIPS CPUs (at least MGV) */
569#if __mips == 1
570  __MIPS_REGISTER_TYPE  tlblo;    /* 73 - NOT FILLED IN, doesn't exist on */
571                                  /*         all MIPS CPUs (at least MGV) */
572#endif
573#if  (__mips == 3) || (__mips == 32)
574  __MIPS_REGISTER_TYPE  tlblo0;   /* 73 - NOT FILLED IN, doesn't exist on */
575                                  /*         all MIPS CPUs (at least MGV) */
576#endif
577
578  __MIPS_REGISTER_TYPE  inx;      /* 74 -- NOT FILLED IN, doesn't exist on */
579                                  /*         all MIPS CPUs (at least MGV) */
580  __MIPS_REGISTER_TYPE  rand;     /* 75 -- NOT FILLED IN, doesn't exist on */
581                                  /*         all MIPS CPUs (at least MGV) */
582  __MIPS_REGISTER_TYPE  ctxt;     /* 76 -- NOT FILLED IN, doesn't exist on */
583                                  /*         all MIPS CPUs (at least MGV) */
584  __MIPS_REGISTER_TYPE  exctype;  /* 77 -- NOT FILLED IN (not enough info) */
585  __MIPS_REGISTER_TYPE  mode;     /* 78 -- NOT FILLED IN (not enough info) */
586  __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
587  __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
588  /* end of __mips == 1 so NREGS == 81 */
589#if  (__mips == 3) || (__mips == 32)
590  __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
591  __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
592  __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
593  __MIPS_REGISTER_TYPE  count;    /* 84 -- NOT FILLED IN */
594  __MIPS_REGISTER_TYPE  compare;  /* 85 -- NOT FILLED IN */
595  __MIPS_REGISTER_TYPE  config;   /* 86 -- NOT FILLED IN */
596  __MIPS_REGISTER_TYPE  lladdr;   /* 87 -- NOT FILLED IN */
597  __MIPS_REGISTER_TYPE  watchlo;  /* 88 -- NOT FILLED IN */
598  __MIPS_REGISTER_TYPE  watchhi;  /* 89 -- NOT FILLED IN */
599  __MIPS_REGISTER_TYPE  ecc;      /* 90 -- NOT FILLED IN */
600  __MIPS_REGISTER_TYPE  cacheerr; /* 91 -- NOT FILLED IN */
601  __MIPS_REGISTER_TYPE  taglo;    /* 92 -- NOT FILLED IN */
602  __MIPS_REGISTER_TYPE  taghi;    /* 93 -- NOT FILLED IN */
603  __MIPS_REGISTER_TYPE  errpc;    /* 94 -- NOT FILLED IN */
604  __MIPS_REGISTER_TYPE  xctxt;    /* 95 -- NOT FILLED IN */
605 /* end of __mips == 3 so NREGS == 96 */
606#endif
607
608} CPU_Interrupt_frame;
609
610/*
611 *  This variable is optional.  It is used on CPUs on which it is difficult
612 *  to generate an "uninitialized" FP context.  It is filled in by
613 *  _CPU_Initialize and copied into the task's FP context area during
614 *  _CPU_Context_Initialize.
615 */
616
617SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
618
619/*
620 *  Nothing prevents the porter from declaring more CPU specific variables.
621 */
622
623/* XXX: if needed, put more variables here */
624
625/*
626 *  The size of the floating point context area.  On some CPUs this
627 *  will not be a "sizeof" because the format of the floating point
628 *  area is not defined -- only the size is.  This is usually on
629 *  CPUs with a "floating point save context" instruction.
630 */
631
632#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
633
634/*
635 *  Amount of extra stack (above minimum stack size) required by
636 *  system initialization thread.  Remember that in a multiprocessor
637 *  system the system intialization thread becomes the MP server thread.
638 */
639
640#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
641
642/*
643 *  This defines the number of entries in the ISR_Vector_table managed
644 *  by RTEMS.
645 */
646
647extern unsigned int mips_interrupt_number_of_vectors;
648#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (mips_interrupt_number_of_vectors)
649#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
650
651/*
652 *  Should be large enough to run all RTEMS tests.  This ensures
653 *  that a "reasonable" small application should not have any problems.
654 */
655
656#define CPU_STACK_MINIMUM_SIZE          (8 * 1024)
657
658/*
659 *  CPU's worst alignment requirement for data types on a byte boundary.  This
660 *  alignment does not take into account the requirements for the stack.
661 */
662
663#define CPU_ALIGNMENT              8
664
665/*
666 *  This number corresponds to the byte alignment requirement for the
667 *  heap handler.  This alignment requirement may be stricter than that
668 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
669 *  common for the heap to follow the same alignment requirement as
670 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
671 *  then this should be set to CPU_ALIGNMENT.
672 *
673 *  NOTE:  This does not have to be a power of 2.  It does have to
674 *         be greater or equal to than CPU_ALIGNMENT.
675 */
676
677#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
678
679/*
680 *  This number corresponds to the byte alignment requirement for memory
681 *  buffers allocated by the partition manager.  This alignment requirement
682 *  may be stricter than that for the data types alignment specified by
683 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
684 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
685 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
686 *
687 *  NOTE:  This does not have to be a power of 2.  It does have to
688 *         be greater or equal to than CPU_ALIGNMENT.
689 */
690
691#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
692
693/*
694 *  This number corresponds to the byte alignment requirement for the
695 *  stack.  This alignment requirement may be stricter than that for the
696 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
697 *  is strict enough for the stack, then this should be set to 0.
698 *
699 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
700 */
701
702#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
703
704/*
705 *  ISR handler macros
706 */
707
708/*
709 *  Declare the function that is present in the shared libcpu directory,
710 *  that returns the processor dependent interrupt mask.
711 */
712
713uint32_t mips_interrupt_mask( void );
714
715/*
716 *  Disable all interrupts for an RTEMS critical section.  The previous
717 *  level is returned in _level.
718 */
719
720#define _CPU_ISR_Disable( _level ) \
721  do { \
722    unsigned int _scratch; \
723    mips_get_sr( _scratch ); \
724    mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
725    _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
726  } while(0)
727
728/*
729 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
730 *  This indicates the end of an RTEMS critical section.  The parameter
731 *  _level is not modified.
732 */
733
734#define _CPU_ISR_Enable( _level )  \
735  do { \
736    unsigned int _scratch; \
737    mips_get_sr( _scratch ); \
738    mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
739  } while(0)
740
741/*
742 *  This temporarily restores the interrupt to _level before immediately
743 *  disabling them again.  This is used to divide long RTEMS critical
744 *  sections into two or more parts.  The parameter _level is not
745 *  modified.
746 */
747
748#define _CPU_ISR_Flash( _xlevel ) \
749  do { \
750    unsigned int _scratch2 = _xlevel; \
751    _CPU_ISR_Enable( _scratch2 ); \
752    _CPU_ISR_Disable( _scratch2 ); \
753    _xlevel = _scratch2; \
754  } while(0)
755
756/*
757 *  Map interrupt level in task mode onto the hardware that the CPU
758 *  actually provides.  Currently, interrupt levels which do not
759 *  map onto the CPU in a generic fashion are undefined.  Someday,
760 *  it would be nice if these were "mapped" by the application
761 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
762 *  8 - 255 would be available for bsp/application specific meaning.
763 *  This could be used to manage a programmable interrupt controller
764 *  via the rtems_task_mode directive.
765 *
766 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
767 *  manipulates the IEC.
768 */
769
770uint32_t   _CPU_ISR_Get_level( void );  /* in cpu.c */
771
772void _CPU_ISR_Set_level( uint32_t   );  /* in cpu.c */
773
774/* end of ISR handler macros */
775
776/* Context handler macros */
777
778/*
779 *  Initialize the context to a state suitable for starting a
780 *  task after a context restore operation.  Generally, this
781 *  involves:
782 *
783 *     - setting a starting address
784 *     - preparing the stack
785 *     - preparing the stack and frame pointers
786 *     - setting the proper interrupt level in the context
787 *     - initializing the floating point context
788 *
789 *  This routine generally does not set any unnecessary register
790 *  in the context.  The state of the "general data" registers is
791 *  undefined at task start time.
792 *
793 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
794 *        point thread.  This is typically only used on CPUs where the
795 *        FPU may be easily disabled by software such as on the SPARC
796 *        where the PSR contains an enable FPU bit.
797 *
798 *  The per-thread status register holds the interrupt enable, FP enable
799 *  and global interrupt enable for that thread.  It means each thread can
800 *  enable its own set of interrupts.  If interrupts are disabled, RTEMS
801 *  can still dispatch via blocking calls.  This is the function of the
802 *  "Interrupt Level", and on the MIPS, it controls the IEC bit and all
803 *  the hardware interrupts as defined in the SR.  Software ints
804 *  are automatically enabled for all threads, as they will only occur under
805 *  program control anyhow.  Besides, the interrupt level parm is only 8 bits,
806 *  and controlling the software ints plus the others would require 9.
807 *
808 *  If the Interrupt Level is 0, all ints are on.  Otherwise, the
809 *  Interrupt Level should supply a bit pattern to impose on the SR
810 *  interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6
811 *  apply to the SR register Intr bits from bit 10 thru bit 15.  Bit 7 of
812 *  the Interrupt Level parameter is unused at this time.
813 *
814 *  These are the only per-thread SR bits, the others are maintained
815 *  globally & explicitly preserved by the Context Switch code in cpu_asm.s
816 */
817
818
819#if (__mips == 3) || (__mips == 32)
820#define _INTON          SR_IE
821#if __mips_fpr==64
822#define _EXTRABITS      SR_FR
823#else
824#define _EXTRABITS      0
825#endif /* __mips_fpr==64 */
826#endif /* __mips == 3 */
827#if __mips == 1
828#define _INTON          SR_IEC
829#define _EXTRABITS      0  /* make sure we're in user mode on MIPS1 processors */
830#endif /* __mips == 1 */
831
832
833void _CPU_Context_Initialize(
834  Context_Control  *the_context,
835  uintptr_t        *stack_base,
836  uint32_t          size,
837  uint32_t          new_level,
838  void             *entry_point,
839  bool              is_fp
840);
841
842
843/*
844 *  This routine is responsible for somehow restarting the currently
845 *  executing task.  If you are lucky, then all that is necessary
846 *  is restoring the context.  Otherwise, there will need to be
847 *  a special assembly routine which does something special in this
848 *  case.  Context_Restore should work most of the time.  It will
849 *  not work if restarting self conflicts with the stack frame
850 *  assumptions of restoring a context.
851 */
852
853#define _CPU_Context_Restart_self( _the_context ) \
854   _CPU_Context_restore( (_the_context) );
855
856/*
857 *  The purpose of this macro is to allow the initial pointer into
858 *  A floating point context area (used to save the floating point
859 *  context) to be at an arbitrary place in the floating point
860 *  context area.
861 *
862 *  This is necessary because some FP units are designed to have
863 *  their context saved as a stack which grows into lower addresses.
864 *  Other FP units can be saved by simply moving registers into offsets
865 *  from the base of the context area.  Finally some FP units provide
866 *  a "dump context" instruction which could fill in from high to low
867 *  or low to high based on the whim of the CPU designers.
868 */
869
870#define _CPU_Context_Fp_start( _base, _offset ) \
871   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
872
873/*
874 *  This routine initializes the FP context area passed to it to.
875 *  There are a few standard ways in which to initialize the
876 *  floating point context.  The code included for this macro assumes
877 *  that this is a CPU in which a "initial" FP context was saved into
878 *  _CPU_Null_fp_context and it simply copies it to the destination
879 *  context passed to it.
880 *
881 *  Other models include (1) not doing anything, and (2) putting
882 *  a "null FP status word" in the correct place in the FP context.
883 */
884
885#if ( CPU_HARDWARE_FP == TRUE )
886#define _CPU_Context_Initialize_fp( _destination ) \
887  { \
888   *(*(_destination)) = _CPU_Null_fp_context; \
889  }
890#endif
891
892/* end of Context handler macros */
893
894/* Fatal Error manager macros */
895
896/*
897 *  This routine copies _error into a known place -- typically a stack
898 *  location or a register, optionally disables interrupts, and
899 *  halts/stops the CPU.
900 */
901
902#define _CPU_Fatal_halt( _error ) \
903  do { \
904    unsigned int _level; \
905    _CPU_ISR_Disable(_level); \
906    loop: goto loop; \
907  } while (0)
908
909
910extern void mips_break( int error );
911
912/* Bitfield handler macros */
913
914/*
915 *  This routine sets _output to the bit number of the first bit
916 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Control.
917 *  This type may be either 16 or 32 bits wide although only the 16
918 *  least significant bits will be used.
919 *
920 *  There are a number of variables in using a "find first bit" type
921 *  instruction.
922 *
923 *    (1) What happens when run on a value of zero?
924 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
925 *    (3) The numbering may be zero or one based.
926 *    (4) The "find first bit" instruction may search from MSB or LSB.
927 *
928 *  RTEMS guarantees that (1) will never happen so it is not a concern.
929 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
930 *  _CPU_Priority_bits_index().  These three form a set of routines
931 *  which must logically operate together.  Bits in the _value are
932 *  set and cleared based on masks built by _CPU_Priority_mask().
933 *  The basic major and minor values calculated by _Priority_Major()
934 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
935 *  to properly range between the values returned by the "find first bit"
936 *  instruction.  This makes it possible for _Priority_Get_highest() to
937 *  calculate the major and directly index into the minor table.
938 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
939 *  is the first bit found.
940 *
941 *  This entire "find first bit" and mapping process depends heavily
942 *  on the manner in which a priority is broken into a major and minor
943 *  components with the major being the 4 MSB of a priority and minor
944 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
945 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
946 *  to the lowest priority.
947 *
948 *  If your CPU does not have a "find first bit" instruction, then
949 *  there are ways to make do without it.  Here are a handful of ways
950 *  to implement this in software:
951 *
952 *    - a series of 16 bit test instructions
953 *    - a "binary search using if's"
954 *    - _number = 0
955 *      if _value > 0x00ff
956 *        _value >>=8
957 *        _number = 8;
958 *
959 *      if _value > 0x0000f
960 *        _value >=8
961 *        _number += 4
962 *
963 *      _number += bit_set_table[ _value ]
964 *
965 *    where bit_set_table[ 16 ] has values which indicate the first
966 *      bit set
967 */
968
969#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
970#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
971
972#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
973
974#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
975  { \
976    (_output) = 0;   /* do something to prevent warnings */ \
977  }
978
979#endif
980
981/* end of Bitfield handler macros */
982
983/*
984 *  This routine builds the mask which corresponds to the bit fields
985 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
986 *  for that routine.
987 */
988
989#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
990
991#define _CPU_Priority_Mask( _bit_number ) \
992  ( 1 << (_bit_number) )
993
994#endif
995
996/*
997 *  This routine translates the bit numbers returned by
998 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
999 *  a major or minor component of a priority.  See the discussion
1000 *  for that routine.
1001 */
1002
1003#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1004
1005#define _CPU_Priority_bits_index( _priority ) \
1006  (_priority)
1007
1008#endif
1009
1010/* end of Priority handler macros */
1011
1012/* functions */
1013
1014/*
1015 *  _CPU_Initialize
1016 *
1017 *  This routine performs CPU dependent initialization.
1018 */
1019
1020void _CPU_Initialize(void);
1021
1022/*
1023 *  _CPU_ISR_install_raw_handler
1024 *
1025 *  This routine installs a "raw" interrupt handler directly into the
1026 *  processor's vector table.
1027 */
1028
1029void _CPU_ISR_install_raw_handler(
1030  uint32_t    vector,
1031  proc_ptr    new_handler,
1032  proc_ptr   *old_handler
1033);
1034
1035/*
1036 *  _CPU_ISR_install_vector
1037 *
1038 *  This routine installs an interrupt vector.
1039 */
1040
1041void _CPU_ISR_install_vector(
1042  uint32_t    vector,
1043  proc_ptr    new_handler,
1044  proc_ptr   *old_handler
1045);
1046
1047/*
1048 *  _CPU_Install_interrupt_stack
1049 *
1050 *  This routine installs the hardware interrupt stack pointer.
1051 *
1052 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1053 *         is TRUE.
1054 */
1055
1056void _CPU_Install_interrupt_stack( void );
1057
1058/*
1059 *  _CPU_Internal_threads_Idle_thread_body
1060 *
1061 *  This routine is the CPU dependent IDLE thread body.
1062 *
1063 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1064 *         is TRUE.
1065 */
1066
1067void *_CPU_Thread_Idle_body( uintptr_t ignored );
1068
1069/*
1070 *  _CPU_Context_switch
1071 *
1072 *  This routine switches from the run context to the heir context.
1073 */
1074
1075void _CPU_Context_switch(
1076  Context_Control  *run,
1077  Context_Control  *heir
1078);
1079
1080/*
1081 *  _CPU_Context_restore
1082 *
1083 *  This routine is generally used only to restart self in an
1084 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1085 *
1086 *  NOTE: May be unnecessary to reload some registers.
1087 */
1088
1089void _CPU_Context_restore(
1090  Context_Control *new_context
1091) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1092
1093/*
1094 *  _CPU_Context_save_fp
1095 *
1096 *  This routine saves the floating point context passed to it.
1097 */
1098
1099void _CPU_Context_save_fp(
1100  Context_Control_fp **fp_context_ptr
1101);
1102
1103/*
1104 *  _CPU_Context_restore_fp
1105 *
1106 *  This routine restores the floating point context passed to it.
1107 */
1108
1109void _CPU_Context_restore_fp(
1110  Context_Control_fp **fp_context_ptr
1111);
1112
1113/*  The following routine swaps the endian format of an unsigned int.
1114 *  It must be static because it is referenced indirectly.
1115 *
1116 *  This version will work on any processor, but if there is a better
1117 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1118 *
1119 *     swap least significant two bytes with 16-bit rotate
1120 *     swap upper and lower 16-bits
1121 *     swap most significant two bytes with 16-bit rotate
1122 *
1123 *  Some CPUs have special instructions which swap a 32-bit quantity in
1124 *  a single instruction (e.g. i486).  It is probably best to avoid
1125 *  an "endian swapping control bit" in the CPU.  One good reason is
1126 *  that interrupts would probably have to be disabled to ensure that
1127 *  an interrupt does not try to access the same "chunk" with the wrong
1128 *  endian.  Another good reason is that on some CPUs, the endian bit
1129 *  endianness for ALL fetches -- both code and data -- so the code
1130 *  will be fetched incorrectly.
1131 */
1132
1133static inline uint32_t CPU_swap_u32(
1134  uint32_t value
1135)
1136{
1137  uint32_t   byte1, byte2, byte3, byte4, swapped;
1138
1139  byte4 = (value >> 24) & 0xff;
1140  byte3 = (value >> 16) & 0xff;
1141  byte2 = (value >> 8)  & 0xff;
1142  byte1 =  value        & 0xff;
1143
1144  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1145  return( swapped );
1146}
1147
1148#define CPU_swap_u16( value ) \
1149  (((value&0xff) << 8) | ((value >> 8)&0xff))
1150
1151
1152#endif
1153
1154
1155
1156#ifdef __cplusplus
1157}
1158#endif
1159
1160#endif
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