source: rtems/cpukit/score/cpu/mips/rtems/score/cpu.h @ 28e9f45

4.104.114.84.95
Last change on this file since 28e9f45 was 28e9f45, checked in by Joel Sherrill <joel.sherrill@…>, on 01/07/05 at 14:35:53

2005-01-07 Joel Sherrill <joel@…>

  • rtems/score/cpu.h: Remove warnings.
  • Property mode set to 100644
File size: 42.9 KB
Line 
1/*
2 *  Mips CPU Dependent Header File
3 *
4 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
5 *           Joel Sherrill <joel@OARcorp.com>.
6 *
7 *    These changes made the code conditional on standard cpp predefines,
8 *    merged the mips1 and mips3 code sequences as much as possible,
9 *    and moved some of the assembly code to C.  Alan did much of the
10 *    initial analysis and rework.  Joel took over from there and
11 *    wrote the JMR3904 BSP so this could be tested.  Joel also
12 *    added the new interrupt vectoring support in libcpu and
13 *    tried to better support the various interrupt controllers.
14 *
15 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
16 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
17 *
18 *    To anyone who acknowledges that this file is provided "AS IS"
19 *    without any express or implied warranty:
20 *      permission to use, copy, modify, and distribute this file
21 *      for any purpose is hereby granted without fee, provided that
22 *      the above copyright notice and this notice appears in all
23 *      copies, and that the name of Transition Networks not be used in
24 *      advertising or publicity pertaining to distribution of the
25 *      software without specific, written prior permission.
26 *      Transition Networks makes no representations about the suitability
27 *      of this software for any purpose.
28 *
29 *  COPYRIGHT (c) 1989-2001.
30 *  On-Line Applications Research Corporation (OAR).
31 *
32 *  The license and distribution terms for this file may be
33 *  found in the file LICENSE in this distribution or at
34 *  http://www.rtems.com/license/LICENSE.
35 *
36 *  $Id$
37 */
38
39#ifndef __CPU_h
40#define __CPU_h
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
46#include <rtems/score/mips.h>       /* pick up machine definitions */
47#ifndef ASM
48#include <rtems/score/types.h>
49#endif
50
51#ifndef TRUE
52#define TRUE 1
53#endif
54#ifndef FALSE
55#define FALSE 0
56#endif
57
58
59/* conditional compilation parameters */
60
61/*
62 *  Should the calls to _Thread_Enable_dispatch be inlined?
63 *
64 *  If TRUE, then they are inlined.
65 *  If FALSE, then a subroutine call is made.
66 *
67 *  Basically this is an example of the classic trade-off of size
68 *  versus speed.  Inlining the call (TRUE) typically increases the
69 *  size of RTEMS while speeding up the enabling of dispatching.
70 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
71 *  only be 0 or 1 unless you are in an interrupt handler and that
72 *  interrupt handler invokes the executive.]  When not inlined
73 *  something calls _Thread_Enable_dispatch which in turns calls
74 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
75 *  one subroutine call is avoided entirely.]
76 */
77
78#define CPU_INLINE_ENABLE_DISPATCH       FALSE
79
80/*
81 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
82 *  be unrolled one time?  In unrolled each iteration of the loop examines
83 *  two "nodes" on the chain being searched.  Otherwise, only one node
84 *  is examined per iteration.
85 *
86 *  If TRUE, then the loops are unrolled.
87 *  If FALSE, then the loops are not unrolled.
88 *
89 *  The primary factor in making this decision is the cost of disabling
90 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
91 *  body of the loop.  On some CPUs, the flash is more expensive than
92 *  one iteration of the loop body.  In this case, it might be desirable
93 *  to unroll the loop.  It is important to note that on some CPUs, this
94 *  code is the longest interrupt disable period in RTEMS.  So it is
95 *  necessary to strike a balance when setting this parameter.
96 */
97
98#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
99
100/*
101 *  Does RTEMS manage a dedicated interrupt stack in software?
102 *
103 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
104 *  If FALSE, nothing is done.
105 *
106 *  If the CPU supports a dedicated interrupt stack in hardware,
107 *  then it is generally the responsibility of the BSP to allocate it
108 *  and set it up.
109 *
110 *  If the CPU does not support a dedicated interrupt stack, then
111 *  the porter has two options: (1) execute interrupts on the
112 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
113 *  interrupt stack.
114 *
115 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
116 *
117 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
118 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
119 *  possible that both are FALSE for a particular CPU.  Although it
120 *  is unclear what that would imply about the interrupt processing
121 *  procedure on that CPU.
122 */
123
124#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
125
126/*
127 *  Does this CPU have hardware support for a dedicated interrupt stack?
128 *
129 *  If TRUE, then it must be installed during initialization.
130 *  If FALSE, then no installation is performed.
131 *
132 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
133 *
134 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
135 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
136 *  possible that both are FALSE for a particular CPU.  Although it
137 *  is unclear what that would imply about the interrupt processing
138 *  procedure on that CPU.
139 */
140
141#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
142
143/*
144 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
145 *
146 *  If TRUE, then the memory is allocated during initialization.
147 *  If FALSE, then the memory is allocated during initialization.
148 *
149 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
150 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
151 */
152
153#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
154
155/*
156 *  Does the RTEMS invoke the user's ISR with the vector number and
157 *  a pointer to the saved interrupt frame (1) or just the vector
158 *  number (0)?
159 *
160 */
161
162#define CPU_ISR_PASSES_FRAME_POINTER 1
163
164
165
166/*
167 *  Does the CPU have hardware floating point?
168 *
169 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
170 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
171 *
172 *  If there is a FP coprocessor such as the i387 or mc68881, then
173 *  the answer is TRUE.
174 *
175 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
176 *  It indicates whether or not this CPU model has FP support.  For
177 *  example, it would be possible to have an i386_nofp CPU model
178 *  which set this to false to indicate that you have an i386 without
179 *  an i387 and wish to leave floating point support out of RTEMS.
180 */
181
182#if ( MIPS_HAS_FPU == 1 )
183#define CPU_HARDWARE_FP     TRUE
184#else
185#define CPU_HARDWARE_FP     FALSE
186#endif
187
188/*
189 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
190 *
191 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
192 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
193 *
194 *  So far, the only CPU in which this option has been used is the
195 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
196 *  floating point registers to perform integer multiplies.  If
197 *  a function which you would not think utilize the FP unit DOES,
198 *  then one can not easily predict which tasks will use the FP hardware.
199 *  In this case, this option should be TRUE.
200 *
201 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
202 */
203
204#define CPU_ALL_TASKS_ARE_FP    FALSE
205
206/*
207 *  Should the IDLE task have a floating point context?
208 *
209 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
210 *  and it has a floating point context which is switched in and out.
211 *  If FALSE, then the IDLE task does not have a floating point context.
212 *
213 *  Setting this to TRUE negatively impacts the time required to preempt
214 *  the IDLE task from an interrupt because the floating point context
215 *  must be saved as part of the preemption.
216 */
217
218#define CPU_IDLE_TASK_IS_FP      FALSE
219
220/*
221 *  Should the saving of the floating point registers be deferred
222 *  until a context switch is made to another different floating point
223 *  task?
224 *
225 *  If TRUE, then the floating point context will not be stored until
226 *  necessary.  It will remain in the floating point registers and not
227 *  disturned until another floating point task is switched to.
228 *
229 *  If FALSE, then the floating point context is saved when a floating
230 *  point task is switched out and restored when the next floating point
231 *  task is restored.  The state of the floating point registers between
232 *  those two operations is not specified.
233 *
234 *  If the floating point context does NOT have to be saved as part of
235 *  interrupt dispatching, then it should be safe to set this to TRUE.
236 *
237 *  Setting this flag to TRUE results in using a different algorithm
238 *  for deciding when to save and restore the floating point context.
239 *  The deferred FP switch algorithm minimizes the number of times
240 *  the FP context is saved and restored.  The FP context is not saved
241 *  until a context switch is made to another, different FP task.
242 *  Thus in a system with only one FP task, the FP context will never
243 *  be saved or restored.
244 */
245
246#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
247
248/*
249 *  Does this port provide a CPU dependent IDLE task implementation?
250 *
251 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
252 *  must be provided and is the default IDLE thread body instead of
253 *  _Internal_threads_Idle_thread_body.
254 *
255 *  If FALSE, then use the generic IDLE thread body if the BSP does
256 *  not provide one.
257 *
258 *  This is intended to allow for supporting processors which have
259 *  a low power or idle mode.  When the IDLE thread is executed, then
260 *  the CPU can be powered down.
261 *
262 *  The order of precedence for selecting the IDLE thread body is:
263 *
264 *    1.  BSP provided
265 *    2.  CPU dependent (if provided)
266 *    3.  generic (if no BSP and no CPU dependent)
267 */
268
269/* we can use the low power wait instruction for the IDLE thread */
270#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
271
272/*
273 *  Does the stack grow up (toward higher addresses) or down
274 *  (toward lower addresses)?
275 *
276 *  If TRUE, then the grows upward.
277 *  If FALSE, then the grows toward smaller addresses.
278 */
279
280/* our stack grows down */
281#define CPU_STACK_GROWS_UP               FALSE
282
283/*
284 *  The following is the variable attribute used to force alignment
285 *  of critical RTEMS structures.  On some processors it may make
286 *  sense to have these aligned on tighter boundaries than
287 *  the minimum requirements of the compiler in order to have as
288 *  much of the critical data area as possible in a cache line.
289 *
290 *  The placement of this macro in the declaration of the variables
291 *  is based on the syntactically requirements of the GNU C
292 *  "__attribute__" extension.  For example with GNU C, use
293 *  the following to force a structures to a 32 byte boundary.
294 *
295 *      __attribute__ ((aligned (32)))
296 *
297 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
298 *         To benefit from using this, the data must be heavily
299 *         used so it will stay in the cache and used frequently enough
300 *         in the executive to justify turning this on.
301 */
302
303/* our cache line size is 16 bytes */
304#if __GNUC__
305#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
306#else
307#define CPU_STRUCTURE_ALIGNMENT
308#endif
309
310/*
311 *  Define what is required to specify how the network to host conversion
312 *  routines are handled.
313 */
314
315#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
316#define CPU_BIG_ENDIAN                           TRUE
317#define CPU_LITTLE_ENDIAN                        FALSE
318
319/*
320 *  The following defines the number of bits actually used in the
321 *  interrupt field of the task mode.  How those bits map to the
322 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
323 */
324
325#define CPU_MODES_INTERRUPT_MASK   0x000000ff
326
327/*
328 *  Processor defined structures
329 *
330 *  Examples structures include the descriptor tables from the i386
331 *  and the processor control structure on the i960ca.
332 */
333
334/* may need to put some structures here.  */
335
336/*
337 * Contexts
338 *
339 *  Generally there are 2 types of context to save.
340 *     1. Interrupt registers to save
341 *     2. Task level registers to save
342 *
343 *  This means we have the following 3 context items:
344 *     1. task level context stuff::  Context_Control
345 *     2. floating point task stuff:: Context_Control_fp
346 *     3. special interrupt level context :: Context_Control_interrupt
347 *
348 *  On some processors, it is cost-effective to save only the callee
349 *  preserved registers during a task context switch.  This means
350 *  that the ISR code needs to save those registers which do not
351 *  persist across function calls.  It is not mandatory to make this
352 *  distinctions between the caller/callee saves registers for the
353 *  purpose of minimizing context saved during task switch and on interrupts.
354 *  If the cost of saving extra registers is minimal, simplicity is the
355 *  choice.  Save the same context on interrupt entry as for tasks in
356 *  this case.
357 *
358 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
359 *  care should be used in designing the context area.
360 *
361 *  On some CPUs with hardware floating point support, the Context_Control_fp
362 *  structure will not be used or it simply consist of an array of a
363 *  fixed number of bytes.   This is done when the floating point context
364 *  is dumped by a "FP save context" type instruction and the format
365 *  is not really defined by the CPU.  In this case, there is no need
366 *  to figure out the exact format -- only the size.  Of course, although
367 *  this is enough information for RTEMS, it is probably not enough for
368 *  a debugger such as gdb.  But that is another problem.
369 */
370
371#ifndef ASSEMBLY_ONLY
372
373/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
374#if (__mips == 1) || (__mips == 32)
375#define __MIPS_REGISTER_TYPE     uint32_t 
376#define __MIPS_FPU_REGISTER_TYPE uint32_t 
377#elif __mips == 3
378#define __MIPS_REGISTER_TYPE     uint64_t 
379#define __MIPS_FPU_REGISTER_TYPE uint64_t 
380#else
381#error "mips register size: unknown architecture level!!"
382#endif
383typedef struct {
384    __MIPS_REGISTER_TYPE s0;
385    __MIPS_REGISTER_TYPE s1;
386    __MIPS_REGISTER_TYPE s2;
387    __MIPS_REGISTER_TYPE s3;
388    __MIPS_REGISTER_TYPE s4;
389    __MIPS_REGISTER_TYPE s5;
390    __MIPS_REGISTER_TYPE s6;
391    __MIPS_REGISTER_TYPE s7;
392    __MIPS_REGISTER_TYPE sp;
393    __MIPS_REGISTER_TYPE fp;
394    __MIPS_REGISTER_TYPE ra;
395    __MIPS_REGISTER_TYPE c0_sr;
396    __MIPS_REGISTER_TYPE c0_epc;
397} Context_Control;
398
399/* WARNING: If this structure is modified, the constants in cpu.h
400 *          must also be updated.
401 */
402
403typedef struct {
404#if ( CPU_HARDWARE_FP == TRUE )
405    __MIPS_FPU_REGISTER_TYPE fp0;
406    __MIPS_FPU_REGISTER_TYPE fp1;
407    __MIPS_FPU_REGISTER_TYPE fp2;
408    __MIPS_FPU_REGISTER_TYPE fp3;
409    __MIPS_FPU_REGISTER_TYPE fp4;
410    __MIPS_FPU_REGISTER_TYPE fp5;
411    __MIPS_FPU_REGISTER_TYPE fp6;
412    __MIPS_FPU_REGISTER_TYPE fp7;
413    __MIPS_FPU_REGISTER_TYPE fp8;
414    __MIPS_FPU_REGISTER_TYPE fp9;
415    __MIPS_FPU_REGISTER_TYPE fp10;
416    __MIPS_FPU_REGISTER_TYPE fp11;
417    __MIPS_FPU_REGISTER_TYPE fp12;
418    __MIPS_FPU_REGISTER_TYPE fp13;
419    __MIPS_FPU_REGISTER_TYPE fp14;
420    __MIPS_FPU_REGISTER_TYPE fp15;
421    __MIPS_FPU_REGISTER_TYPE fp16;
422    __MIPS_FPU_REGISTER_TYPE fp17;
423    __MIPS_FPU_REGISTER_TYPE fp18;
424    __MIPS_FPU_REGISTER_TYPE fp19;
425    __MIPS_FPU_REGISTER_TYPE fp20;
426    __MIPS_FPU_REGISTER_TYPE fp21;
427    __MIPS_FPU_REGISTER_TYPE fp22;
428    __MIPS_FPU_REGISTER_TYPE fp23;
429    __MIPS_FPU_REGISTER_TYPE fp24;
430    __MIPS_FPU_REGISTER_TYPE fp25;
431    __MIPS_FPU_REGISTER_TYPE fp26;
432    __MIPS_FPU_REGISTER_TYPE fp27;
433    __MIPS_FPU_REGISTER_TYPE fp28;
434    __MIPS_FPU_REGISTER_TYPE fp29;
435    __MIPS_FPU_REGISTER_TYPE fp30;
436    __MIPS_FPU_REGISTER_TYPE fp31;
437    __MIPS_FPU_REGISTER_TYPE fpcs;
438#endif
439} Context_Control_fp;
440
441/*
442 *  This struct reflects the stack frame employed in ISR_Handler.  Note
443 *  that the ISR routine save some of the registers to this frame for
444 *  all interrupts and exceptions.  Other registers are saved only on
445 *  exceptions, while others are not touched at all.  The untouched
446 *  registers are not normally disturbed by high-level language
447 *  programs so they can be accessed when required.
448 *
449 *  The registers and their ordering in this struct must directly
450 *  correspond to the layout and ordering of * shown in iregdef.h,
451 *  as cpu_asm.S uses those definitions to fill the stack frame. 
452 *  This struct provides access to the stack frame for C code.
453 *
454 *  Similarly, this structure is used by debugger stubs and exception
455 *  processing routines so be careful when changing the format.
456 *
457 *  NOTE: The comments with this structure and cpu_asm.S should be kept
458 *        in sync.  When in doubt, look in the  code to see if the
459 *        registers you're interested in are actually treated as expected.
460 *        The order of the first portion of this structure follows the
461 *        order of registers expected by gdb.
462 */
463
464typedef struct
465{
466  __MIPS_REGISTER_TYPE  r0;       /*  0 -- NOT FILLED IN */
467  __MIPS_REGISTER_TYPE  at;       /*  1 -- saved always */
468  __MIPS_REGISTER_TYPE  v0;       /*  2 -- saved always */
469  __MIPS_REGISTER_TYPE  v1;       /*  3 -- saved always */
470  __MIPS_REGISTER_TYPE  a0;       /*  4 -- saved always */
471  __MIPS_REGISTER_TYPE  a1;       /*  5 -- saved always */
472  __MIPS_REGISTER_TYPE  a2;       /*  6 -- saved always */
473  __MIPS_REGISTER_TYPE  a3;       /*  7 -- saved always */
474  __MIPS_REGISTER_TYPE  t0;       /*  8 -- saved always */
475  __MIPS_REGISTER_TYPE  t1;       /*  9 -- saved always */
476  __MIPS_REGISTER_TYPE  t2;       /* 10 -- saved always */
477  __MIPS_REGISTER_TYPE  t3;       /* 11 -- saved always */
478  __MIPS_REGISTER_TYPE  t4;       /* 12 -- saved always */
479  __MIPS_REGISTER_TYPE  t5;       /* 13 -- saved always */
480  __MIPS_REGISTER_TYPE  t6;       /* 14 -- saved always */
481  __MIPS_REGISTER_TYPE  t7;       /* 15 -- saved always */
482  __MIPS_REGISTER_TYPE  s0;       /* 16 -- saved on exceptions */
483  __MIPS_REGISTER_TYPE  s1;       /* 17 -- saved on exceptions */
484  __MIPS_REGISTER_TYPE  s2;       /* 18 -- saved on exceptions */
485  __MIPS_REGISTER_TYPE  s3;       /* 19 -- saved on exceptions */
486  __MIPS_REGISTER_TYPE  s4;       /* 20 -- saved on exceptions */
487  __MIPS_REGISTER_TYPE  s5;       /* 21 -- saved on exceptions */
488  __MIPS_REGISTER_TYPE  s6;       /* 22 -- saved on exceptions */
489  __MIPS_REGISTER_TYPE  s7;       /* 23 -- saved on exceptions */
490  __MIPS_REGISTER_TYPE  t8;       /* 24 -- saved always */
491  __MIPS_REGISTER_TYPE  t9;       /* 25 -- saved always */
492  __MIPS_REGISTER_TYPE  k0;       /* 26 -- NOT FILLED IN, kernel tmp reg */
493  __MIPS_REGISTER_TYPE  k1;       /* 27 -- NOT FILLED IN, kernel tmp reg */
494  __MIPS_REGISTER_TYPE  gp;       /* 28 -- saved always */
495  __MIPS_REGISTER_TYPE  sp;       /* 29 -- saved on exceptions NOT RESTORED */
496  __MIPS_REGISTER_TYPE  fp;       /* 30 -- saved always */
497  __MIPS_REGISTER_TYPE  ra;       /* 31 -- saved always */
498  __MIPS_REGISTER_TYPE  c0_sr;    /* 32 -- saved always, some bits are */
499                                  /*    manipulated per-thread          */
500  __MIPS_REGISTER_TYPE  mdlo;     /* 33 -- saved always */
501  __MIPS_REGISTER_TYPE  mdhi;     /* 34 -- saved always */
502  __MIPS_REGISTER_TYPE  badvaddr; /* 35 -- saved on exceptions, read-only */
503  __MIPS_REGISTER_TYPE  cause;    /* 36 -- saved on exceptions NOT restored */
504  __MIPS_REGISTER_TYPE  epc;      /* 37 -- saved always, read-only register */
505                                  /*        but logically restored */
506  __MIPS_FPU_REGISTER_TYPE f0;    /* 38 -- saved if FP enabled */
507  __MIPS_FPU_REGISTER_TYPE f1;    /* 39 -- saved if FP enabled */
508  __MIPS_FPU_REGISTER_TYPE f2;    /* 40 -- saved if FP enabled */
509  __MIPS_FPU_REGISTER_TYPE f3;    /* 41 -- saved if FP enabled */
510  __MIPS_FPU_REGISTER_TYPE f4;    /* 42 -- saved if FP enabled */
511  __MIPS_FPU_REGISTER_TYPE f5;    /* 43 -- saved if FP enabled */
512  __MIPS_FPU_REGISTER_TYPE f6;    /* 44 -- saved if FP enabled */
513  __MIPS_FPU_REGISTER_TYPE f7;    /* 45 -- saved if FP enabled */
514  __MIPS_FPU_REGISTER_TYPE f8;    /* 46 -- saved if FP enabled */
515  __MIPS_FPU_REGISTER_TYPE f9;    /* 47 -- saved if FP enabled */
516  __MIPS_FPU_REGISTER_TYPE f10;   /* 48 -- saved if FP enabled */
517  __MIPS_FPU_REGISTER_TYPE f11;   /* 49 -- saved if FP enabled */
518  __MIPS_FPU_REGISTER_TYPE f12;   /* 50 -- saved if FP enabled */
519  __MIPS_FPU_REGISTER_TYPE f13;   /* 51 -- saved if FP enabled */
520  __MIPS_FPU_REGISTER_TYPE f14;   /* 52 -- saved if FP enabled */
521  __MIPS_FPU_REGISTER_TYPE f15;   /* 53 -- saved if FP enabled */
522  __MIPS_FPU_REGISTER_TYPE f16;   /* 54 -- saved if FP enabled */
523  __MIPS_FPU_REGISTER_TYPE f17;   /* 55 -- saved if FP enabled */
524  __MIPS_FPU_REGISTER_TYPE f18;   /* 56 -- saved if FP enabled */
525  __MIPS_FPU_REGISTER_TYPE f19;   /* 57 -- saved if FP enabled */
526  __MIPS_FPU_REGISTER_TYPE f20;   /* 58 -- saved if FP enabled */
527  __MIPS_FPU_REGISTER_TYPE f21;   /* 59 -- saved if FP enabled */
528  __MIPS_FPU_REGISTER_TYPE f22;   /* 60 -- saved if FP enabled */
529  __MIPS_FPU_REGISTER_TYPE f23;   /* 61 -- saved if FP enabled */
530  __MIPS_FPU_REGISTER_TYPE f24;   /* 62 -- saved if FP enabled */
531  __MIPS_FPU_REGISTER_TYPE f25;   /* 63 -- saved if FP enabled */
532  __MIPS_FPU_REGISTER_TYPE f26;   /* 64 -- saved if FP enabled */
533  __MIPS_FPU_REGISTER_TYPE f27;   /* 65 -- saved if FP enabled */
534  __MIPS_FPU_REGISTER_TYPE f28;   /* 66 -- saved if FP enabled */
535  __MIPS_FPU_REGISTER_TYPE f29;   /* 67 -- saved if FP enabled */
536  __MIPS_FPU_REGISTER_TYPE f30;   /* 68 -- saved if FP enabled */
537  __MIPS_FPU_REGISTER_TYPE f31;   /* 69 -- saved if FP enabled */
538  __MIPS_REGISTER_TYPE     fcsr;  /* 70 -- saved on exceptions */
539                                  /*    (oddly not documented on MGV) */
540  __MIPS_REGISTER_TYPE     feir;  /* 71 -- saved on exceptions */
541                                  /*    (oddly not documented on MGV) */
542
543  /* GDB does not seem to care about anything past this point */
544
545  __MIPS_REGISTER_TYPE  tlbhi;    /* 72 - NOT FILLED IN, doesn't exist on */
546                                  /*         all MIPS CPUs (at least MGV) */
547#if __mips == 1
548  __MIPS_REGISTER_TYPE  tlblo;    /* 73 - NOT FILLED IN, doesn't exist on */
549                                  /*         all MIPS CPUs (at least MGV) */
550#endif
551#if  (__mips == 3) || (__mips == 32)
552  __MIPS_REGISTER_TYPE  tlblo0;   /* 73 - NOT FILLED IN, doesn't exist on */
553                                  /*         all MIPS CPUs (at least MGV) */
554#endif
555
556  __MIPS_REGISTER_TYPE  inx;      /* 74 -- NOT FILLED IN, doesn't exist on */
557                                  /*         all MIPS CPUs (at least MGV) */
558  __MIPS_REGISTER_TYPE  rand;     /* 75 -- NOT FILLED IN, doesn't exist on */
559                                  /*         all MIPS CPUs (at least MGV) */
560  __MIPS_REGISTER_TYPE  ctxt;     /* 76 -- NOT FILLED IN, doesn't exist on */
561                                  /*         all MIPS CPUs (at least MGV) */
562  __MIPS_REGISTER_TYPE  exctype;  /* 77 -- NOT FILLED IN (not enough info) */
563  __MIPS_REGISTER_TYPE  mode;     /* 78 -- NOT FILLED IN (not enough info) */
564  __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
565  __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
566  /* end of __mips == 1 so NREGS == 81 */
567#if  (__mips == 3) || (__mips == 32)
568  __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
569  __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
570  __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
571  __MIPS_REGISTER_TYPE  count;    /* 84 -- NOT FILLED IN */
572  __MIPS_REGISTER_TYPE  compare;  /* 85 -- NOT FILLED IN */
573  __MIPS_REGISTER_TYPE  config;   /* 86 -- NOT FILLED IN */
574  __MIPS_REGISTER_TYPE  lladdr;   /* 87 -- NOT FILLED IN */
575  __MIPS_REGISTER_TYPE  watchlo;  /* 88 -- NOT FILLED IN */
576  __MIPS_REGISTER_TYPE  watchhi;  /* 89 -- NOT FILLED IN */
577  __MIPS_REGISTER_TYPE  ecc;      /* 90 -- NOT FILLED IN */
578  __MIPS_REGISTER_TYPE  cacheerr; /* 91 -- NOT FILLED IN */
579  __MIPS_REGISTER_TYPE  taglo;    /* 92 -- NOT FILLED IN */
580  __MIPS_REGISTER_TYPE  taghi;    /* 93 -- NOT FILLED IN */
581  __MIPS_REGISTER_TYPE  errpc;    /* 94 -- NOT FILLED IN */
582  __MIPS_REGISTER_TYPE  xctxt;    /* 95 -- NOT FILLED IN */
583 /* end of __mips == 3 so NREGS == 96 */
584#endif
585
586} CPU_Interrupt_frame;
587
588
589/*
590 *  The following table contains the information required to configure
591 *  the mips processor specific parameters.
592 */
593
594typedef struct {
595  void       (*pretasking_hook)( void );
596  void       (*predriver_hook)( void );
597  void       (*postdriver_hook)( void );
598  void       (*idle_task)( void );
599  boolean      do_zero_of_workspace;
600  uint32_t     idle_task_stack_size;
601  uint32_t     interrupt_stack_size;
602  uint32_t     extra_mpci_receive_server_stack;
603  void *     (*stack_allocate_hook)( uint32_t   );
604  void       (*stack_free_hook)( void* );
605  /* end of fields required on all CPUs */
606
607  uint32_t     clicks_per_microsecond;
608}   rtems_cpu_table;
609
610
611/*
612 *  Macros to access required entires in the CPU Table are in
613 *  the file rtems/system.h.
614 */
615
616/*
617 *  Macros to access MIPS specific additions to the CPU Table
618 */
619
620#define rtems_cpu_configuration_get_clicks_per_microsecond() \
621   (_CPU_Table.clicks_per_microsecond)
622
623/*
624 *  This variable is optional.  It is used on CPUs on which it is difficult
625 *  to generate an "uninitialized" FP context.  It is filled in by
626 *  _CPU_Initialize and copied into the task's FP context area during
627 *  _CPU_Context_Initialize.
628 */
629
630SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
631
632/*
633 *  On some CPUs, RTEMS supports a software managed interrupt stack.
634 *  This stack is allocated by the Interrupt Manager and the switch
635 *  is performed in _ISR_Handler.  These variables contain pointers
636 *  to the lowest and highest addresses in the chunk of memory allocated
637 *  for the interrupt stack.  Since it is unknown whether the stack
638 *  grows up or down (in general), this give the CPU dependent
639 *  code the option of picking the version it wants to use.
640 *
641 *  NOTE: These two variables are required if the macro
642 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
643 */
644
645SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
646SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
647
648/*
649 *  With some compilation systems, it is difficult if not impossible to
650 *  call a high-level language routine from assembly language.  This
651 *  is especially true of commercial Ada compilers and name mangling
652 *  C++ ones.  This variable can be optionally defined by the CPU porter
653 *  and contains the address of the routine _Thread_Dispatch.  This
654 *  can make it easier to invoke that routine at the end of the interrupt
655 *  sequence (if a dispatch is necessary).
656 *
657
658SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
659 *
660 *  NOTE: Not needed on this port.
661 */
662
663
664
665/*
666 *  Nothing prevents the porter from declaring more CPU specific variables.
667 */
668
669/* XXX: if needed, put more variables here */
670
671/*
672 *  The size of the floating point context area.  On some CPUs this
673 *  will not be a "sizeof" because the format of the floating point
674 *  area is not defined -- only the size is.  This is usually on
675 *  CPUs with a "floating point save context" instruction.
676 */
677
678#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
679
680/*
681 *  Amount of extra stack (above minimum stack size) required by
682 *  system initialization thread.  Remember that in a multiprocessor
683 *  system the system intialization thread becomes the MP server thread.
684 */
685
686#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
687
688/*
689 *  This defines the number of entries in the ISR_Vector_table managed
690 *  by RTEMS.
691 */
692
693extern unsigned int mips_interrupt_number_of_vectors;
694#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (mips_interrupt_number_of_vectors)
695#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
696
697/*
698 *  Should be large enough to run all RTEMS tests.  This insures
699 *  that a "reasonable" small application should not have any problems.
700 */
701
702#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(unsigned32))
703
704
705/*
706 *  CPU's worst alignment requirement for data types on a byte boundary.  This
707 *  alignment does not take into account the requirements for the stack.
708 */
709
710#define CPU_ALIGNMENT              8
711
712/*
713 *  This number corresponds to the byte alignment requirement for the
714 *  heap handler.  This alignment requirement may be stricter than that
715 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
716 *  common for the heap to follow the same alignment requirement as
717 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
718 *  then this should be set to CPU_ALIGNMENT.
719 *
720 *  NOTE:  This does not have to be a power of 2.  It does have to
721 *         be greater or equal to than CPU_ALIGNMENT.
722 */
723
724#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
725
726/*
727 *  This number corresponds to the byte alignment requirement for memory
728 *  buffers allocated by the partition manager.  This alignment requirement
729 *  may be stricter than that for the data types alignment specified by
730 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
731 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
732 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
733 *
734 *  NOTE:  This does not have to be a power of 2.  It does have to
735 *         be greater or equal to than CPU_ALIGNMENT.
736 */
737
738#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
739
740/*
741 *  This number corresponds to the byte alignment requirement for the
742 *  stack.  This alignment requirement may be stricter than that for the
743 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
744 *  is strict enough for the stack, then this should be set to 0.
745 *
746 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
747 */
748
749#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
750
751/*
752 *  ISR handler macros
753 */
754
755/*
756 *  Support routine to initialize the RTEMS vector table after it is allocated.
757 */
758
759#define _CPU_Initialize_vectors()
760
761/*
762 *  Disable all interrupts for an RTEMS critical section.  The previous
763 *  level is returned in _level.
764 */
765
766#define _CPU_ISR_Disable( _level ) \
767  do { \
768    unsigned int _scratch; \
769    mips_get_sr( _scratch ); \
770    mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
771    _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
772  } while(0)
773
774/*
775 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
776 *  This indicates the end of an RTEMS critical section.  The parameter
777 *  _level is not modified.
778 */
779
780#define _CPU_ISR_Enable( _level )  \
781  do { \
782    unsigned int _scratch; \
783    mips_get_sr( _scratch ); \
784    mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
785  } while(0)
786
787/*
788 *  This temporarily restores the interrupt to _level before immediately
789 *  disabling them again.  This is used to divide long RTEMS critical
790 *  sections into two or more parts.  The parameter _level is not
791 *  modified.
792 */
793
794#define _CPU_ISR_Flash( _xlevel ) \
795  do { \
796    unsigned int _scratch2 = _xlevel; \
797    _CPU_ISR_Enable( _scratch2 ); \
798    _CPU_ISR_Disable( _scratch2 ); \
799    _xlevel = _scratch2; \
800  } while(0)
801
802/*
803 *  Map interrupt level in task mode onto the hardware that the CPU
804 *  actually provides.  Currently, interrupt levels which do not
805 *  map onto the CPU in a generic fashion are undefined.  Someday,
806 *  it would be nice if these were "mapped" by the application
807 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
808 *  8 - 255 would be available for bsp/application specific meaning.
809 *  This could be used to manage a programmable interrupt controller
810 *  via the rtems_task_mode directive.
811 *
812 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
813 *  manipulates the IEC.
814 */
815
816uint32_t   _CPU_ISR_Get_level( void );  /* in cpu.c */
817
818void _CPU_ISR_Set_level( uint32_t   );  /* in cpu.c */
819
820/* end of ISR handler macros */
821
822/* Context handler macros */
823
824/*
825 *  Initialize the context to a state suitable for starting a
826 *  task after a context restore operation.  Generally, this
827 *  involves:
828 *
829 *     - setting a starting address
830 *     - preparing the stack
831 *     - preparing the stack and frame pointers
832 *     - setting the proper interrupt level in the context
833 *     - initializing the floating point context
834 *
835 *  This routine generally does not set any unnecessary register
836 *  in the context.  The state of the "general data" registers is
837 *  undefined at task start time.
838 *
839 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
840 *        point thread.  This is typically only used on CPUs where the
841 *        FPU may be easily disabled by software such as on the SPARC
842 *        where the PSR contains an enable FPU bit.
843 *
844 *  The per-thread status register holds the interrupt enable, FP enable
845 *  and global interrupt enable for that thread.  It means each thread can
846 *  enable its own set of interrupts.  If interrupts are disabled, RTEMS
847 *  can still dispatch via blocking calls.  This is the function of the
848 *  "Interrupt Level", and on the MIPS, it controls the IEC bit and all
849 *  the hardware interrupts as defined in the SR.  Software ints
850 *  are automatically enabled for all threads, as they will only occur under
851 *  program control anyhow.  Besides, the interrupt level parm is only 8 bits,
852 *  and controlling the software ints plus the others would require 9.
853 *
854 *  If the Interrupt Level is 0, all ints are on.  Otherwise, the
855 *  Interrupt Level should supply a bit pattern to impose on the SR
856 *  interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6
857 *  apply to the SR register Intr bits from bit 10 thru bit 15.  Bit 7 of
858 *  the Interrupt Level parameter is unused at this time.
859 *
860 *  These are the only per-thread SR bits, the others are maintained
861 *  globally & explicitly preserved by the Context Switch code in cpu_asm.s
862 */
863
864
865#if (__mips == 3) || (__mips == 32)
866#define _INTON          SR_IE
867#define _EXTRABITS      0
868#endif
869#if __mips == 1
870#define _INTON          SR_IEC
871#define _EXTRABITS      0  /* make sure we're in user mode on MIPS1 processors */
872#endif
873
874#define _CPU_Context_Initialize( _the_context, _stack_base, _size, _isr, _entry_point, _is_fp ) \
875  { \
876        uint32_t   _stack_tmp = \
877           (uint32_t  )(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
878        uint32_t   _intlvl = _isr & 0xff; \
879        _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
880        (_the_context)->sp = _stack_tmp; \
881        (_the_context)->fp = _stack_tmp; \
882        (_the_context)->ra = (__MIPS_REGISTER_TYPE)_entry_point; \
883        (_the_context)->c0_sr = ((_intlvl==0)?(0xFF00 | _INTON):( ((_intlvl<<9) & 0xfc00) | \
884                                                       0x300 | \
885                                                       ((_intlvl & 1)?_INTON:0)) ) | \
886                                SR_CU0 | ((_is_fp)?SR_CU1:0) | _EXTRABITS; \
887  }
888
889
890
891/*
892 *  This routine is responsible for somehow restarting the currently
893 *  executing task.  If you are lucky, then all that is necessary
894 *  is restoring the context.  Otherwise, there will need to be
895 *  a special assembly routine which does something special in this
896 *  case.  Context_Restore should work most of the time.  It will
897 *  not work if restarting self conflicts with the stack frame
898 *  assumptions of restoring a context.
899 */
900
901#define _CPU_Context_Restart_self( _the_context ) \
902   _CPU_Context_restore( (_the_context) );
903
904/*
905 *  The purpose of this macro is to allow the initial pointer into
906 *  A floating point context area (used to save the floating point
907 *  context) to be at an arbitrary place in the floating point
908 *  context area.
909 *
910 *  This is necessary because some FP units are designed to have
911 *  their context saved as a stack which grows into lower addresses.
912 *  Other FP units can be saved by simply moving registers into offsets
913 *  from the base of the context area.  Finally some FP units provide
914 *  a "dump context" instruction which could fill in from high to low
915 *  or low to high based on the whim of the CPU designers.
916 */
917
918#define _CPU_Context_Fp_start( _base, _offset ) \
919   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
920
921/*
922 *  This routine initializes the FP context area passed to it to.
923 *  There are a few standard ways in which to initialize the
924 *  floating point context.  The code included for this macro assumes
925 *  that this is a CPU in which a "initial" FP context was saved into
926 *  _CPU_Null_fp_context and it simply copies it to the destination
927 *  context passed to it.
928 *
929 *  Other models include (1) not doing anything, and (2) putting
930 *  a "null FP status word" in the correct place in the FP context.
931 */
932
933#if ( CPU_HARDWARE_FP == TRUE )
934#define _CPU_Context_Initialize_fp( _destination ) \
935  { \
936   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
937  }
938#endif
939
940/* end of Context handler macros */
941
942/* Fatal Error manager macros */
943
944/*
945 *  This routine copies _error into a known place -- typically a stack
946 *  location or a register, optionally disables interrupts, and
947 *  halts/stops the CPU.
948 */
949
950#define _CPU_Fatal_halt( _error ) \
951  do { \
952    unsigned int _level; \
953    _CPU_ISR_Disable(_level); \
954    loop: goto loop; \
955  } while (0)
956
957
958extern void mips_break( int error );
959
960/* Bitfield handler macros */
961
962/*
963 *  This routine sets _output to the bit number of the first bit
964 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
965 *  This type may be either 16 or 32 bits wide although only the 16
966 *  least significant bits will be used.
967 *
968 *  There are a number of variables in using a "find first bit" type
969 *  instruction.
970 *
971 *    (1) What happens when run on a value of zero?
972 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
973 *    (3) The numbering may be zero or one based.
974 *    (4) The "find first bit" instruction may search from MSB or LSB.
975 *
976 *  RTEMS guarantees that (1) will never happen so it is not a concern.
977 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
978 *  _CPU_Priority_bits_index().  These three form a set of routines
979 *  which must logically operate together.  Bits in the _value are
980 *  set and cleared based on masks built by _CPU_Priority_mask().
981 *  The basic major and minor values calculated by _Priority_Major()
982 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
983 *  to properly range between the values returned by the "find first bit"
984 *  instruction.  This makes it possible for _Priority_Get_highest() to
985 *  calculate the major and directly index into the minor table.
986 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
987 *  is the first bit found.
988 *
989 *  This entire "find first bit" and mapping process depends heavily
990 *  on the manner in which a priority is broken into a major and minor
991 *  components with the major being the 4 MSB of a priority and minor
992 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
993 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
994 *  to the lowest priority.
995 *
996 *  If your CPU does not have a "find first bit" instruction, then
997 *  there are ways to make do without it.  Here are a handful of ways
998 *  to implement this in software:
999 *
1000 *    - a series of 16 bit test instructions
1001 *    - a "binary search using if's"
1002 *    - _number = 0
1003 *      if _value > 0x00ff
1004 *        _value >>=8
1005 *        _number = 8;
1006 *
1007 *      if _value > 0x0000f
1008 *        _value >=8
1009 *        _number += 4
1010 *
1011 *      _number += bit_set_table[ _value ]
1012 *
1013 *    where bit_set_table[ 16 ] has values which indicate the first
1014 *      bit set
1015 */
1016
1017#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
1018#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
1019
1020#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1021
1022#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1023  { \
1024    (_output) = 0;   /* do something to prevent warnings */ \
1025  }
1026
1027#endif
1028
1029/* end of Bitfield handler macros */
1030
1031/*
1032 *  This routine builds the mask which corresponds to the bit fields
1033 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
1034 *  for that routine.
1035 */
1036
1037#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1038
1039#define _CPU_Priority_Mask( _bit_number ) \
1040  ( 1 << (_bit_number) )
1041
1042#endif
1043
1044/*
1045 *  This routine translates the bit numbers returned by
1046 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
1047 *  a major or minor component of a priority.  See the discussion
1048 *  for that routine.
1049 */
1050
1051#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1052
1053#define _CPU_Priority_bits_index( _priority ) \
1054  (_priority)
1055
1056#endif
1057
1058/* end of Priority handler macros */
1059
1060/* functions */
1061
1062/*
1063 *  _CPU_Initialize
1064 *
1065 *  This routine performs CPU dependent initialization.
1066 */
1067
1068void _CPU_Initialize(
1069  rtems_cpu_table  *cpu_table,
1070  void      (*thread_dispatch)
1071);
1072
1073/*
1074 *  _CPU_ISR_install_raw_handler
1075 *
1076 *  This routine installs a "raw" interrupt handler directly into the
1077 *  processor's vector table.
1078 */
1079
1080void _CPU_ISR_install_raw_handler(
1081  uint32_t    vector,
1082  proc_ptr    new_handler,
1083  proc_ptr   *old_handler
1084);
1085
1086/*
1087 *  _CPU_ISR_install_vector
1088 *
1089 *  This routine installs an interrupt vector.
1090 */
1091
1092void _CPU_ISR_install_vector(
1093  uint32_t    vector,
1094  proc_ptr    new_handler,
1095  proc_ptr   *old_handler
1096);
1097
1098/*
1099 *  _CPU_Install_interrupt_stack
1100 *
1101 *  This routine installs the hardware interrupt stack pointer.
1102 *
1103 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1104 *         is TRUE.
1105 */
1106
1107void _CPU_Install_interrupt_stack( void );
1108
1109/*
1110 *  _CPU_Internal_threads_Idle_thread_body
1111 *
1112 *  This routine is the CPU dependent IDLE thread body.
1113 *
1114 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1115 *         is TRUE.
1116 */
1117
1118void _CPU_Thread_Idle_body( void );
1119
1120/*
1121 *  _CPU_Context_switch
1122 *
1123 *  This routine switches from the run context to the heir context.
1124 */
1125
1126void _CPU_Context_switch(
1127  Context_Control  *run,
1128  Context_Control  *heir
1129);
1130
1131/*
1132 *  _CPU_Context_restore
1133 *
1134 *  This routine is generally used only to restart self in an
1135 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1136 *
1137 *  NOTE: May be unnecessary to reload some registers.
1138 */
1139
1140void _CPU_Context_restore(
1141  Context_Control *new_context
1142);
1143
1144/*
1145 *  _CPU_Context_save_fp
1146 *
1147 *  This routine saves the floating point context passed to it.
1148 */
1149
1150void _CPU_Context_save_fp(
1151  void **fp_context_ptr
1152);
1153
1154/*
1155 *  _CPU_Context_restore_fp
1156 *
1157 *  This routine restores the floating point context passed to it.
1158 */
1159
1160void _CPU_Context_restore_fp(
1161  void **fp_context_ptr
1162);
1163
1164/*  The following routine swaps the endian format of an unsigned int.
1165 *  It must be static because it is referenced indirectly.
1166 *
1167 *  This version will work on any processor, but if there is a better
1168 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1169 *
1170 *     swap least significant two bytes with 16-bit rotate
1171 *     swap upper and lower 16-bits
1172 *     swap most significant two bytes with 16-bit rotate
1173 *
1174 *  Some CPUs have special instructions which swap a 32-bit quantity in
1175 *  a single instruction (e.g. i486).  It is probably best to avoid
1176 *  an "endian swapping control bit" in the CPU.  One good reason is
1177 *  that interrupts would probably have to be disabled to insure that
1178 *  an interrupt does not try to access the same "chunk" with the wrong
1179 *  endian.  Another good reason is that on some CPUs, the endian bit
1180 *  endianness for ALL fetches -- both code and data -- so the code
1181 *  will be fetched incorrectly.
1182 */
1183
1184static inline unsigned int CPU_swap_u32(
1185  unsigned int value
1186)
1187{
1188  uint32_t   byte1, byte2, byte3, byte4, swapped;
1189
1190  byte4 = (value >> 24) & 0xff;
1191  byte3 = (value >> 16) & 0xff;
1192  byte2 = (value >> 8)  & 0xff;
1193  byte1 =  value        & 0xff;
1194
1195  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1196  return( swapped );
1197}
1198
1199#define CPU_swap_u16( value ) \
1200  (((value&0xff) << 8) | ((value >> 8)&0xff))
1201
1202
1203#endif
1204
1205
1206
1207#ifdef __cplusplus
1208}
1209#endif
1210
1211#endif
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