source: rtems/cpukit/score/cpu/mips/rtems/score/cpu.h @ 27bfcd8

5
Last change on this file since 27bfcd8 was 27bfcd8, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 25, 2017 at 1:32:02 PM

score: Delete _CPU_Context_Fp_start()

Since the FP area pointer is passed by reference in
_CPU_Context_Initialize_fp() the optional FP area adjustment via
_CPU_Context_Fp_start() is superfluous. It is also wrong with respect
to memory management, e.g. pointer passed to _Workspace_Free() may be
not the one returned by _Workspace_Allocate().

Close #1400.

  • Property mode set to 100644
File size: 34.8 KB
Line 
1/**
2 *  @file
3 *
4 *  @brief Mips CPU Dependent Header File
5 */
6
7/*
8 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
9 *           Joel Sherrill <joel@OARcorp.com>.
10 *
11 *    These changes made the code conditional on standard cpp predefines,
12 *    merged the mips1 and mips3 code sequences as much as possible,
13 *    and moved some of the assembly code to C.  Alan did much of the
14 *    initial analysis and rework.  Joel took over from there and
15 *    wrote the JMR3904 BSP so this could be tested.  Joel also
16 *    added the new interrupt vectoring support in libcpu and
17 *    tried to better support the various interrupt controllers.
18 *
19 */
20
21/*
22 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
23 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
24 *
25 *    To anyone who acknowledges that this file is provided "AS IS"
26 *    without any express or implied warranty:
27 *      permission to use, copy, modify, and distribute this file
28 *      for any purpose is hereby granted without fee, provided that
29 *      the above copyright notice and this notice appears in all
30 *      copies, and that the name of Transition Networks not be used in
31 *      advertising or publicity pertaining to distribution of the
32 *      software without specific, written prior permission.
33 *      Transition Networks makes no representations about the suitability
34 *      of this software for any purpose.
35 *
36 *  COPYRIGHT (c) 1989-2012.
37 *  On-Line Applications Research Corporation (OAR).
38 *
39 *  The license and distribution terms for this file may be
40 *  found in the file LICENSE in this distribution or at
41 *  http://www.rtems.org/license/LICENSE.
42 */
43
44#ifndef _RTEMS_SCORE_CPU_H
45#define _RTEMS_SCORE_CPU_H
46
47/**
48 *  @defgroup ScoreCPU CPU CPU
49 *
50 *  @ingroup Score
51 *
52 */
53/**@{*/
54
55#ifdef __cplusplus
56extern "C" {
57#endif
58
59#include <rtems/score/types.h>
60#include <rtems/score/mips.h>
61
62/* conditional compilation parameters */
63
64/*
65 *  Does RTEMS manage a dedicated interrupt stack in software?
66 *
67 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
68 *  If FALSE, nothing is done.
69 *
70 *  If the CPU supports a dedicated interrupt stack in hardware,
71 *  then it is generally the responsibility of the BSP to allocate it
72 *  and set it up.
73 *
74 *  If the CPU does not support a dedicated interrupt stack, then
75 *  the porter has two options: (1) execute interrupts on the
76 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
77 *  interrupt stack.
78 *
79 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
80 *
81 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
82 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
83 *  possible that both are FALSE for a particular CPU.  Although it
84 *  is unclear what that would imply about the interrupt processing
85 *  procedure on that CPU.
86 */
87
88#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
89
90/*
91 *  Does the CPU follow the simple vectored interrupt model?
92 *
93 *  If TRUE, then RTEMS allocates the vector table it internally manages.
94 *  If FALSE, then the BSP is assumed to allocate and manage the vector
95 *  table
96 *
97 *  MIPS Specific Information:
98 *
99 *  Up to and including RTEMS 4.10, the MIPS port used simple vectored
100 *  interrupts. But this was changed to the PIC model after 4.10.
101 */
102#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
103
104/*
105 *  Does this CPU have hardware support for a dedicated interrupt stack?
106 *
107 *  If TRUE, then it must be installed during initialization.
108 *  If FALSE, then no installation is performed.
109 *
110 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
111 *
112 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
113 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
114 *  possible that both are FALSE for a particular CPU.  Although it
115 *  is unclear what that would imply about the interrupt processing
116 *  procedure on that CPU.
117 */
118
119#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
120
121/*
122 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
123 *
124 *  If TRUE, then the memory is allocated during initialization.
125 *  If FALSE, then the memory is allocated during initialization.
126 *
127 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
128 */
129
130#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
131
132/*
133 *  Does the RTEMS invoke the user's ISR with the vector number and
134 *  a pointer to the saved interrupt frame (1) or just the vector
135 *  number (0)?
136 *
137 */
138
139#define CPU_ISR_PASSES_FRAME_POINTER TRUE
140
141
142
143/*
144 *  Does the CPU have hardware floating point?
145 *
146 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
147 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
148 *
149 *  If there is a FP coprocessor such as the i387 or mc68881, then
150 *  the answer is TRUE.
151 *
152 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
153 *  It indicates whether or not this CPU model has FP support.  For
154 *  example, it would be possible to have an i386_nofp CPU model
155 *  which set this to false to indicate that you have an i386 without
156 *  an i387 and wish to leave floating point support out of RTEMS.
157 */
158
159#if ( MIPS_HAS_FPU == 1 )
160#define CPU_HARDWARE_FP     TRUE
161#else
162#define CPU_HARDWARE_FP     FALSE
163#endif
164
165/*
166 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
167 *
168 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
169 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
170 *
171 *  So far, the only CPU in which this option has been used is the
172 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
173 *  floating point registers to perform integer multiplies.  If
174 *  a function which you would not think utilize the FP unit DOES,
175 *  then one can not easily predict which tasks will use the FP hardware.
176 *  In this case, this option should be TRUE.
177 *
178 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
179 *
180 *  Mips Note: It appears the GCC can implicitly generate FPU
181 *  and Altivec instructions when you least expect them.  So make
182 *  all tasks floating point.
183 */
184
185#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
186
187/*
188 *  Should the IDLE task have a floating point context?
189 *
190 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
191 *  and it has a floating point context which is switched in and out.
192 *  If FALSE, then the IDLE task does not have a floating point context.
193 *
194 *  Setting this to TRUE negatively impacts the time required to preempt
195 *  the IDLE task from an interrupt because the floating point context
196 *  must be saved as part of the preemption.
197 */
198
199#define CPU_IDLE_TASK_IS_FP      FALSE
200
201/*
202 *  Should the saving of the floating point registers be deferred
203 *  until a context switch is made to another different floating point
204 *  task?
205 *
206 *  If TRUE, then the floating point context will not be stored until
207 *  necessary.  It will remain in the floating point registers and not
208 *  disturned until another floating point task is switched to.
209 *
210 *  If FALSE, then the floating point context is saved when a floating
211 *  point task is switched out and restored when the next floating point
212 *  task is restored.  The state of the floating point registers between
213 *  those two operations is not specified.
214 *
215 *  If the floating point context does NOT have to be saved as part of
216 *  interrupt dispatching, then it should be safe to set this to TRUE.
217 *
218 *  Setting this flag to TRUE results in using a different algorithm
219 *  for deciding when to save and restore the floating point context.
220 *  The deferred FP switch algorithm minimizes the number of times
221 *  the FP context is saved and restored.  The FP context is not saved
222 *  until a context switch is made to another, different FP task.
223 *  Thus in a system with only one FP task, the FP context will never
224 *  be saved or restored.
225 */
226
227#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
228
229#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
230
231/*
232 *  Does this port provide a CPU dependent IDLE task implementation?
233 *
234 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
235 *  must be provided and is the default IDLE thread body instead of
236 *  _Internal_threads_Idle_thread_body.
237 *
238 *  If FALSE, then use the generic IDLE thread body if the BSP does
239 *  not provide one.
240 *
241 *  This is intended to allow for supporting processors which have
242 *  a low power or idle mode.  When the IDLE thread is executed, then
243 *  the CPU can be powered down.
244 *
245 *  The order of precedence for selecting the IDLE thread body is:
246 *
247 *    1.  BSP provided
248 *    2.  CPU dependent (if provided)
249 *    3.  generic (if no BSP and no CPU dependent)
250 */
251
252/* we can use the low power wait instruction for the IDLE thread */
253#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
254
255/*
256 *  Does the stack grow up (toward higher addresses) or down
257 *  (toward lower addresses)?
258 *
259 *  If TRUE, then the grows upward.
260 *  If FALSE, then the grows toward smaller addresses.
261 */
262
263/* our stack grows down */
264#define CPU_STACK_GROWS_UP               FALSE
265
266/* FIXME: Is this the right value? */
267#define CPU_CACHE_LINE_BYTES 16
268
269#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
270
271/*
272 *  The following defines the number of bits actually used in the
273 *  interrupt field of the task mode.  How those bits map to the
274 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
275 */
276
277#define CPU_MODES_INTERRUPT_MASK   0x000000ff
278
279#define CPU_SIZEOF_POINTER 4
280
281#define CPU_MAXIMUM_PROCESSORS 32
282
283/*
284 *  Processor defined structures
285 *
286 *  Examples structures include the descriptor tables from the i386
287 *  and the processor control structure on the i960ca.
288 */
289
290/* may need to put some structures here.  */
291
292/*
293 * Contexts
294 *
295 *  Generally there are 2 types of context to save.
296 *     1. Interrupt registers to save
297 *     2. Task level registers to save
298 *
299 *  This means we have the following 3 context items:
300 *     1. task level context stuff::  Context_Control
301 *     2. floating point task stuff:: Context_Control_fp
302 *     3. special interrupt level context :: Context_Control_interrupt
303 *
304 *  On some processors, it is cost-effective to save only the callee
305 *  preserved registers during a task context switch.  This means
306 *  that the ISR code needs to save those registers which do not
307 *  persist across function calls.  It is not mandatory to make this
308 *  distinctions between the caller/callee saves registers for the
309 *  purpose of minimizing context saved during task switch and on interrupts.
310 *  If the cost of saving extra registers is minimal, simplicity is the
311 *  choice.  Save the same context on interrupt entry as for tasks in
312 *  this case.
313 *
314 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
315 *  care should be used in designing the context area.
316 *
317 *  On some CPUs with hardware floating point support, the Context_Control_fp
318 *  structure will not be used or it simply consist of an array of a
319 *  fixed number of bytes.   This is done when the floating point context
320 *  is dumped by a "FP save context" type instruction and the format
321 *  is not really defined by the CPU.  In this case, there is no need
322 *  to figure out the exact format -- only the size.  Of course, although
323 *  this is enough information for RTEMS, it is probably not enough for
324 *  a debugger such as gdb.  But that is another problem.
325 */
326
327#ifndef ASM
328
329/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
330#if (__mips == 1) || (__mips == 32)
331#define __MIPS_REGISTER_TYPE     uint32_t
332#define __MIPS_FPU_REGISTER_TYPE uint32_t
333#elif __mips == 3
334#define __MIPS_REGISTER_TYPE     uint64_t
335#define __MIPS_FPU_REGISTER_TYPE uint64_t
336#else
337#error "mips register size: unknown architecture level!!"
338#endif
339typedef struct {
340    __MIPS_REGISTER_TYPE s0;
341    __MIPS_REGISTER_TYPE s1;
342    __MIPS_REGISTER_TYPE s2;
343    __MIPS_REGISTER_TYPE s3;
344    __MIPS_REGISTER_TYPE s4;
345    __MIPS_REGISTER_TYPE s5;
346    __MIPS_REGISTER_TYPE s6;
347    __MIPS_REGISTER_TYPE s7;
348    __MIPS_REGISTER_TYPE sp;
349    __MIPS_REGISTER_TYPE fp;
350    __MIPS_REGISTER_TYPE ra;
351    __MIPS_REGISTER_TYPE c0_sr;
352    __MIPS_REGISTER_TYPE c0_epc;
353} Context_Control;
354
355#define _CPU_Context_Get_SP( _context ) \
356  (uintptr_t) (_context)->sp
357
358/* WARNING: If this structure is modified, the constants in cpu.h
359 *          must also be updated.
360 */
361
362typedef struct {
363#if ( CPU_HARDWARE_FP == TRUE )
364    __MIPS_FPU_REGISTER_TYPE fp0;
365    __MIPS_FPU_REGISTER_TYPE fp1;
366    __MIPS_FPU_REGISTER_TYPE fp2;
367    __MIPS_FPU_REGISTER_TYPE fp3;
368    __MIPS_FPU_REGISTER_TYPE fp4;
369    __MIPS_FPU_REGISTER_TYPE fp5;
370    __MIPS_FPU_REGISTER_TYPE fp6;
371    __MIPS_FPU_REGISTER_TYPE fp7;
372    __MIPS_FPU_REGISTER_TYPE fp8;
373    __MIPS_FPU_REGISTER_TYPE fp9;
374    __MIPS_FPU_REGISTER_TYPE fp10;
375    __MIPS_FPU_REGISTER_TYPE fp11;
376    __MIPS_FPU_REGISTER_TYPE fp12;
377    __MIPS_FPU_REGISTER_TYPE fp13;
378    __MIPS_FPU_REGISTER_TYPE fp14;
379    __MIPS_FPU_REGISTER_TYPE fp15;
380    __MIPS_FPU_REGISTER_TYPE fp16;
381    __MIPS_FPU_REGISTER_TYPE fp17;
382    __MIPS_FPU_REGISTER_TYPE fp18;
383    __MIPS_FPU_REGISTER_TYPE fp19;
384    __MIPS_FPU_REGISTER_TYPE fp20;
385    __MIPS_FPU_REGISTER_TYPE fp21;
386    __MIPS_FPU_REGISTER_TYPE fp22;
387    __MIPS_FPU_REGISTER_TYPE fp23;
388    __MIPS_FPU_REGISTER_TYPE fp24;
389    __MIPS_FPU_REGISTER_TYPE fp25;
390    __MIPS_FPU_REGISTER_TYPE fp26;
391    __MIPS_FPU_REGISTER_TYPE fp27;
392    __MIPS_FPU_REGISTER_TYPE fp28;
393    __MIPS_FPU_REGISTER_TYPE fp29;
394    __MIPS_FPU_REGISTER_TYPE fp30;
395    __MIPS_FPU_REGISTER_TYPE fp31;
396    uint32_t fpcs;
397#endif
398} Context_Control_fp;
399
400/*
401 *  This struct reflects the stack frame employed in ISR_Handler.  Note
402 *  that the ISR routine save some of the registers to this frame for
403 *  all interrupts and exceptions.  Other registers are saved only on
404 *  exceptions, while others are not touched at all.  The untouched
405 *  registers are not normally disturbed by high-level language
406 *  programs so they can be accessed when required.
407 *
408 *  The registers and their ordering in this struct must directly
409 *  correspond to the layout and ordering of * shown in iregdef.h,
410 *  as cpu_asm.S uses those definitions to fill the stack frame.
411 *  This struct provides access to the stack frame for C code.
412 *
413 *  Similarly, this structure is used by debugger stubs and exception
414 *  processing routines so be careful when changing the format.
415 *
416 *  NOTE: The comments with this structure and cpu_asm.S should be kept
417 *        in sync.  When in doubt, look in the  code to see if the
418 *        registers you're interested in are actually treated as expected.
419 *        The order of the first portion of this structure follows the
420 *        order of registers expected by gdb.
421 */
422
423typedef struct
424{
425  __MIPS_REGISTER_TYPE  r0;       /*  0 -- NOT FILLED IN */
426  __MIPS_REGISTER_TYPE  at;       /*  1 -- saved always */
427  __MIPS_REGISTER_TYPE  v0;       /*  2 -- saved always */
428  __MIPS_REGISTER_TYPE  v1;       /*  3 -- saved always */
429  __MIPS_REGISTER_TYPE  a0;       /*  4 -- saved always */
430  __MIPS_REGISTER_TYPE  a1;       /*  5 -- saved always */
431  __MIPS_REGISTER_TYPE  a2;       /*  6 -- saved always */
432  __MIPS_REGISTER_TYPE  a3;       /*  7 -- saved always */
433  __MIPS_REGISTER_TYPE  t0;       /*  8 -- saved always */
434  __MIPS_REGISTER_TYPE  t1;       /*  9 -- saved always */
435  __MIPS_REGISTER_TYPE  t2;       /* 10 -- saved always */
436  __MIPS_REGISTER_TYPE  t3;       /* 11 -- saved always */
437  __MIPS_REGISTER_TYPE  t4;       /* 12 -- saved always */
438  __MIPS_REGISTER_TYPE  t5;       /* 13 -- saved always */
439  __MIPS_REGISTER_TYPE  t6;       /* 14 -- saved always */
440  __MIPS_REGISTER_TYPE  t7;       /* 15 -- saved always */
441  __MIPS_REGISTER_TYPE  s0;       /* 16 -- saved on exceptions */
442  __MIPS_REGISTER_TYPE  s1;       /* 17 -- saved on exceptions */
443  __MIPS_REGISTER_TYPE  s2;       /* 18 -- saved on exceptions */
444  __MIPS_REGISTER_TYPE  s3;       /* 19 -- saved on exceptions */
445  __MIPS_REGISTER_TYPE  s4;       /* 20 -- saved on exceptions */
446  __MIPS_REGISTER_TYPE  s5;       /* 21 -- saved on exceptions */
447  __MIPS_REGISTER_TYPE  s6;       /* 22 -- saved on exceptions */
448  __MIPS_REGISTER_TYPE  s7;       /* 23 -- saved on exceptions */
449  __MIPS_REGISTER_TYPE  t8;       /* 24 -- saved always */
450  __MIPS_REGISTER_TYPE  t9;       /* 25 -- saved always */
451  __MIPS_REGISTER_TYPE  k0;       /* 26 -- NOT FILLED IN, kernel tmp reg */
452  __MIPS_REGISTER_TYPE  k1;       /* 27 -- NOT FILLED IN, kernel tmp reg */
453  __MIPS_REGISTER_TYPE  gp;       /* 28 -- saved always */
454  __MIPS_REGISTER_TYPE  sp;       /* 29 -- saved on exceptions NOT RESTORED */
455  __MIPS_REGISTER_TYPE  fp;       /* 30 -- saved always */
456  __MIPS_REGISTER_TYPE  ra;       /* 31 -- saved always */
457  __MIPS_REGISTER_TYPE  c0_sr;    /* 32 -- saved always, some bits are */
458                                  /*    manipulated per-thread          */
459  __MIPS_REGISTER_TYPE  mdlo;     /* 33 -- saved always */
460  __MIPS_REGISTER_TYPE  mdhi;     /* 34 -- saved always */
461  __MIPS_REGISTER_TYPE  badvaddr; /* 35 -- saved on exceptions, read-only */
462  __MIPS_REGISTER_TYPE  cause;    /* 36 -- saved on exceptions NOT restored */
463  __MIPS_REGISTER_TYPE  epc;      /* 37 -- saved always, read-only register */
464                                  /*        but logically restored */
465  __MIPS_FPU_REGISTER_TYPE f0;    /* 38 -- saved if FP enabled */
466  __MIPS_FPU_REGISTER_TYPE f1;    /* 39 -- saved if FP enabled */
467  __MIPS_FPU_REGISTER_TYPE f2;    /* 40 -- saved if FP enabled */
468  __MIPS_FPU_REGISTER_TYPE f3;    /* 41 -- saved if FP enabled */
469  __MIPS_FPU_REGISTER_TYPE f4;    /* 42 -- saved if FP enabled */
470  __MIPS_FPU_REGISTER_TYPE f5;    /* 43 -- saved if FP enabled */
471  __MIPS_FPU_REGISTER_TYPE f6;    /* 44 -- saved if FP enabled */
472  __MIPS_FPU_REGISTER_TYPE f7;    /* 45 -- saved if FP enabled */
473  __MIPS_FPU_REGISTER_TYPE f8;    /* 46 -- saved if FP enabled */
474  __MIPS_FPU_REGISTER_TYPE f9;    /* 47 -- saved if FP enabled */
475  __MIPS_FPU_REGISTER_TYPE f10;   /* 48 -- saved if FP enabled */
476  __MIPS_FPU_REGISTER_TYPE f11;   /* 49 -- saved if FP enabled */
477  __MIPS_FPU_REGISTER_TYPE f12;   /* 50 -- saved if FP enabled */
478  __MIPS_FPU_REGISTER_TYPE f13;   /* 51 -- saved if FP enabled */
479  __MIPS_FPU_REGISTER_TYPE f14;   /* 52 -- saved if FP enabled */
480  __MIPS_FPU_REGISTER_TYPE f15;   /* 53 -- saved if FP enabled */
481  __MIPS_FPU_REGISTER_TYPE f16;   /* 54 -- saved if FP enabled */
482  __MIPS_FPU_REGISTER_TYPE f17;   /* 55 -- saved if FP enabled */
483  __MIPS_FPU_REGISTER_TYPE f18;   /* 56 -- saved if FP enabled */
484  __MIPS_FPU_REGISTER_TYPE f19;   /* 57 -- saved if FP enabled */
485  __MIPS_FPU_REGISTER_TYPE f20;   /* 58 -- saved if FP enabled */
486  __MIPS_FPU_REGISTER_TYPE f21;   /* 59 -- saved if FP enabled */
487  __MIPS_FPU_REGISTER_TYPE f22;   /* 60 -- saved if FP enabled */
488  __MIPS_FPU_REGISTER_TYPE f23;   /* 61 -- saved if FP enabled */
489  __MIPS_FPU_REGISTER_TYPE f24;   /* 62 -- saved if FP enabled */
490  __MIPS_FPU_REGISTER_TYPE f25;   /* 63 -- saved if FP enabled */
491  __MIPS_FPU_REGISTER_TYPE f26;   /* 64 -- saved if FP enabled */
492  __MIPS_FPU_REGISTER_TYPE f27;   /* 65 -- saved if FP enabled */
493  __MIPS_FPU_REGISTER_TYPE f28;   /* 66 -- saved if FP enabled */
494  __MIPS_FPU_REGISTER_TYPE f29;   /* 67 -- saved if FP enabled */
495  __MIPS_FPU_REGISTER_TYPE f30;   /* 68 -- saved if FP enabled */
496  __MIPS_FPU_REGISTER_TYPE f31;   /* 69 -- saved if FP enabled */
497  __MIPS_REGISTER_TYPE     fcsr;  /* 70 -- saved on exceptions */
498                                  /*    (oddly not documented on MGV) */
499  __MIPS_REGISTER_TYPE     feir;  /* 71 -- saved on exceptions */
500                                  /*    (oddly not documented on MGV) */
501
502  /* GDB does not seem to care about anything past this point */
503
504  __MIPS_REGISTER_TYPE  tlbhi;    /* 72 - NOT FILLED IN, doesn't exist on */
505                                  /*         all MIPS CPUs (at least MGV) */
506#if __mips == 1
507  __MIPS_REGISTER_TYPE  tlblo;    /* 73 - NOT FILLED IN, doesn't exist on */
508                                  /*         all MIPS CPUs (at least MGV) */
509#endif
510#if  (__mips == 3) || (__mips == 32)
511  __MIPS_REGISTER_TYPE  tlblo0;   /* 73 - NOT FILLED IN, doesn't exist on */
512                                  /*         all MIPS CPUs (at least MGV) */
513#endif
514
515  __MIPS_REGISTER_TYPE  inx;      /* 74 -- NOT FILLED IN, doesn't exist on */
516                                  /*         all MIPS CPUs (at least MGV) */
517  __MIPS_REGISTER_TYPE  rand;     /* 75 -- NOT FILLED IN, doesn't exist on */
518                                  /*         all MIPS CPUs (at least MGV) */
519  __MIPS_REGISTER_TYPE  ctxt;     /* 76 -- NOT FILLED IN, doesn't exist on */
520                                  /*         all MIPS CPUs (at least MGV) */
521  __MIPS_REGISTER_TYPE  exctype;  /* 77 -- NOT FILLED IN (not enough info) */
522  __MIPS_REGISTER_TYPE  mode;     /* 78 -- NOT FILLED IN (not enough info) */
523  __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
524  __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
525  /* end of __mips == 1 so NREGS == 81 */
526#if  (__mips == 3) || (__mips == 32)
527  __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
528  __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
529  __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
530  __MIPS_REGISTER_TYPE  count;    /* 84 -- NOT FILLED IN */
531  __MIPS_REGISTER_TYPE  compare;  /* 85 -- NOT FILLED IN */
532  __MIPS_REGISTER_TYPE  config;   /* 86 -- NOT FILLED IN */
533  __MIPS_REGISTER_TYPE  lladdr;   /* 87 -- NOT FILLED IN */
534  __MIPS_REGISTER_TYPE  watchlo;  /* 88 -- NOT FILLED IN */
535  __MIPS_REGISTER_TYPE  watchhi;  /* 89 -- NOT FILLED IN */
536  __MIPS_REGISTER_TYPE  ecc;      /* 90 -- NOT FILLED IN */
537  __MIPS_REGISTER_TYPE  cacheerr; /* 91 -- NOT FILLED IN */
538  __MIPS_REGISTER_TYPE  taglo;    /* 92 -- NOT FILLED IN */
539  __MIPS_REGISTER_TYPE  taghi;    /* 93 -- NOT FILLED IN */
540  __MIPS_REGISTER_TYPE  errpc;    /* 94 -- NOT FILLED IN */
541  __MIPS_REGISTER_TYPE  xctxt;    /* 95 -- NOT FILLED IN */
542 /* end of __mips == 3 so NREGS == 96 */
543#endif
544
545} CPU_Interrupt_frame;
546
547typedef CPU_Interrupt_frame CPU_Exception_frame;
548
549/*
550 *  This variable is optional.  It is used on CPUs on which it is difficult
551 *  to generate an "uninitialized" FP context.  It is filled in by
552 *  _CPU_Initialize and copied into the task's FP context area during
553 *  _CPU_Context_Initialize.
554 */
555
556extern Context_Control_fp _CPU_Null_fp_context;
557
558/*
559 *  Nothing prevents the porter from declaring more CPU specific variables.
560 */
561
562/* XXX: if needed, put more variables here */
563
564/*
565 *  The size of the floating point context area.  On some CPUs this
566 *  will not be a "sizeof" because the format of the floating point
567 *  area is not defined -- only the size is.  This is usually on
568 *  CPUs with a "floating point save context" instruction.
569 */
570
571#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
572
573/*
574 *  Amount of extra stack (above minimum stack size) required by
575 *  system initialization thread.  Remember that in a multiprocessor
576 *  system the system intialization thread becomes the MP server thread.
577 */
578
579#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
580
581/*
582 *  Should be large enough to run all RTEMS tests.  This ensures
583 *  that a "reasonable" small application should not have any problems.
584 */
585
586#define CPU_STACK_MINIMUM_SIZE          (8 * 1024)
587
588/*
589 *  CPU's worst alignment requirement for data types on a byte boundary.  This
590 *  alignment does not take into account the requirements for the stack.
591 */
592
593#define CPU_ALIGNMENT              8
594
595/*
596 *  This number corresponds to the byte alignment requirement for the
597 *  heap handler.  This alignment requirement may be stricter than that
598 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
599 *  common for the heap to follow the same alignment requirement as
600 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
601 *  then this should be set to CPU_ALIGNMENT.
602 *
603 *  NOTE:  This does not have to be a power of 2.  It does have to
604 *         be greater or equal to than CPU_ALIGNMENT.
605 */
606
607#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
608
609/*
610 *  This number corresponds to the byte alignment requirement for memory
611 *  buffers allocated by the partition manager.  This alignment requirement
612 *  may be stricter than that for the data types alignment specified by
613 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
614 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
615 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
616 *
617 *  NOTE:  This does not have to be a power of 2.  It does have to
618 *         be greater or equal to than CPU_ALIGNMENT.
619 */
620
621#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
622
623/*
624 *  This number corresponds to the byte alignment requirement for the
625 *  stack.  This alignment requirement may be stricter than that for the
626 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
627 *  is strict enough for the stack, then this should be set to 0.
628 *
629 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
630 */
631
632#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
633
634void mips_vector_exceptions( CPU_Interrupt_frame *frame );
635
636/*
637 *  ISR handler macros
638 */
639
640/*
641 *  Declare the function that is present in the shared libcpu directory,
642 *  that returns the processor dependent interrupt mask.
643 */
644
645uint32_t mips_interrupt_mask( void );
646
647/*
648 *  Disable all interrupts for an RTEMS critical section.  The previous
649 *  level is returned in _level.
650 */
651
652#define _CPU_ISR_Disable( _level ) \
653  do { \
654    unsigned int _scratch; \
655    mips_get_sr( _scratch ); \
656    mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
657    _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
658  } while(0)
659
660/*
661 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
662 *  This indicates the end of an RTEMS critical section.  The parameter
663 *  _level is not modified.
664 */
665
666#define _CPU_ISR_Enable( _level )  \
667  do { \
668    unsigned int _scratch; \
669    mips_get_sr( _scratch ); \
670    mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
671  } while(0)
672
673/*
674 *  This temporarily restores the interrupt to _level before immediately
675 *  disabling them again.  This is used to divide long RTEMS critical
676 *  sections into two or more parts.  The parameter _level is not
677 *  modified.
678 */
679
680#define _CPU_ISR_Flash( _xlevel ) \
681  do { \
682    unsigned int _scratch2 = _xlevel; \
683    _CPU_ISR_Enable( _scratch2 ); \
684    _CPU_ISR_Disable( _scratch2 ); \
685    _xlevel = _scratch2; \
686  } while(0)
687
688RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
689{
690  return ( level & SR_INTERRUPT_ENABLE_BITS ) != 0;
691}
692
693/*
694 *  Map interrupt level in task mode onto the hardware that the CPU
695 *  actually provides.  Currently, interrupt levels which do not
696 *  map onto the CPU in a generic fashion are undefined.  Someday,
697 *  it would be nice if these were "mapped" by the application
698 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
699 *  8 - 255 would be available for bsp/application specific meaning.
700 *  This could be used to manage a programmable interrupt controller
701 *  via the rtems_task_mode directive.
702 *
703 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
704 *  manipulates the IEC.
705 */
706
707uint32_t   _CPU_ISR_Get_level( void );  /* in cpu.c */
708
709void _CPU_ISR_Set_level( uint32_t   );  /* in cpu.c */
710
711/* end of ISR handler macros */
712
713/* Context handler macros */
714
715/*
716 *  Initialize the context to a state suitable for starting a
717 *  task after a context restore operation.  Generally, this
718 *  involves:
719 *
720 *     - setting a starting address
721 *     - preparing the stack
722 *     - preparing the stack and frame pointers
723 *     - setting the proper interrupt level in the context
724 *     - initializing the floating point context
725 *
726 *  This routine generally does not set any unnecessary register
727 *  in the context.  The state of the "general data" registers is
728 *  undefined at task start time.
729 *
730 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
731 *        point thread.  This is typically only used on CPUs where the
732 *        FPU may be easily disabled by software such as on the SPARC
733 *        where the PSR contains an enable FPU bit.
734 *
735 *  The per-thread status register holds the interrupt enable, FP enable
736 *  and global interrupt enable for that thread.  It means each thread can
737 *  enable its own set of interrupts.  If interrupts are disabled, RTEMS
738 *  can still dispatch via blocking calls.  This is the function of the
739 *  "Interrupt Level", and on the MIPS, it controls the IEC bit and all
740 *  the hardware interrupts as defined in the SR.  Software ints
741 *  are automatically enabled for all threads, as they will only occur under
742 *  program control anyhow.  Besides, the interrupt level parm is only 8 bits,
743 *  and controlling the software ints plus the others would require 9.
744 *
745 *  If the Interrupt Level is 0, all ints are on.  Otherwise, the
746 *  Interrupt Level should supply a bit pattern to impose on the SR
747 *  interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6
748 *  apply to the SR register Intr bits from bit 10 thru bit 15.  Bit 7 of
749 *  the Interrupt Level parameter is unused at this time.
750 *
751 *  These are the only per-thread SR bits, the others are maintained
752 *  globally & explicitly preserved by the Context Switch code in cpu_asm.s
753 */
754
755
756#if (__mips == 3) || (__mips == 32)
757#define _INTON          SR_IE
758#if __mips_fpr==64
759#define _EXTRABITS      SR_FR
760#else
761#define _EXTRABITS      0
762#endif /* __mips_fpr==64 */
763#endif /* __mips == 3 */
764#if __mips == 1
765#define _INTON          SR_IEC
766#define _EXTRABITS      0  /* make sure we're in user mode on MIPS1 processors */
767#endif /* __mips == 1 */
768
769
770void _CPU_Context_Initialize(
771  Context_Control  *the_context,
772  uintptr_t        *stack_base,
773  uint32_t          size,
774  uint32_t          new_level,
775  void             *entry_point,
776  bool              is_fp,
777  void             *tls_area
778);
779
780
781/*
782 *  This routine is responsible for somehow restarting the currently
783 *  executing task.  If you are lucky, then all that is necessary
784 *  is restoring the context.  Otherwise, there will need to be
785 *  a special assembly routine which does something special in this
786 *  case.  Context_Restore should work most of the time.  It will
787 *  not work if restarting self conflicts with the stack frame
788 *  assumptions of restoring a context.
789 */
790
791#define _CPU_Context_Restart_self( _the_context ) \
792   _CPU_Context_restore( (_the_context) );
793
794/*
795 *  This routine initializes the FP context area passed to it to.
796 *  There are a few standard ways in which to initialize the
797 *  floating point context.  The code included for this macro assumes
798 *  that this is a CPU in which a "initial" FP context was saved into
799 *  _CPU_Null_fp_context and it simply copies it to the destination
800 *  context passed to it.
801 *
802 *  Other models include (1) not doing anything, and (2) putting
803 *  a "null FP status word" in the correct place in the FP context.
804 */
805
806#if ( CPU_HARDWARE_FP == TRUE )
807#define _CPU_Context_Initialize_fp( _destination ) \
808  { \
809   *(*(_destination)) = _CPU_Null_fp_context; \
810  }
811#endif
812
813/* end of Context handler macros */
814
815/* Fatal Error manager macros */
816
817/*
818 *  This routine copies _error into a known place -- typically a stack
819 *  location or a register, optionally disables interrupts, and
820 *  halts/stops the CPU.
821 */
822
823#define _CPU_Fatal_halt( _source, _error ) \
824  do { \
825    unsigned int _level; \
826    _CPU_ISR_Disable(_level); \
827    (void)_level; \
828    loop: goto loop; \
829  } while (0)
830
831
832extern void mips_break( int error );
833
834#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
835
836/* functions */
837
838/*
839 *  _CPU_Initialize
840 *
841 *  This routine performs CPU dependent initialization.
842 */
843
844void _CPU_Initialize(void);
845
846/*
847 *  _CPU_ISR_install_raw_handler
848 *
849 *  This routine installs a "raw" interrupt handler directly into the
850 *  processor's vector table.
851 */
852
853void _CPU_ISR_install_raw_handler(
854  uint32_t    vector,
855  proc_ptr    new_handler,
856  proc_ptr   *old_handler
857);
858
859/*
860 *  _CPU_ISR_install_vector
861 *
862 *  This routine installs an interrupt vector.
863 */
864
865void _CPU_ISR_install_vector(
866  uint32_t    vector,
867  proc_ptr    new_handler,
868  proc_ptr   *old_handler
869);
870
871/*
872 *  _CPU_Install_interrupt_stack
873 *
874 *  This routine installs the hardware interrupt stack pointer.
875 *
876 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
877 *         is TRUE.
878 */
879
880void _CPU_Install_interrupt_stack( void );
881
882/*
883 *  _CPU_Internal_threads_Idle_thread_body
884 *
885 *  This routine is the CPU dependent IDLE thread body.
886 *
887 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
888 *         is TRUE.
889 */
890
891void *_CPU_Thread_Idle_body( uintptr_t ignored );
892
893/*
894 *  _CPU_Context_switch
895 *
896 *  This routine switches from the run context to the heir context.
897 */
898
899void _CPU_Context_switch(
900  Context_Control  *run,
901  Context_Control  *heir
902);
903
904/*
905 *  _CPU_Context_restore
906 *
907 *  This routine is generally used only to restart self in an
908 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
909 *
910 *  NOTE: May be unnecessary to reload some registers.
911 */
912
913void _CPU_Context_restore(
914  Context_Control *new_context
915) RTEMS_NO_RETURN;
916
917/*
918 *  _CPU_Context_save_fp
919 *
920 *  This routine saves the floating point context passed to it.
921 */
922
923void _CPU_Context_save_fp(
924  Context_Control_fp **fp_context_ptr
925);
926
927/*
928 *  _CPU_Context_restore_fp
929 *
930 *  This routine restores the floating point context passed to it.
931 */
932
933void _CPU_Context_restore_fp(
934  Context_Control_fp **fp_context_ptr
935);
936
937static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
938{
939  /* TODO */
940}
941
942static inline void _CPU_Context_validate( uintptr_t pattern )
943{
944  while (1) {
945    /* TODO */
946  }
947}
948
949void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
950
951/*  The following routine swaps the endian format of an unsigned int.
952 *  It must be static because it is referenced indirectly.
953 *
954 *  This version will work on any processor, but if there is a better
955 *  way for your CPU PLEASE use it.  The most common way to do this is to:
956 *
957 *     swap least significant two bytes with 16-bit rotate
958 *     swap upper and lower 16-bits
959 *     swap most significant two bytes with 16-bit rotate
960 *
961 *  Some CPUs have special instructions which swap a 32-bit quantity in
962 *  a single instruction (e.g. i486).  It is probably best to avoid
963 *  an "endian swapping control bit" in the CPU.  One good reason is
964 *  that interrupts would probably have to be disabled to ensure that
965 *  an interrupt does not try to access the same "chunk" with the wrong
966 *  endian.  Another good reason is that on some CPUs, the endian bit
967 *  endianness for ALL fetches -- both code and data -- so the code
968 *  will be fetched incorrectly.
969 */
970
971static inline uint32_t CPU_swap_u32(
972  uint32_t value
973)
974{
975  uint32_t   byte1, byte2, byte3, byte4, swapped;
976
977  byte4 = (value >> 24) & 0xff;
978  byte3 = (value >> 16) & 0xff;
979  byte2 = (value >> 8)  & 0xff;
980  byte1 =  value        & 0xff;
981
982  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
983  return( swapped );
984}
985
986#define CPU_swap_u16( value ) \
987  (((value&0xff) << 8) | ((value >> 8)&0xff))
988
989typedef uint32_t CPU_Counter_ticks;
990
991CPU_Counter_ticks _CPU_Counter_read( void );
992
993static inline CPU_Counter_ticks _CPU_Counter_difference(
994  CPU_Counter_ticks second,
995  CPU_Counter_ticks first
996)
997{
998  return second - first;
999}
1000
1001#endif
1002
1003
1004
1005#ifdef __cplusplus
1006}
1007#endif
1008
1009/**@}*/
1010#endif
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