source: rtems/cpukit/score/cpu/mips/rtems/score/cpu.h @ 11f2bf59

4.104.114.84.95
Last change on this file since 11f2bf59 was 11f2bf59, checked in by Ralf Corsepius <ralf.corsepius@…>, on Aug 4, 2007 at 6:06:26 AM

2007-08-04 Ralf Corsépius <ralf.corsepius@…>

  • score/cpu/mips/rtems/score/cpu.h: Use uintptr_t instead of uint32_t.
  • Property mode set to 100644
File size: 43.4 KB
Line 
1/*
2 *  Mips CPU Dependent Header File
3 *
4 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
5 *           Joel Sherrill <joel@OARcorp.com>.
6 *
7 *    These changes made the code conditional on standard cpp predefines,
8 *    merged the mips1 and mips3 code sequences as much as possible,
9 *    and moved some of the assembly code to C.  Alan did much of the
10 *    initial analysis and rework.  Joel took over from there and
11 *    wrote the JMR3904 BSP so this could be tested.  Joel also
12 *    added the new interrupt vectoring support in libcpu and
13 *    tried to better support the various interrupt controllers.
14 *
15 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
16 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
17 *
18 *    To anyone who acknowledges that this file is provided "AS IS"
19 *    without any express or implied warranty:
20 *      permission to use, copy, modify, and distribute this file
21 *      for any purpose is hereby granted without fee, provided that
22 *      the above copyright notice and this notice appears in all
23 *      copies, and that the name of Transition Networks not be used in
24 *      advertising or publicity pertaining to distribution of the
25 *      software without specific, written prior permission.
26 *      Transition Networks makes no representations about the suitability
27 *      of this software for any purpose.
28 *
29 *  COPYRIGHT (c) 1989-2006.
30 *  On-Line Applications Research Corporation (OAR).
31 *
32 *  The license and distribution terms for this file may be
33 *  found in the file LICENSE in this distribution or at
34 *  http://www.rtems.com/license/LICENSE.
35 *
36 *  $Id$
37 */
38
39#ifndef _RTEMS_SCORE_CPU_H
40#define _RTEMS_SCORE_CPU_H
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
46#include <rtems/score/mips.h>       /* pick up machine definitions */
47#ifndef ASM
48#include <rtems/score/types.h>
49#endif
50
51#ifndef TRUE
52#define TRUE 1
53#endif
54#ifndef FALSE
55#define FALSE 0
56#endif
57
58
59/* conditional compilation parameters */
60
61/*
62 *  Should the calls to _Thread_Enable_dispatch be inlined?
63 *
64 *  If TRUE, then they are inlined.
65 *  If FALSE, then a subroutine call is made.
66 *
67 *  Basically this is an example of the classic trade-off of size
68 *  versus speed.  Inlining the call (TRUE) typically increases the
69 *  size of RTEMS while speeding up the enabling of dispatching.
70 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
71 *  only be 0 or 1 unless you are in an interrupt handler and that
72 *  interrupt handler invokes the executive.]  When not inlined
73 *  something calls _Thread_Enable_dispatch which in turns calls
74 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
75 *  one subroutine call is avoided entirely.]
76 */
77
78#define CPU_INLINE_ENABLE_DISPATCH       FALSE
79
80/*
81 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
82 *  be unrolled one time?  In unrolled each iteration of the loop examines
83 *  two "nodes" on the chain being searched.  Otherwise, only one node
84 *  is examined per iteration.
85 *
86 *  If TRUE, then the loops are unrolled.
87 *  If FALSE, then the loops are not unrolled.
88 *
89 *  The primary factor in making this decision is the cost of disabling
90 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
91 *  body of the loop.  On some CPUs, the flash is more expensive than
92 *  one iteration of the loop body.  In this case, it might be desirable
93 *  to unroll the loop.  It is important to note that on some CPUs, this
94 *  code is the longest interrupt disable period in RTEMS.  So it is
95 *  necessary to strike a balance when setting this parameter.
96 */
97
98#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
99
100/*
101 *  Does RTEMS manage a dedicated interrupt stack in software?
102 *
103 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
104 *  If FALSE, nothing is done.
105 *
106 *  If the CPU supports a dedicated interrupt stack in hardware,
107 *  then it is generally the responsibility of the BSP to allocate it
108 *  and set it up.
109 *
110 *  If the CPU does not support a dedicated interrupt stack, then
111 *  the porter has two options: (1) execute interrupts on the
112 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
113 *  interrupt stack.
114 *
115 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
116 *
117 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
118 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
119 *  possible that both are FALSE for a particular CPU.  Although it
120 *  is unclear what that would imply about the interrupt processing
121 *  procedure on that CPU.
122 */
123
124#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
125
126/*
127 *  Does this CPU have hardware support for a dedicated interrupt stack?
128 *
129 *  If TRUE, then it must be installed during initialization.
130 *  If FALSE, then no installation is performed.
131 *
132 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
133 *
134 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
135 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
136 *  possible that both are FALSE for a particular CPU.  Although it
137 *  is unclear what that would imply about the interrupt processing
138 *  procedure on that CPU.
139 */
140
141#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
142
143/*
144 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
145 *
146 *  If TRUE, then the memory is allocated during initialization.
147 *  If FALSE, then the memory is allocated during initialization.
148 *
149 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
150 */
151
152#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
153
154/*
155 *  Does the RTEMS invoke the user's ISR with the vector number and
156 *  a pointer to the saved interrupt frame (1) or just the vector
157 *  number (0)?
158 *
159 */
160
161#define CPU_ISR_PASSES_FRAME_POINTER 1
162
163
164
165/*
166 *  Does the CPU have hardware floating point?
167 *
168 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
169 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
170 *
171 *  If there is a FP coprocessor such as the i387 or mc68881, then
172 *  the answer is TRUE.
173 *
174 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
175 *  It indicates whether or not this CPU model has FP support.  For
176 *  example, it would be possible to have an i386_nofp CPU model
177 *  which set this to false to indicate that you have an i386 without
178 *  an i387 and wish to leave floating point support out of RTEMS.
179 */
180
181#if ( MIPS_HAS_FPU == 1 )
182#define CPU_HARDWARE_FP     TRUE
183#else
184#define CPU_HARDWARE_FP     FALSE
185#endif
186
187/*
188 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
189 *
190 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
191 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
192 *
193 *  So far, the only CPU in which this option has been used is the
194 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
195 *  floating point registers to perform integer multiplies.  If
196 *  a function which you would not think utilize the FP unit DOES,
197 *  then one can not easily predict which tasks will use the FP hardware.
198 *  In this case, this option should be TRUE.
199 *
200 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
201 */
202
203#define CPU_ALL_TASKS_ARE_FP    FALSE
204
205/*
206 *  Should the IDLE task have a floating point context?
207 *
208 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
209 *  and it has a floating point context which is switched in and out.
210 *  If FALSE, then the IDLE task does not have a floating point context.
211 *
212 *  Setting this to TRUE negatively impacts the time required to preempt
213 *  the IDLE task from an interrupt because the floating point context
214 *  must be saved as part of the preemption.
215 */
216
217#define CPU_IDLE_TASK_IS_FP      FALSE
218
219/*
220 *  Should the saving of the floating point registers be deferred
221 *  until a context switch is made to another different floating point
222 *  task?
223 *
224 *  If TRUE, then the floating point context will not be stored until
225 *  necessary.  It will remain in the floating point registers and not
226 *  disturned until another floating point task is switched to.
227 *
228 *  If FALSE, then the floating point context is saved when a floating
229 *  point task is switched out and restored when the next floating point
230 *  task is restored.  The state of the floating point registers between
231 *  those two operations is not specified.
232 *
233 *  If the floating point context does NOT have to be saved as part of
234 *  interrupt dispatching, then it should be safe to set this to TRUE.
235 *
236 *  Setting this flag to TRUE results in using a different algorithm
237 *  for deciding when to save and restore the floating point context.
238 *  The deferred FP switch algorithm minimizes the number of times
239 *  the FP context is saved and restored.  The FP context is not saved
240 *  until a context switch is made to another, different FP task.
241 *  Thus in a system with only one FP task, the FP context will never
242 *  be saved or restored.
243 */
244
245#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
246
247/*
248 *  Does this port provide a CPU dependent IDLE task implementation?
249 *
250 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
251 *  must be provided and is the default IDLE thread body instead of
252 *  _Internal_threads_Idle_thread_body.
253 *
254 *  If FALSE, then use the generic IDLE thread body if the BSP does
255 *  not provide one.
256 *
257 *  This is intended to allow for supporting processors which have
258 *  a low power or idle mode.  When the IDLE thread is executed, then
259 *  the CPU can be powered down.
260 *
261 *  The order of precedence for selecting the IDLE thread body is:
262 *
263 *    1.  BSP provided
264 *    2.  CPU dependent (if provided)
265 *    3.  generic (if no BSP and no CPU dependent)
266 */
267
268/* we can use the low power wait instruction for the IDLE thread */
269#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
270
271/*
272 *  Does the stack grow up (toward higher addresses) or down
273 *  (toward lower addresses)?
274 *
275 *  If TRUE, then the grows upward.
276 *  If FALSE, then the grows toward smaller addresses.
277 */
278
279/* our stack grows down */
280#define CPU_STACK_GROWS_UP               FALSE
281
282/*
283 *  The following is the variable attribute used to force alignment
284 *  of critical RTEMS structures.  On some processors it may make
285 *  sense to have these aligned on tighter boundaries than
286 *  the minimum requirements of the compiler in order to have as
287 *  much of the critical data area as possible in a cache line.
288 *
289 *  The placement of this macro in the declaration of the variables
290 *  is based on the syntactically requirements of the GNU C
291 *  "__attribute__" extension.  For example with GNU C, use
292 *  the following to force a structures to a 32 byte boundary.
293 *
294 *      __attribute__ ((aligned (32)))
295 *
296 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
297 *         To benefit from using this, the data must be heavily
298 *         used so it will stay in the cache and used frequently enough
299 *         in the executive to justify turning this on.
300 */
301
302/* our cache line size is 16 bytes */
303#if __GNUC__
304#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
305#else
306#define CPU_STRUCTURE_ALIGNMENT
307#endif
308
309/*
310 *  Define what is required to specify how the network to host conversion
311 *  routines are handled.
312 */
313
314/* __MIPSEB__ or __MIPSEL__ is defined by GCC based on -EB or -EL command line options */
315#if defined(__MIPSEB__)
316#define CPU_BIG_ENDIAN                           TRUE
317#define CPU_LITTLE_ENDIAN                        FALSE
318#elif defined(__MIPSEL__)
319#define CPU_BIG_ENDIAN                           FALSE
320#define CPU_LITTLE_ENDIAN                        TRUE
321#else
322#error "Unknown endianness"
323#endif
324
325/*
326 *  The following defines the number of bits actually used in the
327 *  interrupt field of the task mode.  How those bits map to the
328 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
329 */
330
331#define CPU_MODES_INTERRUPT_MASK   0x000000ff
332
333/*
334 *  Processor defined structures
335 *
336 *  Examples structures include the descriptor tables from the i386
337 *  and the processor control structure on the i960ca.
338 */
339
340/* may need to put some structures here.  */
341
342/*
343 * Contexts
344 *
345 *  Generally there are 2 types of context to save.
346 *     1. Interrupt registers to save
347 *     2. Task level registers to save
348 *
349 *  This means we have the following 3 context items:
350 *     1. task level context stuff::  Context_Control
351 *     2. floating point task stuff:: Context_Control_fp
352 *     3. special interrupt level context :: Context_Control_interrupt
353 *
354 *  On some processors, it is cost-effective to save only the callee
355 *  preserved registers during a task context switch.  This means
356 *  that the ISR code needs to save those registers which do not
357 *  persist across function calls.  It is not mandatory to make this
358 *  distinctions between the caller/callee saves registers for the
359 *  purpose of minimizing context saved during task switch and on interrupts.
360 *  If the cost of saving extra registers is minimal, simplicity is the
361 *  choice.  Save the same context on interrupt entry as for tasks in
362 *  this case.
363 *
364 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
365 *  care should be used in designing the context area.
366 *
367 *  On some CPUs with hardware floating point support, the Context_Control_fp
368 *  structure will not be used or it simply consist of an array of a
369 *  fixed number of bytes.   This is done when the floating point context
370 *  is dumped by a "FP save context" type instruction and the format
371 *  is not really defined by the CPU.  In this case, there is no need
372 *  to figure out the exact format -- only the size.  Of course, although
373 *  this is enough information for RTEMS, it is probably not enough for
374 *  a debugger such as gdb.  But that is another problem.
375 */
376
377#ifndef ASSEMBLY_ONLY
378
379/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
380#if (__mips == 1) || (__mips == 32)
381#define __MIPS_REGISTER_TYPE     uint32_t 
382#define __MIPS_FPU_REGISTER_TYPE uint32_t 
383#elif __mips == 3
384#define __MIPS_REGISTER_TYPE     uint64_t 
385#define __MIPS_FPU_REGISTER_TYPE uint64_t 
386#else
387#error "mips register size: unknown architecture level!!"
388#endif
389typedef struct {
390    __MIPS_REGISTER_TYPE s0;
391    __MIPS_REGISTER_TYPE s1;
392    __MIPS_REGISTER_TYPE s2;
393    __MIPS_REGISTER_TYPE s3;
394    __MIPS_REGISTER_TYPE s4;
395    __MIPS_REGISTER_TYPE s5;
396    __MIPS_REGISTER_TYPE s6;
397    __MIPS_REGISTER_TYPE s7;
398    __MIPS_REGISTER_TYPE sp;
399    __MIPS_REGISTER_TYPE fp;
400    __MIPS_REGISTER_TYPE ra;
401    __MIPS_REGISTER_TYPE c0_sr;
402    __MIPS_REGISTER_TYPE c0_epc;
403} Context_Control;
404
405/* WARNING: If this structure is modified, the constants in cpu.h
406 *          must also be updated.
407 */
408
409typedef struct {
410#if ( CPU_HARDWARE_FP == TRUE )
411    __MIPS_FPU_REGISTER_TYPE fp0;
412    __MIPS_FPU_REGISTER_TYPE fp1;
413    __MIPS_FPU_REGISTER_TYPE fp2;
414    __MIPS_FPU_REGISTER_TYPE fp3;
415    __MIPS_FPU_REGISTER_TYPE fp4;
416    __MIPS_FPU_REGISTER_TYPE fp5;
417    __MIPS_FPU_REGISTER_TYPE fp6;
418    __MIPS_FPU_REGISTER_TYPE fp7;
419    __MIPS_FPU_REGISTER_TYPE fp8;
420    __MIPS_FPU_REGISTER_TYPE fp9;
421    __MIPS_FPU_REGISTER_TYPE fp10;
422    __MIPS_FPU_REGISTER_TYPE fp11;
423    __MIPS_FPU_REGISTER_TYPE fp12;
424    __MIPS_FPU_REGISTER_TYPE fp13;
425    __MIPS_FPU_REGISTER_TYPE fp14;
426    __MIPS_FPU_REGISTER_TYPE fp15;
427    __MIPS_FPU_REGISTER_TYPE fp16;
428    __MIPS_FPU_REGISTER_TYPE fp17;
429    __MIPS_FPU_REGISTER_TYPE fp18;
430    __MIPS_FPU_REGISTER_TYPE fp19;
431    __MIPS_FPU_REGISTER_TYPE fp20;
432    __MIPS_FPU_REGISTER_TYPE fp21;
433    __MIPS_FPU_REGISTER_TYPE fp22;
434    __MIPS_FPU_REGISTER_TYPE fp23;
435    __MIPS_FPU_REGISTER_TYPE fp24;
436    __MIPS_FPU_REGISTER_TYPE fp25;
437    __MIPS_FPU_REGISTER_TYPE fp26;
438    __MIPS_FPU_REGISTER_TYPE fp27;
439    __MIPS_FPU_REGISTER_TYPE fp28;
440    __MIPS_FPU_REGISTER_TYPE fp29;
441    __MIPS_FPU_REGISTER_TYPE fp30;
442    __MIPS_FPU_REGISTER_TYPE fp31;
443    uint32_t fpcs;
444#endif
445} Context_Control_fp;
446
447/*
448 *  This struct reflects the stack frame employed in ISR_Handler.  Note
449 *  that the ISR routine save some of the registers to this frame for
450 *  all interrupts and exceptions.  Other registers are saved only on
451 *  exceptions, while others are not touched at all.  The untouched
452 *  registers are not normally disturbed by high-level language
453 *  programs so they can be accessed when required.
454 *
455 *  The registers and their ordering in this struct must directly
456 *  correspond to the layout and ordering of * shown in iregdef.h,
457 *  as cpu_asm.S uses those definitions to fill the stack frame. 
458 *  This struct provides access to the stack frame for C code.
459 *
460 *  Similarly, this structure is used by debugger stubs and exception
461 *  processing routines so be careful when changing the format.
462 *
463 *  NOTE: The comments with this structure and cpu_asm.S should be kept
464 *        in sync.  When in doubt, look in the  code to see if the
465 *        registers you're interested in are actually treated as expected.
466 *        The order of the first portion of this structure follows the
467 *        order of registers expected by gdb.
468 */
469
470typedef struct
471{
472  __MIPS_REGISTER_TYPE  r0;       /*  0 -- NOT FILLED IN */
473  __MIPS_REGISTER_TYPE  at;       /*  1 -- saved always */
474  __MIPS_REGISTER_TYPE  v0;       /*  2 -- saved always */
475  __MIPS_REGISTER_TYPE  v1;       /*  3 -- saved always */
476  __MIPS_REGISTER_TYPE  a0;       /*  4 -- saved always */
477  __MIPS_REGISTER_TYPE  a1;       /*  5 -- saved always */
478  __MIPS_REGISTER_TYPE  a2;       /*  6 -- saved always */
479  __MIPS_REGISTER_TYPE  a3;       /*  7 -- saved always */
480  __MIPS_REGISTER_TYPE  t0;       /*  8 -- saved always */
481  __MIPS_REGISTER_TYPE  t1;       /*  9 -- saved always */
482  __MIPS_REGISTER_TYPE  t2;       /* 10 -- saved always */
483  __MIPS_REGISTER_TYPE  t3;       /* 11 -- saved always */
484  __MIPS_REGISTER_TYPE  t4;       /* 12 -- saved always */
485  __MIPS_REGISTER_TYPE  t5;       /* 13 -- saved always */
486  __MIPS_REGISTER_TYPE  t6;       /* 14 -- saved always */
487  __MIPS_REGISTER_TYPE  t7;       /* 15 -- saved always */
488  __MIPS_REGISTER_TYPE  s0;       /* 16 -- saved on exceptions */
489  __MIPS_REGISTER_TYPE  s1;       /* 17 -- saved on exceptions */
490  __MIPS_REGISTER_TYPE  s2;       /* 18 -- saved on exceptions */
491  __MIPS_REGISTER_TYPE  s3;       /* 19 -- saved on exceptions */
492  __MIPS_REGISTER_TYPE  s4;       /* 20 -- saved on exceptions */
493  __MIPS_REGISTER_TYPE  s5;       /* 21 -- saved on exceptions */
494  __MIPS_REGISTER_TYPE  s6;       /* 22 -- saved on exceptions */
495  __MIPS_REGISTER_TYPE  s7;       /* 23 -- saved on exceptions */
496  __MIPS_REGISTER_TYPE  t8;       /* 24 -- saved always */
497  __MIPS_REGISTER_TYPE  t9;       /* 25 -- saved always */
498  __MIPS_REGISTER_TYPE  k0;       /* 26 -- NOT FILLED IN, kernel tmp reg */
499  __MIPS_REGISTER_TYPE  k1;       /* 27 -- NOT FILLED IN, kernel tmp reg */
500  __MIPS_REGISTER_TYPE  gp;       /* 28 -- saved always */
501  __MIPS_REGISTER_TYPE  sp;       /* 29 -- saved on exceptions NOT RESTORED */
502  __MIPS_REGISTER_TYPE  fp;       /* 30 -- saved always */
503  __MIPS_REGISTER_TYPE  ra;       /* 31 -- saved always */
504  __MIPS_REGISTER_TYPE  c0_sr;    /* 32 -- saved always, some bits are */
505                                  /*    manipulated per-thread          */
506  __MIPS_REGISTER_TYPE  mdlo;     /* 33 -- saved always */
507  __MIPS_REGISTER_TYPE  mdhi;     /* 34 -- saved always */
508  __MIPS_REGISTER_TYPE  badvaddr; /* 35 -- saved on exceptions, read-only */
509  __MIPS_REGISTER_TYPE  cause;    /* 36 -- saved on exceptions NOT restored */
510  __MIPS_REGISTER_TYPE  epc;      /* 37 -- saved always, read-only register */
511                                  /*        but logically restored */
512  __MIPS_FPU_REGISTER_TYPE f0;    /* 38 -- saved if FP enabled */
513  __MIPS_FPU_REGISTER_TYPE f1;    /* 39 -- saved if FP enabled */
514  __MIPS_FPU_REGISTER_TYPE f2;    /* 40 -- saved if FP enabled */
515  __MIPS_FPU_REGISTER_TYPE f3;    /* 41 -- saved if FP enabled */
516  __MIPS_FPU_REGISTER_TYPE f4;    /* 42 -- saved if FP enabled */
517  __MIPS_FPU_REGISTER_TYPE f5;    /* 43 -- saved if FP enabled */
518  __MIPS_FPU_REGISTER_TYPE f6;    /* 44 -- saved if FP enabled */
519  __MIPS_FPU_REGISTER_TYPE f7;    /* 45 -- saved if FP enabled */
520  __MIPS_FPU_REGISTER_TYPE f8;    /* 46 -- saved if FP enabled */
521  __MIPS_FPU_REGISTER_TYPE f9;    /* 47 -- saved if FP enabled */
522  __MIPS_FPU_REGISTER_TYPE f10;   /* 48 -- saved if FP enabled */
523  __MIPS_FPU_REGISTER_TYPE f11;   /* 49 -- saved if FP enabled */
524  __MIPS_FPU_REGISTER_TYPE f12;   /* 50 -- saved if FP enabled */
525  __MIPS_FPU_REGISTER_TYPE f13;   /* 51 -- saved if FP enabled */
526  __MIPS_FPU_REGISTER_TYPE f14;   /* 52 -- saved if FP enabled */
527  __MIPS_FPU_REGISTER_TYPE f15;   /* 53 -- saved if FP enabled */
528  __MIPS_FPU_REGISTER_TYPE f16;   /* 54 -- saved if FP enabled */
529  __MIPS_FPU_REGISTER_TYPE f17;   /* 55 -- saved if FP enabled */
530  __MIPS_FPU_REGISTER_TYPE f18;   /* 56 -- saved if FP enabled */
531  __MIPS_FPU_REGISTER_TYPE f19;   /* 57 -- saved if FP enabled */
532  __MIPS_FPU_REGISTER_TYPE f20;   /* 58 -- saved if FP enabled */
533  __MIPS_FPU_REGISTER_TYPE f21;   /* 59 -- saved if FP enabled */
534  __MIPS_FPU_REGISTER_TYPE f22;   /* 60 -- saved if FP enabled */
535  __MIPS_FPU_REGISTER_TYPE f23;   /* 61 -- saved if FP enabled */
536  __MIPS_FPU_REGISTER_TYPE f24;   /* 62 -- saved if FP enabled */
537  __MIPS_FPU_REGISTER_TYPE f25;   /* 63 -- saved if FP enabled */
538  __MIPS_FPU_REGISTER_TYPE f26;   /* 64 -- saved if FP enabled */
539  __MIPS_FPU_REGISTER_TYPE f27;   /* 65 -- saved if FP enabled */
540  __MIPS_FPU_REGISTER_TYPE f28;   /* 66 -- saved if FP enabled */
541  __MIPS_FPU_REGISTER_TYPE f29;   /* 67 -- saved if FP enabled */
542  __MIPS_FPU_REGISTER_TYPE f30;   /* 68 -- saved if FP enabled */
543  __MIPS_FPU_REGISTER_TYPE f31;   /* 69 -- saved if FP enabled */
544  __MIPS_REGISTER_TYPE     fcsr;  /* 70 -- saved on exceptions */
545                                  /*    (oddly not documented on MGV) */
546  __MIPS_REGISTER_TYPE     feir;  /* 71 -- saved on exceptions */
547                                  /*    (oddly not documented on MGV) */
548
549  /* GDB does not seem to care about anything past this point */
550
551  __MIPS_REGISTER_TYPE  tlbhi;    /* 72 - NOT FILLED IN, doesn't exist on */
552                                  /*         all MIPS CPUs (at least MGV) */
553#if __mips == 1
554  __MIPS_REGISTER_TYPE  tlblo;    /* 73 - NOT FILLED IN, doesn't exist on */
555                                  /*         all MIPS CPUs (at least MGV) */
556#endif
557#if  (__mips == 3) || (__mips == 32)
558  __MIPS_REGISTER_TYPE  tlblo0;   /* 73 - NOT FILLED IN, doesn't exist on */
559                                  /*         all MIPS CPUs (at least MGV) */
560#endif
561
562  __MIPS_REGISTER_TYPE  inx;      /* 74 -- NOT FILLED IN, doesn't exist on */
563                                  /*         all MIPS CPUs (at least MGV) */
564  __MIPS_REGISTER_TYPE  rand;     /* 75 -- NOT FILLED IN, doesn't exist on */
565                                  /*         all MIPS CPUs (at least MGV) */
566  __MIPS_REGISTER_TYPE  ctxt;     /* 76 -- NOT FILLED IN, doesn't exist on */
567                                  /*         all MIPS CPUs (at least MGV) */
568  __MIPS_REGISTER_TYPE  exctype;  /* 77 -- NOT FILLED IN (not enough info) */
569  __MIPS_REGISTER_TYPE  mode;     /* 78 -- NOT FILLED IN (not enough info) */
570  __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
571  __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
572  /* end of __mips == 1 so NREGS == 81 */
573#if  (__mips == 3) || (__mips == 32)
574  __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
575  __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
576  __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
577  __MIPS_REGISTER_TYPE  count;    /* 84 -- NOT FILLED IN */
578  __MIPS_REGISTER_TYPE  compare;  /* 85 -- NOT FILLED IN */
579  __MIPS_REGISTER_TYPE  config;   /* 86 -- NOT FILLED IN */
580  __MIPS_REGISTER_TYPE  lladdr;   /* 87 -- NOT FILLED IN */
581  __MIPS_REGISTER_TYPE  watchlo;  /* 88 -- NOT FILLED IN */
582  __MIPS_REGISTER_TYPE  watchhi;  /* 89 -- NOT FILLED IN */
583  __MIPS_REGISTER_TYPE  ecc;      /* 90 -- NOT FILLED IN */
584  __MIPS_REGISTER_TYPE  cacheerr; /* 91 -- NOT FILLED IN */
585  __MIPS_REGISTER_TYPE  taglo;    /* 92 -- NOT FILLED IN */
586  __MIPS_REGISTER_TYPE  taghi;    /* 93 -- NOT FILLED IN */
587  __MIPS_REGISTER_TYPE  errpc;    /* 94 -- NOT FILLED IN */
588  __MIPS_REGISTER_TYPE  xctxt;    /* 95 -- NOT FILLED IN */
589 /* end of __mips == 3 so NREGS == 96 */
590#endif
591
592} CPU_Interrupt_frame;
593
594
595/*
596 *  The following table contains the information required to configure
597 *  the mips processor specific parameters.
598 */
599
600typedef struct {
601  void       (*pretasking_hook)( void );
602  void       (*predriver_hook)( void );
603  void       (*postdriver_hook)( void );
604  void       (*idle_task)( void );
605  boolean      do_zero_of_workspace;
606  uint32_t     idle_task_stack_size;
607  uint32_t     interrupt_stack_size;
608  uint32_t     extra_mpci_receive_server_stack;
609  void *     (*stack_allocate_hook)( uint32_t   );
610  void       (*stack_free_hook)( void* );
611  /* end of fields required on all CPUs */
612
613  uint32_t     clicks_per_microsecond;
614}   rtems_cpu_table;
615
616
617/*
618 *  Macros to access required entires in the CPU Table are in
619 *  the file rtems/system.h.
620 */
621
622/*
623 *  Macros to access MIPS specific additions to the CPU Table
624 */
625
626#define rtems_cpu_configuration_get_clicks_per_microsecond() \
627   (_CPU_Table.clicks_per_microsecond)
628
629/*
630 *  This variable is optional.  It is used on CPUs on which it is difficult
631 *  to generate an "uninitialized" FP context.  It is filled in by
632 *  _CPU_Initialize and copied into the task's FP context area during
633 *  _CPU_Context_Initialize.
634 */
635
636SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
637
638/*
639 *  On some CPUs, RTEMS supports a software managed interrupt stack.
640 *  This stack is allocated by the Interrupt Manager and the switch
641 *  is performed in _ISR_Handler.  These variables contain pointers
642 *  to the lowest and highest addresses in the chunk of memory allocated
643 *  for the interrupt stack.  Since it is unknown whether the stack
644 *  grows up or down (in general), this give the CPU dependent
645 *  code the option of picking the version it wants to use.
646 *
647 *  NOTE: These two variables are required if the macro
648 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
649 */
650
651SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
652SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
653
654/*
655 *  With some compilation systems, it is difficult if not impossible to
656 *  call a high-level language routine from assembly language.  This
657 *  is especially true of commercial Ada compilers and name mangling
658 *  C++ ones.  This variable can be optionally defined by the CPU porter
659 *  and contains the address of the routine _Thread_Dispatch.  This
660 *  can make it easier to invoke that routine at the end of the interrupt
661 *  sequence (if a dispatch is necessary).
662 *
663
664SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
665 *
666 *  NOTE: Not needed on this port.
667 */
668
669
670
671/*
672 *  Nothing prevents the porter from declaring more CPU specific variables.
673 */
674
675/* XXX: if needed, put more variables here */
676
677/*
678 *  The size of the floating point context area.  On some CPUs this
679 *  will not be a "sizeof" because the format of the floating point
680 *  area is not defined -- only the size is.  This is usually on
681 *  CPUs with a "floating point save context" instruction.
682 */
683
684#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
685
686/*
687 *  Amount of extra stack (above minimum stack size) required by
688 *  system initialization thread.  Remember that in a multiprocessor
689 *  system the system intialization thread becomes the MP server thread.
690 */
691
692#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
693
694/*
695 *  This defines the number of entries in the ISR_Vector_table managed
696 *  by RTEMS.
697 */
698
699extern unsigned int mips_interrupt_number_of_vectors;
700#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (mips_interrupt_number_of_vectors)
701#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
702
703/*
704 *  Should be large enough to run all RTEMS tests.  This ensures
705 *  that a "reasonable" small application should not have any problems.
706 */
707
708#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(uint32_t))
709
710
711/*
712 *  CPU's worst alignment requirement for data types on a byte boundary.  This
713 *  alignment does not take into account the requirements for the stack.
714 */
715
716#define CPU_ALIGNMENT              8
717
718/*
719 *  This number corresponds to the byte alignment requirement for the
720 *  heap handler.  This alignment requirement may be stricter than that
721 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
722 *  common for the heap to follow the same alignment requirement as
723 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
724 *  then this should be set to CPU_ALIGNMENT.
725 *
726 *  NOTE:  This does not have to be a power of 2.  It does have to
727 *         be greater or equal to than CPU_ALIGNMENT.
728 */
729
730#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
731
732/*
733 *  This number corresponds to the byte alignment requirement for memory
734 *  buffers allocated by the partition manager.  This alignment requirement
735 *  may be stricter than that for the data types alignment specified by
736 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
737 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
738 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
739 *
740 *  NOTE:  This does not have to be a power of 2.  It does have to
741 *         be greater or equal to than CPU_ALIGNMENT.
742 */
743
744#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
745
746/*
747 *  This number corresponds to the byte alignment requirement for the
748 *  stack.  This alignment requirement may be stricter than that for the
749 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
750 *  is strict enough for the stack, then this should be set to 0.
751 *
752 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
753 */
754
755#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
756
757/*
758 *  ISR handler macros
759 */
760
761/*
762 *  Support routine to initialize the RTEMS vector table after it is allocated.
763 */
764
765#define _CPU_Initialize_vectors()
766
767/*
768 *  Declare the function that is present in the shared libcpu directory,
769 *  that returns the processor dependent interrupt mask.
770 */
771
772uint32_t mips_interrupt_mask( void );
773
774/*
775 *  Disable all interrupts for an RTEMS critical section.  The previous
776 *  level is returned in _level.
777 */
778
779#define _CPU_ISR_Disable( _level ) \
780  do { \
781    unsigned int _scratch; \
782    mips_get_sr( _scratch ); \
783    mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
784    _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
785  } while(0)
786
787/*
788 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
789 *  This indicates the end of an RTEMS critical section.  The parameter
790 *  _level is not modified.
791 */
792
793#define _CPU_ISR_Enable( _level )  \
794  do { \
795    unsigned int _scratch; \
796    mips_get_sr( _scratch ); \
797    mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
798  } while(0)
799
800/*
801 *  This temporarily restores the interrupt to _level before immediately
802 *  disabling them again.  This is used to divide long RTEMS critical
803 *  sections into two or more parts.  The parameter _level is not
804 *  modified.
805 */
806
807#define _CPU_ISR_Flash( _xlevel ) \
808  do { \
809    unsigned int _scratch2 = _xlevel; \
810    _CPU_ISR_Enable( _scratch2 ); \
811    _CPU_ISR_Disable( _scratch2 ); \
812    _xlevel = _scratch2; \
813  } while(0)
814
815/*
816 *  Map interrupt level in task mode onto the hardware that the CPU
817 *  actually provides.  Currently, interrupt levels which do not
818 *  map onto the CPU in a generic fashion are undefined.  Someday,
819 *  it would be nice if these were "mapped" by the application
820 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
821 *  8 - 255 would be available for bsp/application specific meaning.
822 *  This could be used to manage a programmable interrupt controller
823 *  via the rtems_task_mode directive.
824 *
825 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
826 *  manipulates the IEC.
827 */
828
829uint32_t   _CPU_ISR_Get_level( void );  /* in cpu.c */
830
831void _CPU_ISR_Set_level( uint32_t   );  /* in cpu.c */
832
833/* end of ISR handler macros */
834
835/* Context handler macros */
836
837/*
838 *  Initialize the context to a state suitable for starting a
839 *  task after a context restore operation.  Generally, this
840 *  involves:
841 *
842 *     - setting a starting address
843 *     - preparing the stack
844 *     - preparing the stack and frame pointers
845 *     - setting the proper interrupt level in the context
846 *     - initializing the floating point context
847 *
848 *  This routine generally does not set any unnecessary register
849 *  in the context.  The state of the "general data" registers is
850 *  undefined at task start time.
851 *
852 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
853 *        point thread.  This is typically only used on CPUs where the
854 *        FPU may be easily disabled by software such as on the SPARC
855 *        where the PSR contains an enable FPU bit.
856 *
857 *  The per-thread status register holds the interrupt enable, FP enable
858 *  and global interrupt enable for that thread.  It means each thread can
859 *  enable its own set of interrupts.  If interrupts are disabled, RTEMS
860 *  can still dispatch via blocking calls.  This is the function of the
861 *  "Interrupt Level", and on the MIPS, it controls the IEC bit and all
862 *  the hardware interrupts as defined in the SR.  Software ints
863 *  are automatically enabled for all threads, as they will only occur under
864 *  program control anyhow.  Besides, the interrupt level parm is only 8 bits,
865 *  and controlling the software ints plus the others would require 9.
866 *
867 *  If the Interrupt Level is 0, all ints are on.  Otherwise, the
868 *  Interrupt Level should supply a bit pattern to impose on the SR
869 *  interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6
870 *  apply to the SR register Intr bits from bit 10 thru bit 15.  Bit 7 of
871 *  the Interrupt Level parameter is unused at this time.
872 *
873 *  These are the only per-thread SR bits, the others are maintained
874 *  globally & explicitly preserved by the Context Switch code in cpu_asm.s
875 */
876
877
878#if (__mips == 3) || (__mips == 32)
879#define _INTON          SR_IE
880#if __mips_fpr==64
881#define _EXTRABITS      SR_FR
882#else
883#define _EXTRABITS      0
884#endif /* __mips_fpr==64 */
885#endif /* __mips == 3 */
886#if __mips == 1
887#define _INTON          SR_IEC
888#define _EXTRABITS      0  /* make sure we're in user mode on MIPS1 processors */
889#endif /* __mips == 1 */
890
891#define _CPU_Context_Initialize( _the_context, _stack_base, _size, _isr, _entry_point, _is_fp ) \
892  { \
893        uintptr_t  _stack_tmp = \
894           (uintptr_t)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
895        uintptr_t  _intlvl = _isr & 0xff; \
896        _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
897        (_the_context)->sp = _stack_tmp; \
898        (_the_context)->fp = _stack_tmp; \
899        (_the_context)->ra = (__MIPS_REGISTER_TYPE)_entry_point; \
900        (_the_context)->c0_sr = ((_intlvl==0)?(mips_interrupt_mask() | 0x300 | _INTON): \
901                ( ((_intlvl<<9) & mips_interrupt_mask()) | 0x300 | ((_intlvl & 1)?_INTON:0)) ) | \
902                                SR_CU0 | ((_is_fp)?SR_CU1:0) | _EXTRABITS; \
903  }
904
905
906
907/*
908 *  This routine is responsible for somehow restarting the currently
909 *  executing task.  If you are lucky, then all that is necessary
910 *  is restoring the context.  Otherwise, there will need to be
911 *  a special assembly routine which does something special in this
912 *  case.  Context_Restore should work most of the time.  It will
913 *  not work if restarting self conflicts with the stack frame
914 *  assumptions of restoring a context.
915 */
916
917#define _CPU_Context_Restart_self( _the_context ) \
918   _CPU_Context_restore( (_the_context) );
919
920/*
921 *  The purpose of this macro is to allow the initial pointer into
922 *  A floating point context area (used to save the floating point
923 *  context) to be at an arbitrary place in the floating point
924 *  context area.
925 *
926 *  This is necessary because some FP units are designed to have
927 *  their context saved as a stack which grows into lower addresses.
928 *  Other FP units can be saved by simply moving registers into offsets
929 *  from the base of the context area.  Finally some FP units provide
930 *  a "dump context" instruction which could fill in from high to low
931 *  or low to high based on the whim of the CPU designers.
932 */
933
934#define _CPU_Context_Fp_start( _base, _offset ) \
935   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
936
937/*
938 *  This routine initializes the FP context area passed to it to.
939 *  There are a few standard ways in which to initialize the
940 *  floating point context.  The code included for this macro assumes
941 *  that this is a CPU in which a "initial" FP context was saved into
942 *  _CPU_Null_fp_context and it simply copies it to the destination
943 *  context passed to it.
944 *
945 *  Other models include (1) not doing anything, and (2) putting
946 *  a "null FP status word" in the correct place in the FP context.
947 */
948
949#if ( CPU_HARDWARE_FP == TRUE )
950#define _CPU_Context_Initialize_fp( _destination ) \
951  { \
952   *(*(_destination)) = _CPU_Null_fp_context; \
953  }
954#endif
955
956/* end of Context handler macros */
957
958/* Fatal Error manager macros */
959
960/*
961 *  This routine copies _error into a known place -- typically a stack
962 *  location or a register, optionally disables interrupts, and
963 *  halts/stops the CPU.
964 */
965
966#define _CPU_Fatal_halt( _error ) \
967  do { \
968    unsigned int _level; \
969    _CPU_ISR_Disable(_level); \
970    loop: goto loop; \
971  } while (0)
972
973
974extern void mips_break( int error );
975
976/* Bitfield handler macros */
977
978/*
979 *  This routine sets _output to the bit number of the first bit
980 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
981 *  This type may be either 16 or 32 bits wide although only the 16
982 *  least significant bits will be used.
983 *
984 *  There are a number of variables in using a "find first bit" type
985 *  instruction.
986 *
987 *    (1) What happens when run on a value of zero?
988 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
989 *    (3) The numbering may be zero or one based.
990 *    (4) The "find first bit" instruction may search from MSB or LSB.
991 *
992 *  RTEMS guarantees that (1) will never happen so it is not a concern.
993 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
994 *  _CPU_Priority_bits_index().  These three form a set of routines
995 *  which must logically operate together.  Bits in the _value are
996 *  set and cleared based on masks built by _CPU_Priority_mask().
997 *  The basic major and minor values calculated by _Priority_Major()
998 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
999 *  to properly range between the values returned by the "find first bit"
1000 *  instruction.  This makes it possible for _Priority_Get_highest() to
1001 *  calculate the major and directly index into the minor table.
1002 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
1003 *  is the first bit found.
1004 *
1005 *  This entire "find first bit" and mapping process depends heavily
1006 *  on the manner in which a priority is broken into a major and minor
1007 *  components with the major being the 4 MSB of a priority and minor
1008 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
1009 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
1010 *  to the lowest priority.
1011 *
1012 *  If your CPU does not have a "find first bit" instruction, then
1013 *  there are ways to make do without it.  Here are a handful of ways
1014 *  to implement this in software:
1015 *
1016 *    - a series of 16 bit test instructions
1017 *    - a "binary search using if's"
1018 *    - _number = 0
1019 *      if _value > 0x00ff
1020 *        _value >>=8
1021 *        _number = 8;
1022 *
1023 *      if _value > 0x0000f
1024 *        _value >=8
1025 *        _number += 4
1026 *
1027 *      _number += bit_set_table[ _value ]
1028 *
1029 *    where bit_set_table[ 16 ] has values which indicate the first
1030 *      bit set
1031 */
1032
1033#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
1034#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
1035
1036#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1037
1038#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1039  { \
1040    (_output) = 0;   /* do something to prevent warnings */ \
1041  }
1042
1043#endif
1044
1045/* end of Bitfield handler macros */
1046
1047/*
1048 *  This routine builds the mask which corresponds to the bit fields
1049 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
1050 *  for that routine.
1051 */
1052
1053#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1054
1055#define _CPU_Priority_Mask( _bit_number ) \
1056  ( 1 << (_bit_number) )
1057
1058#endif
1059
1060/*
1061 *  This routine translates the bit numbers returned by
1062 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
1063 *  a major or minor component of a priority.  See the discussion
1064 *  for that routine.
1065 */
1066
1067#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1068
1069#define _CPU_Priority_bits_index( _priority ) \
1070  (_priority)
1071
1072#endif
1073
1074/* end of Priority handler macros */
1075
1076/* functions */
1077
1078/*
1079 *  _CPU_Initialize
1080 *
1081 *  This routine performs CPU dependent initialization.
1082 */
1083
1084void _CPU_Initialize(
1085  rtems_cpu_table  *cpu_table,
1086  void      (*thread_dispatch)
1087);
1088
1089/*
1090 *  _CPU_ISR_install_raw_handler
1091 *
1092 *  This routine installs a "raw" interrupt handler directly into the
1093 *  processor's vector table.
1094 */
1095
1096void _CPU_ISR_install_raw_handler(
1097  uint32_t    vector,
1098  proc_ptr    new_handler,
1099  proc_ptr   *old_handler
1100);
1101
1102/*
1103 *  _CPU_ISR_install_vector
1104 *
1105 *  This routine installs an interrupt vector.
1106 */
1107
1108void _CPU_ISR_install_vector(
1109  uint32_t    vector,
1110  proc_ptr    new_handler,
1111  proc_ptr   *old_handler
1112);
1113
1114/*
1115 *  _CPU_Install_interrupt_stack
1116 *
1117 *  This routine installs the hardware interrupt stack pointer.
1118 *
1119 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1120 *         is TRUE.
1121 */
1122
1123void _CPU_Install_interrupt_stack( void );
1124
1125/*
1126 *  _CPU_Internal_threads_Idle_thread_body
1127 *
1128 *  This routine is the CPU dependent IDLE thread body.
1129 *
1130 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1131 *         is TRUE.
1132 */
1133
1134void _CPU_Thread_Idle_body( void );
1135
1136/*
1137 *  _CPU_Context_switch
1138 *
1139 *  This routine switches from the run context to the heir context.
1140 */
1141
1142void _CPU_Context_switch(
1143  Context_Control  *run,
1144  Context_Control  *heir
1145);
1146
1147/*
1148 *  _CPU_Context_restore
1149 *
1150 *  This routine is generally used only to restart self in an
1151 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1152 *
1153 *  NOTE: May be unnecessary to reload some registers.
1154 */
1155
1156void _CPU_Context_restore(
1157  Context_Control *new_context
1158);
1159
1160/*
1161 *  _CPU_Context_save_fp
1162 *
1163 *  This routine saves the floating point context passed to it.
1164 */
1165
1166void _CPU_Context_save_fp(
1167  Context_Control_fp **fp_context_ptr
1168);
1169
1170/*
1171 *  _CPU_Context_restore_fp
1172 *
1173 *  This routine restores the floating point context passed to it.
1174 */
1175
1176void _CPU_Context_restore_fp(
1177  Context_Control_fp **fp_context_ptr
1178);
1179
1180/*  The following routine swaps the endian format of an unsigned int.
1181 *  It must be static because it is referenced indirectly.
1182 *
1183 *  This version will work on any processor, but if there is a better
1184 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1185 *
1186 *     swap least significant two bytes with 16-bit rotate
1187 *     swap upper and lower 16-bits
1188 *     swap most significant two bytes with 16-bit rotate
1189 *
1190 *  Some CPUs have special instructions which swap a 32-bit quantity in
1191 *  a single instruction (e.g. i486).  It is probably best to avoid
1192 *  an "endian swapping control bit" in the CPU.  One good reason is
1193 *  that interrupts would probably have to be disabled to ensure that
1194 *  an interrupt does not try to access the same "chunk" with the wrong
1195 *  endian.  Another good reason is that on some CPUs, the endian bit
1196 *  endianness for ALL fetches -- both code and data -- so the code
1197 *  will be fetched incorrectly.
1198 */
1199
1200static inline uint32_t CPU_swap_u32(
1201  uint32_t value
1202)
1203{
1204  uint32_t   byte1, byte2, byte3, byte4, swapped;
1205
1206  byte4 = (value >> 24) & 0xff;
1207  byte3 = (value >> 16) & 0xff;
1208  byte2 = (value >> 8)  & 0xff;
1209  byte1 =  value        & 0xff;
1210
1211  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1212  return( swapped );
1213}
1214
1215#define CPU_swap_u16( value ) \
1216  (((value&0xff) << 8) | ((value >> 8)&0xff))
1217
1218
1219#endif
1220
1221
1222
1223#ifdef __cplusplus
1224}
1225#endif
1226
1227#endif
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