source: rtems/cpukit/score/cpu/mips/rtems/score/cpu.h @ 0832ca7

4.11
Last change on this file since 0832ca7 was 03b7789, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 26, 2014 at 1:09:10 PM

score: Statically initialize _ISR_Vector_table

  • Property mode set to 100644
File size: 41.9 KB
Line 
1/**
2 *  @file
3 *
4 *  @brief Mips CPU Dependent Header File
5 */
6
7/*
8 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
9 *           Joel Sherrill <joel@OARcorp.com>.
10 *
11 *    These changes made the code conditional on standard cpp predefines,
12 *    merged the mips1 and mips3 code sequences as much as possible,
13 *    and moved some of the assembly code to C.  Alan did much of the
14 *    initial analysis and rework.  Joel took over from there and
15 *    wrote the JMR3904 BSP so this could be tested.  Joel also
16 *    added the new interrupt vectoring support in libcpu and
17 *    tried to better support the various interrupt controllers.
18 *
19 */
20
21/*
22 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
23 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
24 *
25 *    To anyone who acknowledges that this file is provided "AS IS"
26 *    without any express or implied warranty:
27 *      permission to use, copy, modify, and distribute this file
28 *      for any purpose is hereby granted without fee, provided that
29 *      the above copyright notice and this notice appears in all
30 *      copies, and that the name of Transition Networks not be used in
31 *      advertising or publicity pertaining to distribution of the
32 *      software without specific, written prior permission.
33 *      Transition Networks makes no representations about the suitability
34 *      of this software for any purpose.
35 *
36 *  COPYRIGHT (c) 1989-2012.
37 *  On-Line Applications Research Corporation (OAR).
38 *
39 *  The license and distribution terms for this file may be
40 *  found in the file LICENSE in this distribution or at
41 *  http://www.rtems.org/license/LICENSE.
42 */
43
44#ifndef _RTEMS_SCORE_CPU_H
45#define _RTEMS_SCORE_CPU_H
46
47/**
48 *  @defgroup ScoreCPU CPU CPU
49 *
50 *  @ingroup Score
51 *
52 */
53/**@{*/
54
55#ifdef __cplusplus
56extern "C" {
57#endif
58
59#include <rtems/score/types.h>
60#include <rtems/score/mips.h>
61
62/* conditional compilation parameters */
63
64/*
65 *  Should the calls to _Thread_Enable_dispatch be inlined?
66 *
67 *  If TRUE, then they are inlined.
68 *  If FALSE, then a subroutine call is made.
69 *
70 *  Basically this is an example of the classic trade-off of size
71 *  versus speed.  Inlining the call (TRUE) typically increases the
72 *  size of RTEMS while speeding up the enabling of dispatching.
73 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
74 *  only be 0 or 1 unless you are in an interrupt handler and that
75 *  interrupt handler invokes the executive.]  When not inlined
76 *  something calls _Thread_Enable_dispatch which in turns calls
77 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
78 *  one subroutine call is avoided entirely.]
79 */
80
81#define CPU_INLINE_ENABLE_DISPATCH       FALSE
82
83/*
84 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
85 *  be unrolled one time?  In unrolled each iteration of the loop examines
86 *  two "nodes" on the chain being searched.  Otherwise, only one node
87 *  is examined per iteration.
88 *
89 *  If TRUE, then the loops are unrolled.
90 *  If FALSE, then the loops are not unrolled.
91 *
92 *  The primary factor in making this decision is the cost of disabling
93 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
94 *  body of the loop.  On some CPUs, the flash is more expensive than
95 *  one iteration of the loop body.  In this case, it might be desirable
96 *  to unroll the loop.  It is important to note that on some CPUs, this
97 *  code is the longest interrupt disable period in RTEMS.  So it is
98 *  necessary to strike a balance when setting this parameter.
99 */
100
101#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
102
103/*
104 *  Does RTEMS manage a dedicated interrupt stack in software?
105 *
106 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
107 *  If FALSE, nothing is done.
108 *
109 *  If the CPU supports a dedicated interrupt stack in hardware,
110 *  then it is generally the responsibility of the BSP to allocate it
111 *  and set it up.
112 *
113 *  If the CPU does not support a dedicated interrupt stack, then
114 *  the porter has two options: (1) execute interrupts on the
115 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
116 *  interrupt stack.
117 *
118 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
119 *
120 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
121 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
122 *  possible that both are FALSE for a particular CPU.  Although it
123 *  is unclear what that would imply about the interrupt processing
124 *  procedure on that CPU.
125 */
126
127#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
128
129/*
130 *  Does the CPU follow the simple vectored interrupt model?
131 *
132 *  If TRUE, then RTEMS allocates the vector table it internally manages.
133 *  If FALSE, then the BSP is assumed to allocate and manage the vector
134 *  table
135 *
136 *  MIPS Specific Information:
137 *
138 *  Up to and including RTEMS 4.10, the MIPS port used simple vectored
139 *  interrupts. But this was changed to the PIC model after 4.10.
140 */
141#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
142
143/*
144 *  Does this CPU have hardware support for a dedicated interrupt stack?
145 *
146 *  If TRUE, then it must be installed during initialization.
147 *  If FALSE, then no installation is performed.
148 *
149 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
150 *
151 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
152 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
153 *  possible that both are FALSE for a particular CPU.  Although it
154 *  is unclear what that would imply about the interrupt processing
155 *  procedure on that CPU.
156 */
157
158#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
159
160/*
161 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
162 *
163 *  If TRUE, then the memory is allocated during initialization.
164 *  If FALSE, then the memory is allocated during initialization.
165 *
166 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
167 */
168
169#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
170
171/*
172 *  Does the RTEMS invoke the user's ISR with the vector number and
173 *  a pointer to the saved interrupt frame (1) or just the vector
174 *  number (0)?
175 *
176 */
177
178#define CPU_ISR_PASSES_FRAME_POINTER 1
179
180
181
182/*
183 *  Does the CPU have hardware floating point?
184 *
185 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
186 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
187 *
188 *  If there is a FP coprocessor such as the i387 or mc68881, then
189 *  the answer is TRUE.
190 *
191 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
192 *  It indicates whether or not this CPU model has FP support.  For
193 *  example, it would be possible to have an i386_nofp CPU model
194 *  which set this to false to indicate that you have an i386 without
195 *  an i387 and wish to leave floating point support out of RTEMS.
196 */
197
198#if ( MIPS_HAS_FPU == 1 )
199#define CPU_HARDWARE_FP     TRUE
200#else
201#define CPU_HARDWARE_FP     FALSE
202#endif
203
204/*
205 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
206 *
207 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
208 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
209 *
210 *  So far, the only CPU in which this option has been used is the
211 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
212 *  floating point registers to perform integer multiplies.  If
213 *  a function which you would not think utilize the FP unit DOES,
214 *  then one can not easily predict which tasks will use the FP hardware.
215 *  In this case, this option should be TRUE.
216 *
217 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
218 *
219 *  Mips Note: It appears the GCC can implicitly generate FPU
220 *  and Altivec instructions when you least expect them.  So make
221 *  all tasks floating point.
222 */
223
224#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
225
226/*
227 *  Should the IDLE task have a floating point context?
228 *
229 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
230 *  and it has a floating point context which is switched in and out.
231 *  If FALSE, then the IDLE task does not have a floating point context.
232 *
233 *  Setting this to TRUE negatively impacts the time required to preempt
234 *  the IDLE task from an interrupt because the floating point context
235 *  must be saved as part of the preemption.
236 */
237
238#define CPU_IDLE_TASK_IS_FP      FALSE
239
240/*
241 *  Should the saving of the floating point registers be deferred
242 *  until a context switch is made to another different floating point
243 *  task?
244 *
245 *  If TRUE, then the floating point context will not be stored until
246 *  necessary.  It will remain in the floating point registers and not
247 *  disturned until another floating point task is switched to.
248 *
249 *  If FALSE, then the floating point context is saved when a floating
250 *  point task is switched out and restored when the next floating point
251 *  task is restored.  The state of the floating point registers between
252 *  those two operations is not specified.
253 *
254 *  If the floating point context does NOT have to be saved as part of
255 *  interrupt dispatching, then it should be safe to set this to TRUE.
256 *
257 *  Setting this flag to TRUE results in using a different algorithm
258 *  for deciding when to save and restore the floating point context.
259 *  The deferred FP switch algorithm minimizes the number of times
260 *  the FP context is saved and restored.  The FP context is not saved
261 *  until a context switch is made to another, different FP task.
262 *  Thus in a system with only one FP task, the FP context will never
263 *  be saved or restored.
264 */
265
266#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
267
268/*
269 *  Does this port provide a CPU dependent IDLE task implementation?
270 *
271 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
272 *  must be provided and is the default IDLE thread body instead of
273 *  _Internal_threads_Idle_thread_body.
274 *
275 *  If FALSE, then use the generic IDLE thread body if the BSP does
276 *  not provide one.
277 *
278 *  This is intended to allow for supporting processors which have
279 *  a low power or idle mode.  When the IDLE thread is executed, then
280 *  the CPU can be powered down.
281 *
282 *  The order of precedence for selecting the IDLE thread body is:
283 *
284 *    1.  BSP provided
285 *    2.  CPU dependent (if provided)
286 *    3.  generic (if no BSP and no CPU dependent)
287 */
288
289/* we can use the low power wait instruction for the IDLE thread */
290#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
291
292/*
293 *  Does the stack grow up (toward higher addresses) or down
294 *  (toward lower addresses)?
295 *
296 *  If TRUE, then the grows upward.
297 *  If FALSE, then the grows toward smaller addresses.
298 */
299
300/* our stack grows down */
301#define CPU_STACK_GROWS_UP               FALSE
302
303/*
304 *  The following is the variable attribute used to force alignment
305 *  of critical RTEMS structures.  On some processors it may make
306 *  sense to have these aligned on tighter boundaries than
307 *  the minimum requirements of the compiler in order to have as
308 *  much of the critical data area as possible in a cache line.
309 *
310 *  The placement of this macro in the declaration of the variables
311 *  is based on the syntactically requirements of the GNU C
312 *  "__attribute__" extension.  For example with GNU C, use
313 *  the following to force a structures to a 32 byte boundary.
314 *
315 *      __attribute__ ((aligned (32)))
316 *
317 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
318 *         To benefit from using this, the data must be heavily
319 *         used so it will stay in the cache and used frequently enough
320 *         in the executive to justify turning this on.
321 */
322
323/* our cache line size is 16 bytes */
324#if __GNUC__
325#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
326#else
327#define CPU_STRUCTURE_ALIGNMENT
328#endif
329
330#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
331
332/*
333 *  Define what is required to specify how the network to host conversion
334 *  routines are handled.
335 */
336
337/* __MIPSEB__ or __MIPSEL__ is defined by GCC based on -EB or -EL command line options */
338#if defined(__MIPSEB__)
339#define CPU_BIG_ENDIAN                           TRUE
340#define CPU_LITTLE_ENDIAN                        FALSE
341#elif defined(__MIPSEL__)
342#define CPU_BIG_ENDIAN                           FALSE
343#define CPU_LITTLE_ENDIAN                        TRUE
344#else
345#error "Unknown endianness"
346#endif
347
348/*
349 *  The following defines the number of bits actually used in the
350 *  interrupt field of the task mode.  How those bits map to the
351 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
352 */
353
354#define CPU_MODES_INTERRUPT_MASK   0x000000ff
355
356#define CPU_SIZEOF_POINTER 4
357
358#define CPU_PER_CPU_CONTROL_SIZE 0
359
360/*
361 *  Processor defined structures
362 *
363 *  Examples structures include the descriptor tables from the i386
364 *  and the processor control structure on the i960ca.
365 */
366
367/* may need to put some structures here.  */
368
369/*
370 * Contexts
371 *
372 *  Generally there are 2 types of context to save.
373 *     1. Interrupt registers to save
374 *     2. Task level registers to save
375 *
376 *  This means we have the following 3 context items:
377 *     1. task level context stuff::  Context_Control
378 *     2. floating point task stuff:: Context_Control_fp
379 *     3. special interrupt level context :: Context_Control_interrupt
380 *
381 *  On some processors, it is cost-effective to save only the callee
382 *  preserved registers during a task context switch.  This means
383 *  that the ISR code needs to save those registers which do not
384 *  persist across function calls.  It is not mandatory to make this
385 *  distinctions between the caller/callee saves registers for the
386 *  purpose of minimizing context saved during task switch and on interrupts.
387 *  If the cost of saving extra registers is minimal, simplicity is the
388 *  choice.  Save the same context on interrupt entry as for tasks in
389 *  this case.
390 *
391 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
392 *  care should be used in designing the context area.
393 *
394 *  On some CPUs with hardware floating point support, the Context_Control_fp
395 *  structure will not be used or it simply consist of an array of a
396 *  fixed number of bytes.   This is done when the floating point context
397 *  is dumped by a "FP save context" type instruction and the format
398 *  is not really defined by the CPU.  In this case, there is no need
399 *  to figure out the exact format -- only the size.  Of course, although
400 *  this is enough information for RTEMS, it is probably not enough for
401 *  a debugger such as gdb.  But that is another problem.
402 */
403
404#ifndef ASM
405
406typedef struct {
407  /* There is no CPU specific per-CPU state */
408} CPU_Per_CPU_control;
409
410/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
411#if (__mips == 1) || (__mips == 32)
412#define __MIPS_REGISTER_TYPE     uint32_t
413#define __MIPS_FPU_REGISTER_TYPE uint32_t
414#elif __mips == 3
415#define __MIPS_REGISTER_TYPE     uint64_t
416#define __MIPS_FPU_REGISTER_TYPE uint64_t
417#else
418#error "mips register size: unknown architecture level!!"
419#endif
420typedef struct {
421    __MIPS_REGISTER_TYPE s0;
422    __MIPS_REGISTER_TYPE s1;
423    __MIPS_REGISTER_TYPE s2;
424    __MIPS_REGISTER_TYPE s3;
425    __MIPS_REGISTER_TYPE s4;
426    __MIPS_REGISTER_TYPE s5;
427    __MIPS_REGISTER_TYPE s6;
428    __MIPS_REGISTER_TYPE s7;
429    __MIPS_REGISTER_TYPE sp;
430    __MIPS_REGISTER_TYPE fp;
431    __MIPS_REGISTER_TYPE ra;
432    __MIPS_REGISTER_TYPE c0_sr;
433    __MIPS_REGISTER_TYPE c0_epc;
434} Context_Control;
435
436#define _CPU_Context_Get_SP( _context ) \
437  (uintptr_t) (_context)->sp
438
439/* WARNING: If this structure is modified, the constants in cpu.h
440 *          must also be updated.
441 */
442
443typedef struct {
444#if ( CPU_HARDWARE_FP == TRUE )
445    __MIPS_FPU_REGISTER_TYPE fp0;
446    __MIPS_FPU_REGISTER_TYPE fp1;
447    __MIPS_FPU_REGISTER_TYPE fp2;
448    __MIPS_FPU_REGISTER_TYPE fp3;
449    __MIPS_FPU_REGISTER_TYPE fp4;
450    __MIPS_FPU_REGISTER_TYPE fp5;
451    __MIPS_FPU_REGISTER_TYPE fp6;
452    __MIPS_FPU_REGISTER_TYPE fp7;
453    __MIPS_FPU_REGISTER_TYPE fp8;
454    __MIPS_FPU_REGISTER_TYPE fp9;
455    __MIPS_FPU_REGISTER_TYPE fp10;
456    __MIPS_FPU_REGISTER_TYPE fp11;
457    __MIPS_FPU_REGISTER_TYPE fp12;
458    __MIPS_FPU_REGISTER_TYPE fp13;
459    __MIPS_FPU_REGISTER_TYPE fp14;
460    __MIPS_FPU_REGISTER_TYPE fp15;
461    __MIPS_FPU_REGISTER_TYPE fp16;
462    __MIPS_FPU_REGISTER_TYPE fp17;
463    __MIPS_FPU_REGISTER_TYPE fp18;
464    __MIPS_FPU_REGISTER_TYPE fp19;
465    __MIPS_FPU_REGISTER_TYPE fp20;
466    __MIPS_FPU_REGISTER_TYPE fp21;
467    __MIPS_FPU_REGISTER_TYPE fp22;
468    __MIPS_FPU_REGISTER_TYPE fp23;
469    __MIPS_FPU_REGISTER_TYPE fp24;
470    __MIPS_FPU_REGISTER_TYPE fp25;
471    __MIPS_FPU_REGISTER_TYPE fp26;
472    __MIPS_FPU_REGISTER_TYPE fp27;
473    __MIPS_FPU_REGISTER_TYPE fp28;
474    __MIPS_FPU_REGISTER_TYPE fp29;
475    __MIPS_FPU_REGISTER_TYPE fp30;
476    __MIPS_FPU_REGISTER_TYPE fp31;
477    uint32_t fpcs;
478#endif
479} Context_Control_fp;
480
481/*
482 *  This struct reflects the stack frame employed in ISR_Handler.  Note
483 *  that the ISR routine save some of the registers to this frame for
484 *  all interrupts and exceptions.  Other registers are saved only on
485 *  exceptions, while others are not touched at all.  The untouched
486 *  registers are not normally disturbed by high-level language
487 *  programs so they can be accessed when required.
488 *
489 *  The registers and their ordering in this struct must directly
490 *  correspond to the layout and ordering of * shown in iregdef.h,
491 *  as cpu_asm.S uses those definitions to fill the stack frame.
492 *  This struct provides access to the stack frame for C code.
493 *
494 *  Similarly, this structure is used by debugger stubs and exception
495 *  processing routines so be careful when changing the format.
496 *
497 *  NOTE: The comments with this structure and cpu_asm.S should be kept
498 *        in sync.  When in doubt, look in the  code to see if the
499 *        registers you're interested in are actually treated as expected.
500 *        The order of the first portion of this structure follows the
501 *        order of registers expected by gdb.
502 */
503
504typedef struct
505{
506  __MIPS_REGISTER_TYPE  r0;       /*  0 -- NOT FILLED IN */
507  __MIPS_REGISTER_TYPE  at;       /*  1 -- saved always */
508  __MIPS_REGISTER_TYPE  v0;       /*  2 -- saved always */
509  __MIPS_REGISTER_TYPE  v1;       /*  3 -- saved always */
510  __MIPS_REGISTER_TYPE  a0;       /*  4 -- saved always */
511  __MIPS_REGISTER_TYPE  a1;       /*  5 -- saved always */
512  __MIPS_REGISTER_TYPE  a2;       /*  6 -- saved always */
513  __MIPS_REGISTER_TYPE  a3;       /*  7 -- saved always */
514  __MIPS_REGISTER_TYPE  t0;       /*  8 -- saved always */
515  __MIPS_REGISTER_TYPE  t1;       /*  9 -- saved always */
516  __MIPS_REGISTER_TYPE  t2;       /* 10 -- saved always */
517  __MIPS_REGISTER_TYPE  t3;       /* 11 -- saved always */
518  __MIPS_REGISTER_TYPE  t4;       /* 12 -- saved always */
519  __MIPS_REGISTER_TYPE  t5;       /* 13 -- saved always */
520  __MIPS_REGISTER_TYPE  t6;       /* 14 -- saved always */
521  __MIPS_REGISTER_TYPE  t7;       /* 15 -- saved always */
522  __MIPS_REGISTER_TYPE  s0;       /* 16 -- saved on exceptions */
523  __MIPS_REGISTER_TYPE  s1;       /* 17 -- saved on exceptions */
524  __MIPS_REGISTER_TYPE  s2;       /* 18 -- saved on exceptions */
525  __MIPS_REGISTER_TYPE  s3;       /* 19 -- saved on exceptions */
526  __MIPS_REGISTER_TYPE  s4;       /* 20 -- saved on exceptions */
527  __MIPS_REGISTER_TYPE  s5;       /* 21 -- saved on exceptions */
528  __MIPS_REGISTER_TYPE  s6;       /* 22 -- saved on exceptions */
529  __MIPS_REGISTER_TYPE  s7;       /* 23 -- saved on exceptions */
530  __MIPS_REGISTER_TYPE  t8;       /* 24 -- saved always */
531  __MIPS_REGISTER_TYPE  t9;       /* 25 -- saved always */
532  __MIPS_REGISTER_TYPE  k0;       /* 26 -- NOT FILLED IN, kernel tmp reg */
533  __MIPS_REGISTER_TYPE  k1;       /* 27 -- NOT FILLED IN, kernel tmp reg */
534  __MIPS_REGISTER_TYPE  gp;       /* 28 -- saved always */
535  __MIPS_REGISTER_TYPE  sp;       /* 29 -- saved on exceptions NOT RESTORED */
536  __MIPS_REGISTER_TYPE  fp;       /* 30 -- saved always */
537  __MIPS_REGISTER_TYPE  ra;       /* 31 -- saved always */
538  __MIPS_REGISTER_TYPE  c0_sr;    /* 32 -- saved always, some bits are */
539                                  /*    manipulated per-thread          */
540  __MIPS_REGISTER_TYPE  mdlo;     /* 33 -- saved always */
541  __MIPS_REGISTER_TYPE  mdhi;     /* 34 -- saved always */
542  __MIPS_REGISTER_TYPE  badvaddr; /* 35 -- saved on exceptions, read-only */
543  __MIPS_REGISTER_TYPE  cause;    /* 36 -- saved on exceptions NOT restored */
544  __MIPS_REGISTER_TYPE  epc;      /* 37 -- saved always, read-only register */
545                                  /*        but logically restored */
546  __MIPS_FPU_REGISTER_TYPE f0;    /* 38 -- saved if FP enabled */
547  __MIPS_FPU_REGISTER_TYPE f1;    /* 39 -- saved if FP enabled */
548  __MIPS_FPU_REGISTER_TYPE f2;    /* 40 -- saved if FP enabled */
549  __MIPS_FPU_REGISTER_TYPE f3;    /* 41 -- saved if FP enabled */
550  __MIPS_FPU_REGISTER_TYPE f4;    /* 42 -- saved if FP enabled */
551  __MIPS_FPU_REGISTER_TYPE f5;    /* 43 -- saved if FP enabled */
552  __MIPS_FPU_REGISTER_TYPE f6;    /* 44 -- saved if FP enabled */
553  __MIPS_FPU_REGISTER_TYPE f7;    /* 45 -- saved if FP enabled */
554  __MIPS_FPU_REGISTER_TYPE f8;    /* 46 -- saved if FP enabled */
555  __MIPS_FPU_REGISTER_TYPE f9;    /* 47 -- saved if FP enabled */
556  __MIPS_FPU_REGISTER_TYPE f10;   /* 48 -- saved if FP enabled */
557  __MIPS_FPU_REGISTER_TYPE f11;   /* 49 -- saved if FP enabled */
558  __MIPS_FPU_REGISTER_TYPE f12;   /* 50 -- saved if FP enabled */
559  __MIPS_FPU_REGISTER_TYPE f13;   /* 51 -- saved if FP enabled */
560  __MIPS_FPU_REGISTER_TYPE f14;   /* 52 -- saved if FP enabled */
561  __MIPS_FPU_REGISTER_TYPE f15;   /* 53 -- saved if FP enabled */
562  __MIPS_FPU_REGISTER_TYPE f16;   /* 54 -- saved if FP enabled */
563  __MIPS_FPU_REGISTER_TYPE f17;   /* 55 -- saved if FP enabled */
564  __MIPS_FPU_REGISTER_TYPE f18;   /* 56 -- saved if FP enabled */
565  __MIPS_FPU_REGISTER_TYPE f19;   /* 57 -- saved if FP enabled */
566  __MIPS_FPU_REGISTER_TYPE f20;   /* 58 -- saved if FP enabled */
567  __MIPS_FPU_REGISTER_TYPE f21;   /* 59 -- saved if FP enabled */
568  __MIPS_FPU_REGISTER_TYPE f22;   /* 60 -- saved if FP enabled */
569  __MIPS_FPU_REGISTER_TYPE f23;   /* 61 -- saved if FP enabled */
570  __MIPS_FPU_REGISTER_TYPE f24;   /* 62 -- saved if FP enabled */
571  __MIPS_FPU_REGISTER_TYPE f25;   /* 63 -- saved if FP enabled */
572  __MIPS_FPU_REGISTER_TYPE f26;   /* 64 -- saved if FP enabled */
573  __MIPS_FPU_REGISTER_TYPE f27;   /* 65 -- saved if FP enabled */
574  __MIPS_FPU_REGISTER_TYPE f28;   /* 66 -- saved if FP enabled */
575  __MIPS_FPU_REGISTER_TYPE f29;   /* 67 -- saved if FP enabled */
576  __MIPS_FPU_REGISTER_TYPE f30;   /* 68 -- saved if FP enabled */
577  __MIPS_FPU_REGISTER_TYPE f31;   /* 69 -- saved if FP enabled */
578  __MIPS_REGISTER_TYPE     fcsr;  /* 70 -- saved on exceptions */
579                                  /*    (oddly not documented on MGV) */
580  __MIPS_REGISTER_TYPE     feir;  /* 71 -- saved on exceptions */
581                                  /*    (oddly not documented on MGV) */
582
583  /* GDB does not seem to care about anything past this point */
584
585  __MIPS_REGISTER_TYPE  tlbhi;    /* 72 - NOT FILLED IN, doesn't exist on */
586                                  /*         all MIPS CPUs (at least MGV) */
587#if __mips == 1
588  __MIPS_REGISTER_TYPE  tlblo;    /* 73 - NOT FILLED IN, doesn't exist on */
589                                  /*         all MIPS CPUs (at least MGV) */
590#endif
591#if  (__mips == 3) || (__mips == 32)
592  __MIPS_REGISTER_TYPE  tlblo0;   /* 73 - NOT FILLED IN, doesn't exist on */
593                                  /*         all MIPS CPUs (at least MGV) */
594#endif
595
596  __MIPS_REGISTER_TYPE  inx;      /* 74 -- NOT FILLED IN, doesn't exist on */
597                                  /*         all MIPS CPUs (at least MGV) */
598  __MIPS_REGISTER_TYPE  rand;     /* 75 -- NOT FILLED IN, doesn't exist on */
599                                  /*         all MIPS CPUs (at least MGV) */
600  __MIPS_REGISTER_TYPE  ctxt;     /* 76 -- NOT FILLED IN, doesn't exist on */
601                                  /*         all MIPS CPUs (at least MGV) */
602  __MIPS_REGISTER_TYPE  exctype;  /* 77 -- NOT FILLED IN (not enough info) */
603  __MIPS_REGISTER_TYPE  mode;     /* 78 -- NOT FILLED IN (not enough info) */
604  __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
605  __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
606  /* end of __mips == 1 so NREGS == 81 */
607#if  (__mips == 3) || (__mips == 32)
608  __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
609  __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
610  __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
611  __MIPS_REGISTER_TYPE  count;    /* 84 -- NOT FILLED IN */
612  __MIPS_REGISTER_TYPE  compare;  /* 85 -- NOT FILLED IN */
613  __MIPS_REGISTER_TYPE  config;   /* 86 -- NOT FILLED IN */
614  __MIPS_REGISTER_TYPE  lladdr;   /* 87 -- NOT FILLED IN */
615  __MIPS_REGISTER_TYPE  watchlo;  /* 88 -- NOT FILLED IN */
616  __MIPS_REGISTER_TYPE  watchhi;  /* 89 -- NOT FILLED IN */
617  __MIPS_REGISTER_TYPE  ecc;      /* 90 -- NOT FILLED IN */
618  __MIPS_REGISTER_TYPE  cacheerr; /* 91 -- NOT FILLED IN */
619  __MIPS_REGISTER_TYPE  taglo;    /* 92 -- NOT FILLED IN */
620  __MIPS_REGISTER_TYPE  taghi;    /* 93 -- NOT FILLED IN */
621  __MIPS_REGISTER_TYPE  errpc;    /* 94 -- NOT FILLED IN */
622  __MIPS_REGISTER_TYPE  xctxt;    /* 95 -- NOT FILLED IN */
623 /* end of __mips == 3 so NREGS == 96 */
624#endif
625
626} CPU_Interrupt_frame;
627
628typedef CPU_Interrupt_frame CPU_Exception_frame;
629
630/*
631 *  This variable is optional.  It is used on CPUs on which it is difficult
632 *  to generate an "uninitialized" FP context.  It is filled in by
633 *  _CPU_Initialize and copied into the task's FP context area during
634 *  _CPU_Context_Initialize.
635 */
636
637SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
638
639/*
640 *  Nothing prevents the porter from declaring more CPU specific variables.
641 */
642
643/* XXX: if needed, put more variables here */
644
645/*
646 *  The size of the floating point context area.  On some CPUs this
647 *  will not be a "sizeof" because the format of the floating point
648 *  area is not defined -- only the size is.  This is usually on
649 *  CPUs with a "floating point save context" instruction.
650 */
651
652#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
653
654/*
655 *  Amount of extra stack (above minimum stack size) required by
656 *  system initialization thread.  Remember that in a multiprocessor
657 *  system the system intialization thread becomes the MP server thread.
658 */
659
660#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
661
662/*
663 *  Should be large enough to run all RTEMS tests.  This ensures
664 *  that a "reasonable" small application should not have any problems.
665 */
666
667#define CPU_STACK_MINIMUM_SIZE          (8 * 1024)
668
669/*
670 *  CPU's worst alignment requirement for data types on a byte boundary.  This
671 *  alignment does not take into account the requirements for the stack.
672 */
673
674#define CPU_ALIGNMENT              8
675
676/*
677 *  This number corresponds to the byte alignment requirement for the
678 *  heap handler.  This alignment requirement may be stricter than that
679 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
680 *  common for the heap to follow the same alignment requirement as
681 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
682 *  then this should be set to CPU_ALIGNMENT.
683 *
684 *  NOTE:  This does not have to be a power of 2.  It does have to
685 *         be greater or equal to than CPU_ALIGNMENT.
686 */
687
688#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
689
690/*
691 *  This number corresponds to the byte alignment requirement for memory
692 *  buffers allocated by the partition manager.  This alignment requirement
693 *  may be stricter than that for the data types alignment specified by
694 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
695 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
696 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
697 *
698 *  NOTE:  This does not have to be a power of 2.  It does have to
699 *         be greater or equal to than CPU_ALIGNMENT.
700 */
701
702#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
703
704/*
705 *  This number corresponds to the byte alignment requirement for the
706 *  stack.  This alignment requirement may be stricter than that for the
707 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
708 *  is strict enough for the stack, then this should be set to 0.
709 *
710 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
711 */
712
713#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
714
715void mips_vector_exceptions( CPU_Interrupt_frame *frame );
716
717/*
718 *  ISR handler macros
719 */
720
721/*
722 *  Declare the function that is present in the shared libcpu directory,
723 *  that returns the processor dependent interrupt mask.
724 */
725
726uint32_t mips_interrupt_mask( void );
727
728/*
729 *  Disable all interrupts for an RTEMS critical section.  The previous
730 *  level is returned in _level.
731 */
732
733#define _CPU_ISR_Disable( _level ) \
734  do { \
735    unsigned int _scratch; \
736    mips_get_sr( _scratch ); \
737    mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
738    _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
739  } while(0)
740
741/*
742 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
743 *  This indicates the end of an RTEMS critical section.  The parameter
744 *  _level is not modified.
745 */
746
747#define _CPU_ISR_Enable( _level )  \
748  do { \
749    unsigned int _scratch; \
750    mips_get_sr( _scratch ); \
751    mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
752  } while(0)
753
754/*
755 *  This temporarily restores the interrupt to _level before immediately
756 *  disabling them again.  This is used to divide long RTEMS critical
757 *  sections into two or more parts.  The parameter _level is not
758 *  modified.
759 */
760
761#define _CPU_ISR_Flash( _xlevel ) \
762  do { \
763    unsigned int _scratch2 = _xlevel; \
764    _CPU_ISR_Enable( _scratch2 ); \
765    _CPU_ISR_Disable( _scratch2 ); \
766    _xlevel = _scratch2; \
767  } while(0)
768
769/*
770 *  Map interrupt level in task mode onto the hardware that the CPU
771 *  actually provides.  Currently, interrupt levels which do not
772 *  map onto the CPU in a generic fashion are undefined.  Someday,
773 *  it would be nice if these were "mapped" by the application
774 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
775 *  8 - 255 would be available for bsp/application specific meaning.
776 *  This could be used to manage a programmable interrupt controller
777 *  via the rtems_task_mode directive.
778 *
779 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
780 *  manipulates the IEC.
781 */
782
783uint32_t   _CPU_ISR_Get_level( void );  /* in cpu.c */
784
785void _CPU_ISR_Set_level( uint32_t   );  /* in cpu.c */
786
787/* end of ISR handler macros */
788
789/* Context handler macros */
790
791/*
792 *  Initialize the context to a state suitable for starting a
793 *  task after a context restore operation.  Generally, this
794 *  involves:
795 *
796 *     - setting a starting address
797 *     - preparing the stack
798 *     - preparing the stack and frame pointers
799 *     - setting the proper interrupt level in the context
800 *     - initializing the floating point context
801 *
802 *  This routine generally does not set any unnecessary register
803 *  in the context.  The state of the "general data" registers is
804 *  undefined at task start time.
805 *
806 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
807 *        point thread.  This is typically only used on CPUs where the
808 *        FPU may be easily disabled by software such as on the SPARC
809 *        where the PSR contains an enable FPU bit.
810 *
811 *  The per-thread status register holds the interrupt enable, FP enable
812 *  and global interrupt enable for that thread.  It means each thread can
813 *  enable its own set of interrupts.  If interrupts are disabled, RTEMS
814 *  can still dispatch via blocking calls.  This is the function of the
815 *  "Interrupt Level", and on the MIPS, it controls the IEC bit and all
816 *  the hardware interrupts as defined in the SR.  Software ints
817 *  are automatically enabled for all threads, as they will only occur under
818 *  program control anyhow.  Besides, the interrupt level parm is only 8 bits,
819 *  and controlling the software ints plus the others would require 9.
820 *
821 *  If the Interrupt Level is 0, all ints are on.  Otherwise, the
822 *  Interrupt Level should supply a bit pattern to impose on the SR
823 *  interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6
824 *  apply to the SR register Intr bits from bit 10 thru bit 15.  Bit 7 of
825 *  the Interrupt Level parameter is unused at this time.
826 *
827 *  These are the only per-thread SR bits, the others are maintained
828 *  globally & explicitly preserved by the Context Switch code in cpu_asm.s
829 */
830
831
832#if (__mips == 3) || (__mips == 32)
833#define _INTON          SR_IE
834#if __mips_fpr==64
835#define _EXTRABITS      SR_FR
836#else
837#define _EXTRABITS      0
838#endif /* __mips_fpr==64 */
839#endif /* __mips == 3 */
840#if __mips == 1
841#define _INTON          SR_IEC
842#define _EXTRABITS      0  /* make sure we're in user mode on MIPS1 processors */
843#endif /* __mips == 1 */
844
845
846void _CPU_Context_Initialize(
847  Context_Control  *the_context,
848  uintptr_t        *stack_base,
849  uint32_t          size,
850  uint32_t          new_level,
851  void             *entry_point,
852  bool              is_fp,
853  void             *tls_area
854);
855
856
857/*
858 *  This routine is responsible for somehow restarting the currently
859 *  executing task.  If you are lucky, then all that is necessary
860 *  is restoring the context.  Otherwise, there will need to be
861 *  a special assembly routine which does something special in this
862 *  case.  Context_Restore should work most of the time.  It will
863 *  not work if restarting self conflicts with the stack frame
864 *  assumptions of restoring a context.
865 */
866
867#define _CPU_Context_Restart_self( _the_context ) \
868   _CPU_Context_restore( (_the_context) );
869
870/*
871 *  The purpose of this macro is to allow the initial pointer into
872 *  A floating point context area (used to save the floating point
873 *  context) to be at an arbitrary place in the floating point
874 *  context area.
875 *
876 *  This is necessary because some FP units are designed to have
877 *  their context saved as a stack which grows into lower addresses.
878 *  Other FP units can be saved by simply moving registers into offsets
879 *  from the base of the context area.  Finally some FP units provide
880 *  a "dump context" instruction which could fill in from high to low
881 *  or low to high based on the whim of the CPU designers.
882 */
883
884#define _CPU_Context_Fp_start( _base, _offset ) \
885   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
886
887/*
888 *  This routine initializes the FP context area passed to it to.
889 *  There are a few standard ways in which to initialize the
890 *  floating point context.  The code included for this macro assumes
891 *  that this is a CPU in which a "initial" FP context was saved into
892 *  _CPU_Null_fp_context and it simply copies it to the destination
893 *  context passed to it.
894 *
895 *  Other models include (1) not doing anything, and (2) putting
896 *  a "null FP status word" in the correct place in the FP context.
897 */
898
899#if ( CPU_HARDWARE_FP == TRUE )
900#define _CPU_Context_Initialize_fp( _destination ) \
901  { \
902   *(*(_destination)) = _CPU_Null_fp_context; \
903  }
904#endif
905
906/* end of Context handler macros */
907
908/* Fatal Error manager macros */
909
910/*
911 *  This routine copies _error into a known place -- typically a stack
912 *  location or a register, optionally disables interrupts, and
913 *  halts/stops the CPU.
914 */
915
916#define _CPU_Fatal_halt( _error ) \
917  do { \
918    unsigned int _level; \
919    _CPU_ISR_Disable(_level); \
920    (void)_level; \
921    loop: goto loop; \
922  } while (0)
923
924
925extern void mips_break( int error );
926
927/* Bitfield handler macros */
928
929/*
930 *  This routine sets _output to the bit number of the first bit
931 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Word.
932 *  This type may be either 16 or 32 bits wide although only the 16
933 *  least significant bits will be used.
934 *
935 *  There are a number of variables in using a "find first bit" type
936 *  instruction.
937 *
938 *    (1) What happens when run on a value of zero?
939 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
940 *    (3) The numbering may be zero or one based.
941 *    (4) The "find first bit" instruction may search from MSB or LSB.
942 *
943 *  RTEMS guarantees that (1) will never happen so it is not a concern.
944 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
945 *  _CPU_Priority_bits_index().  These three form a set of routines
946 *  which must logically operate together.  Bits in the _value are
947 *  set and cleared based on masks built by _CPU_Priority_mask().
948 *  The basic major and minor values calculated by _Priority_Major()
949 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
950 *  to properly range between the values returned by the "find first bit"
951 *  instruction.  This makes it possible for _Priority_Get_highest() to
952 *  calculate the major and directly index into the minor table.
953 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
954 *  is the first bit found.
955 *
956 *  This entire "find first bit" and mapping process depends heavily
957 *  on the manner in which a priority is broken into a major and minor
958 *  components with the major being the 4 MSB of a priority and minor
959 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
960 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
961 *  to the lowest priority.
962 *
963 *  If your CPU does not have a "find first bit" instruction, then
964 *  there are ways to make do without it.  Here are a handful of ways
965 *  to implement this in software:
966 *
967 *    - a series of 16 bit test instructions
968 *    - a "binary search using if's"
969 *    - _number = 0
970 *      if _value > 0x00ff
971 *        _value >>=8
972 *        _number = 8;
973 *
974 *      if _value > 0x0000f
975 *        _value >=8
976 *        _number += 4
977 *
978 *      _number += bit_set_table[ _value ]
979 *
980 *    where bit_set_table[ 16 ] has values which indicate the first
981 *      bit set
982 */
983
984#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
985#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
986
987#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
988
989#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
990  { \
991    (_output) = 0;   /* do something to prevent warnings */ \
992  }
993
994#endif
995
996/* end of Bitfield handler macros */
997
998/*
999 *  This routine builds the mask which corresponds to the bit fields
1000 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
1001 *  for that routine.
1002 */
1003
1004#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1005
1006#define _CPU_Priority_Mask( _bit_number ) \
1007  ( 1 << (_bit_number) )
1008
1009#endif
1010
1011/*
1012 *  This routine translates the bit numbers returned by
1013 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
1014 *  a major or minor component of a priority.  See the discussion
1015 *  for that routine.
1016 */
1017
1018#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1019
1020#define _CPU_Priority_bits_index( _priority ) \
1021  (_priority)
1022
1023#endif
1024
1025/* end of Priority handler macros */
1026
1027/* functions */
1028
1029/*
1030 *  _CPU_Initialize
1031 *
1032 *  This routine performs CPU dependent initialization.
1033 */
1034
1035void _CPU_Initialize(void);
1036
1037/*
1038 *  _CPU_ISR_install_raw_handler
1039 *
1040 *  This routine installs a "raw" interrupt handler directly into the
1041 *  processor's vector table.
1042 */
1043
1044void _CPU_ISR_install_raw_handler(
1045  uint32_t    vector,
1046  proc_ptr    new_handler,
1047  proc_ptr   *old_handler
1048);
1049
1050/*
1051 *  _CPU_ISR_install_vector
1052 *
1053 *  This routine installs an interrupt vector.
1054 */
1055
1056void _CPU_ISR_install_vector(
1057  uint32_t    vector,
1058  proc_ptr    new_handler,
1059  proc_ptr   *old_handler
1060);
1061
1062/*
1063 *  _CPU_Install_interrupt_stack
1064 *
1065 *  This routine installs the hardware interrupt stack pointer.
1066 *
1067 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1068 *         is TRUE.
1069 */
1070
1071void _CPU_Install_interrupt_stack( void );
1072
1073/*
1074 *  _CPU_Internal_threads_Idle_thread_body
1075 *
1076 *  This routine is the CPU dependent IDLE thread body.
1077 *
1078 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1079 *         is TRUE.
1080 */
1081
1082void *_CPU_Thread_Idle_body( uintptr_t ignored );
1083
1084/*
1085 *  _CPU_Context_switch
1086 *
1087 *  This routine switches from the run context to the heir context.
1088 */
1089
1090void _CPU_Context_switch(
1091  Context_Control  *run,
1092  Context_Control  *heir
1093);
1094
1095/*
1096 *  _CPU_Context_restore
1097 *
1098 *  This routine is generally used only to restart self in an
1099 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1100 *
1101 *  NOTE: May be unnecessary to reload some registers.
1102 */
1103
1104void _CPU_Context_restore(
1105  Context_Control *new_context
1106) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1107
1108/*
1109 *  _CPU_Context_save_fp
1110 *
1111 *  This routine saves the floating point context passed to it.
1112 */
1113
1114void _CPU_Context_save_fp(
1115  Context_Control_fp **fp_context_ptr
1116);
1117
1118/*
1119 *  _CPU_Context_restore_fp
1120 *
1121 *  This routine restores the floating point context passed to it.
1122 */
1123
1124void _CPU_Context_restore_fp(
1125  Context_Control_fp **fp_context_ptr
1126);
1127
1128static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
1129{
1130  /* TODO */
1131}
1132
1133static inline void _CPU_Context_validate( uintptr_t pattern )
1134{
1135  while (1) {
1136    /* TODO */
1137  }
1138}
1139
1140void _BSP_Exception_frame_print( const CPU_Exception_frame *frame );
1141
1142static inline void _CPU_Exception_frame_print(
1143  const CPU_Exception_frame *frame
1144)
1145{
1146  _BSP_Exception_frame_print( frame );
1147}
1148
1149/*  The following routine swaps the endian format of an unsigned int.
1150 *  It must be static because it is referenced indirectly.
1151 *
1152 *  This version will work on any processor, but if there is a better
1153 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1154 *
1155 *     swap least significant two bytes with 16-bit rotate
1156 *     swap upper and lower 16-bits
1157 *     swap most significant two bytes with 16-bit rotate
1158 *
1159 *  Some CPUs have special instructions which swap a 32-bit quantity in
1160 *  a single instruction (e.g. i486).  It is probably best to avoid
1161 *  an "endian swapping control bit" in the CPU.  One good reason is
1162 *  that interrupts would probably have to be disabled to ensure that
1163 *  an interrupt does not try to access the same "chunk" with the wrong
1164 *  endian.  Another good reason is that on some CPUs, the endian bit
1165 *  endianness for ALL fetches -- both code and data -- so the code
1166 *  will be fetched incorrectly.
1167 */
1168
1169static inline uint32_t CPU_swap_u32(
1170  uint32_t value
1171)
1172{
1173  uint32_t   byte1, byte2, byte3, byte4, swapped;
1174
1175  byte4 = (value >> 24) & 0xff;
1176  byte3 = (value >> 16) & 0xff;
1177  byte2 = (value >> 8)  & 0xff;
1178  byte1 =  value        & 0xff;
1179
1180  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1181  return( swapped );
1182}
1183
1184#define CPU_swap_u16( value ) \
1185  (((value&0xff) << 8) | ((value >> 8)&0xff))
1186
1187typedef uint32_t CPU_Counter_ticks;
1188
1189CPU_Counter_ticks _CPU_Counter_read( void );
1190
1191static inline CPU_Counter_ticks _CPU_Counter_difference(
1192  CPU_Counter_ticks second,
1193  CPU_Counter_ticks first
1194)
1195{
1196  return second - first;
1197}
1198
1199#endif
1200
1201
1202
1203#ifdef __cplusplus
1204}
1205#endif
1206
1207/**@}*/
1208#endif
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