[e2040ba] | 1 | /* |
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[aa7f8a1f] | 2 | * Mips CPU Dependent Header File |
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[e2040ba] | 3 | * |
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[aa7f8a1f] | 4 | * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and |
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| 5 | * Joel Sherrill <joel@OARcorp.com>. |
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[e2040ba] | 6 | * |
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[aa7f8a1f] | 7 | * These changes made the code conditional on standard cpp predefines, |
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| 8 | * merged the mips1 and mips3 code sequences as much as possible, |
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| 9 | * and moved some of the assembly code to C. Alan did much of the |
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| 10 | * initial analysis and rework. Joel took over from there and |
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| 11 | * wrote the JMR3904 BSP so this could be tested. Joel also |
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| 12 | * added the new interrupt vectoring support in libcpu and |
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| 13 | * tried to better support the various interrupt controllers. |
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[e2040ba] | 14 | * |
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[aa7f8a1f] | 15 | * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> |
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[e2040ba] | 16 | * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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[aa7f8a1f] | 17 | * |
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| 18 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 19 | * without any express or implied warranty: |
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[7908ba5b] | 20 | * permission to use, copy, modify, and distribute this file |
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| 21 | * for any purpose is hereby granted without fee, provided that |
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| 22 | * the above copyright notice and this notice appears in all |
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| 23 | * copies, and that the name of Transition Networks not be used in |
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| 24 | * advertising or publicity pertaining to distribution of the |
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| 25 | * software without specific, written prior permission. |
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| 26 | * Transition Networks makes no representations about the suitability |
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| 27 | * of this software for any purpose. |
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| 28 | * |
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[ece004d] | 29 | * COPYRIGHT (c) 1989-2006. |
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[7908ba5b] | 30 | * On-Line Applications Research Corporation (OAR). |
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| 31 | * |
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| 32 | * The license and distribution terms for this file may be |
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| 33 | * found in the file LICENSE in this distribution or at |
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[5356c03] | 34 | * http://www.rtems.com/license/LICENSE. |
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[7908ba5b] | 35 | * |
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| 36 | * $Id$ |
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| 37 | */ |
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| 38 | |
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[7f70d1b7] | 39 | #ifndef _RTEMS_SCORE_CPU_H |
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| 40 | #define _RTEMS_SCORE_CPU_H |
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[7908ba5b] | 41 | |
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| 42 | #ifdef __cplusplus |
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| 43 | extern "C" { |
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| 44 | #endif |
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| 45 | |
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[eb4536c] | 46 | #include <rtems/score/types.h> |
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[89b85e51] | 47 | #include <rtems/score/mips.h> |
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[5194a28] | 48 | |
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[7908ba5b] | 49 | /* conditional compilation parameters */ |
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| 50 | |
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| 51 | /* |
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| 52 | * Should the calls to _Thread_Enable_dispatch be inlined? |
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| 53 | * |
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| 54 | * If TRUE, then they are inlined. |
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| 55 | * If FALSE, then a subroutine call is made. |
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| 56 | * |
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| 57 | * Basically this is an example of the classic trade-off of size |
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| 58 | * versus speed. Inlining the call (TRUE) typically increases the |
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| 59 | * size of RTEMS while speeding up the enabling of dispatching. |
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| 60 | * [NOTE: In general, the _Thread_Dispatch_disable_level will |
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| 61 | * only be 0 or 1 unless you are in an interrupt handler and that |
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| 62 | * interrupt handler invokes the executive.] When not inlined |
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| 63 | * something calls _Thread_Enable_dispatch which in turns calls |
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| 64 | * _Thread_Dispatch. If the enable dispatch is inlined, then |
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| 65 | * one subroutine call is avoided entirely.] |
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| 66 | */ |
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| 67 | |
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[e6dec71c] | 68 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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[7908ba5b] | 69 | |
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| 70 | /* |
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| 71 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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| 72 | * be unrolled one time? In unrolled each iteration of the loop examines |
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| 73 | * two "nodes" on the chain being searched. Otherwise, only one node |
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| 74 | * is examined per iteration. |
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| 75 | * |
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| 76 | * If TRUE, then the loops are unrolled. |
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| 77 | * If FALSE, then the loops are not unrolled. |
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| 78 | * |
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| 79 | * The primary factor in making this decision is the cost of disabling |
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| 80 | * and enabling interrupts (_ISR_Flash) versus the cost of rest of the |
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| 81 | * body of the loop. On some CPUs, the flash is more expensive than |
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| 82 | * one iteration of the loop body. In this case, it might be desirable |
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| 83 | * to unroll the loop. It is important to note that on some CPUs, this |
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| 84 | * code is the longest interrupt disable period in RTEMS. So it is |
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| 85 | * necessary to strike a balance when setting this parameter. |
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| 86 | */ |
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| 87 | |
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| 88 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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| 89 | |
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| 90 | /* |
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| 91 | * Does RTEMS manage a dedicated interrupt stack in software? |
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| 92 | * |
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[fda47cd] | 93 | * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. |
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[7908ba5b] | 94 | * If FALSE, nothing is done. |
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| 95 | * |
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| 96 | * If the CPU supports a dedicated interrupt stack in hardware, |
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| 97 | * then it is generally the responsibility of the BSP to allocate it |
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| 98 | * and set it up. |
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| 99 | * |
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| 100 | * If the CPU does not support a dedicated interrupt stack, then |
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| 101 | * the porter has two options: (1) execute interrupts on the |
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| 102 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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| 103 | * interrupt stack. |
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| 104 | * |
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| 105 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 106 | * |
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| 107 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 108 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 109 | * possible that both are FALSE for a particular CPU. Although it |
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| 110 | * is unclear what that would imply about the interrupt processing |
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| 111 | * procedure on that CPU. |
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| 112 | */ |
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| 113 | |
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| 114 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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| 115 | |
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[2fd427c] | 116 | /* |
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| 117 | * Does the CPU follow the simple vectored interrupt model? |
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| 118 | * |
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| 119 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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| 120 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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| 121 | * table |
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| 122 | * |
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| 123 | * MIPS Specific Information: |
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| 124 | * |
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| 125 | * XXX document implementation including references if appropriate |
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| 126 | */ |
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| 127 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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| 128 | |
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[7908ba5b] | 129 | /* |
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| 130 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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| 131 | * |
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| 132 | * If TRUE, then it must be installed during initialization. |
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| 133 | * If FALSE, then no installation is performed. |
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| 134 | * |
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| 135 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 136 | * |
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| 137 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 138 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 139 | * possible that both are FALSE for a particular CPU. Although it |
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| 140 | * is unclear what that would imply about the interrupt processing |
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| 141 | * procedure on that CPU. |
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| 142 | */ |
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| 143 | |
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| 144 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 145 | |
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| 146 | /* |
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| 147 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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| 148 | * |
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| 149 | * If TRUE, then the memory is allocated during initialization. |
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| 150 | * If FALSE, then the memory is allocated during initialization. |
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| 151 | * |
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[ece004d] | 152 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. |
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[7908ba5b] | 153 | */ |
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| 154 | |
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| 155 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
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| 156 | |
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| 157 | /* |
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| 158 | * Does the RTEMS invoke the user's ISR with the vector number and |
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[e2040ba] | 159 | * a pointer to the saved interrupt frame (1) or just the vector |
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[7908ba5b] | 160 | * number (0)? |
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[e2040ba] | 161 | * |
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[7908ba5b] | 162 | */ |
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| 163 | |
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[e2040ba] | 164 | #define CPU_ISR_PASSES_FRAME_POINTER 1 |
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| 165 | |
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| 166 | |
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[7908ba5b] | 167 | |
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| 168 | /* |
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| 169 | * Does the CPU have hardware floating point? |
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| 170 | * |
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| 171 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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| 172 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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| 173 | * |
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| 174 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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| 175 | * the answer is TRUE. |
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| 176 | * |
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[fda47cd] | 177 | * The macro name "MIPS_HAS_FPU" should be made CPU specific. |
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[7908ba5b] | 178 | * It indicates whether or not this CPU model has FP support. For |
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| 179 | * example, it would be possible to have an i386_nofp CPU model |
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| 180 | * which set this to false to indicate that you have an i386 without |
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| 181 | * an i387 and wish to leave floating point support out of RTEMS. |
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| 182 | */ |
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| 183 | |
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[fda47cd] | 184 | #if ( MIPS_HAS_FPU == 1 ) |
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[7908ba5b] | 185 | #define CPU_HARDWARE_FP TRUE |
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| 186 | #else |
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| 187 | #define CPU_HARDWARE_FP FALSE |
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| 188 | #endif |
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| 189 | |
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| 190 | /* |
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| 191 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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| 192 | * |
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| 193 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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| 194 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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| 195 | * |
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[5194a28] | 196 | * So far, the only CPU in which this option has been used is the |
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| 197 | * HP PA-RISC. The HP C compiler and gcc both implicitly use the |
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| 198 | * floating point registers to perform integer multiplies. If |
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| 199 | * a function which you would not think utilize the FP unit DOES, |
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| 200 | * then one can not easily predict which tasks will use the FP hardware. |
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| 201 | * In this case, this option should be TRUE. |
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| 202 | * |
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[7908ba5b] | 203 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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| 204 | */ |
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| 205 | |
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| 206 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 207 | |
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| 208 | /* |
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| 209 | * Should the IDLE task have a floating point context? |
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| 210 | * |
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| 211 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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| 212 | * and it has a floating point context which is switched in and out. |
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| 213 | * If FALSE, then the IDLE task does not have a floating point context. |
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| 214 | * |
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| 215 | * Setting this to TRUE negatively impacts the time required to preempt |
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| 216 | * the IDLE task from an interrupt because the floating point context |
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| 217 | * must be saved as part of the preemption. |
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| 218 | */ |
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| 219 | |
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[0bc5329] | 220 | #define CPU_IDLE_TASK_IS_FP FALSE |
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[7908ba5b] | 221 | |
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| 222 | /* |
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| 223 | * Should the saving of the floating point registers be deferred |
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| 224 | * until a context switch is made to another different floating point |
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| 225 | * task? |
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| 226 | * |
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| 227 | * If TRUE, then the floating point context will not be stored until |
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| 228 | * necessary. It will remain in the floating point registers and not |
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| 229 | * disturned until another floating point task is switched to. |
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| 230 | * |
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| 231 | * If FALSE, then the floating point context is saved when a floating |
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| 232 | * point task is switched out and restored when the next floating point |
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| 233 | * task is restored. The state of the floating point registers between |
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| 234 | * those two operations is not specified. |
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| 235 | * |
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| 236 | * If the floating point context does NOT have to be saved as part of |
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| 237 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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| 238 | * |
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| 239 | * Setting this flag to TRUE results in using a different algorithm |
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| 240 | * for deciding when to save and restore the floating point context. |
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| 241 | * The deferred FP switch algorithm minimizes the number of times |
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| 242 | * the FP context is saved and restored. The FP context is not saved |
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| 243 | * until a context switch is made to another, different FP task. |
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| 244 | * Thus in a system with only one FP task, the FP context will never |
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| 245 | * be saved or restored. |
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| 246 | */ |
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| 247 | |
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| 248 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 249 | |
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| 250 | /* |
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| 251 | * Does this port provide a CPU dependent IDLE task implementation? |
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| 252 | * |
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| 253 | * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body |
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| 254 | * must be provided and is the default IDLE thread body instead of |
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| 255 | * _Internal_threads_Idle_thread_body. |
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| 256 | * |
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| 257 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 258 | * not provide one. |
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| 259 | * |
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| 260 | * This is intended to allow for supporting processors which have |
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| 261 | * a low power or idle mode. When the IDLE thread is executed, then |
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| 262 | * the CPU can be powered down. |
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| 263 | * |
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| 264 | * The order of precedence for selecting the IDLE thread body is: |
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| 265 | * |
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| 266 | * 1. BSP provided |
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| 267 | * 2. CPU dependent (if provided) |
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| 268 | * 3. generic (if no BSP and no CPU dependent) |
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| 269 | */ |
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| 270 | |
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| 271 | /* we can use the low power wait instruction for the IDLE thread */ |
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[e2040ba] | 272 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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[7908ba5b] | 273 | |
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| 274 | /* |
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| 275 | * Does the stack grow up (toward higher addresses) or down |
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| 276 | * (toward lower addresses)? |
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| 277 | * |
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| 278 | * If TRUE, then the grows upward. |
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| 279 | * If FALSE, then the grows toward smaller addresses. |
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| 280 | */ |
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| 281 | |
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| 282 | /* our stack grows down */ |
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| 283 | #define CPU_STACK_GROWS_UP FALSE |
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| 284 | |
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| 285 | /* |
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| 286 | * The following is the variable attribute used to force alignment |
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| 287 | * of critical RTEMS structures. On some processors it may make |
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| 288 | * sense to have these aligned on tighter boundaries than |
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| 289 | * the minimum requirements of the compiler in order to have as |
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| 290 | * much of the critical data area as possible in a cache line. |
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| 291 | * |
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| 292 | * The placement of this macro in the declaration of the variables |
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| 293 | * is based on the syntactically requirements of the GNU C |
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| 294 | * "__attribute__" extension. For example with GNU C, use |
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| 295 | * the following to force a structures to a 32 byte boundary. |
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| 296 | * |
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| 297 | * __attribute__ ((aligned (32))) |
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| 298 | * |
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| 299 | * NOTE: Currently only the Priority Bit Map table uses this feature. |
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| 300 | * To benefit from using this, the data must be heavily |
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| 301 | * used so it will stay in the cache and used frequently enough |
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| 302 | * in the executive to justify turning this on. |
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| 303 | */ |
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| 304 | |
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| 305 | /* our cache line size is 16 bytes */ |
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| 306 | #if __GNUC__ |
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| 307 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) |
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| 308 | #else |
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[e2040ba] | 309 | #define CPU_STRUCTURE_ALIGNMENT |
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[7908ba5b] | 310 | #endif |
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| 311 | |
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| 312 | /* |
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| 313 | * Define what is required to specify how the network to host conversion |
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| 314 | * routines are handled. |
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| 315 | */ |
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| 316 | |
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[01a76a6] | 317 | /* __MIPSEB__ or __MIPSEL__ is defined by GCC based on -EB or -EL command line options */ |
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| 318 | #if defined(__MIPSEB__) |
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[7908ba5b] | 319 | #define CPU_BIG_ENDIAN TRUE |
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| 320 | #define CPU_LITTLE_ENDIAN FALSE |
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[01a76a6] | 321 | #elif defined(__MIPSEL__) |
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| 322 | #define CPU_BIG_ENDIAN FALSE |
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| 323 | #define CPU_LITTLE_ENDIAN TRUE |
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| 324 | #else |
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| 325 | #error "Unknown endianness" |
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| 326 | #endif |
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[7908ba5b] | 327 | |
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| 328 | /* |
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| 329 | * The following defines the number of bits actually used in the |
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| 330 | * interrupt field of the task mode. How those bits map to the |
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| 331 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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| 332 | */ |
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| 333 | |
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[bd1ecb0] | 334 | #define CPU_MODES_INTERRUPT_MASK 0x000000ff |
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[7908ba5b] | 335 | |
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| 336 | /* |
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[5194a28] | 337 | * Processor defined structures |
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| 338 | * |
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| 339 | * Examples structures include the descriptor tables from the i386 |
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| 340 | * and the processor control structure on the i960ca. |
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[7908ba5b] | 341 | */ |
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| 342 | |
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| 343 | /* may need to put some structures here. */ |
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| 344 | |
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| 345 | /* |
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| 346 | * Contexts |
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| 347 | * |
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| 348 | * Generally there are 2 types of context to save. |
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| 349 | * 1. Interrupt registers to save |
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| 350 | * 2. Task level registers to save |
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| 351 | * |
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| 352 | * This means we have the following 3 context items: |
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| 353 | * 1. task level context stuff:: Context_Control |
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| 354 | * 2. floating point task stuff:: Context_Control_fp |
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| 355 | * 3. special interrupt level context :: Context_Control_interrupt |
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| 356 | * |
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| 357 | * On some processors, it is cost-effective to save only the callee |
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| 358 | * preserved registers during a task context switch. This means |
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| 359 | * that the ISR code needs to save those registers which do not |
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| 360 | * persist across function calls. It is not mandatory to make this |
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| 361 | * distinctions between the caller/callee saves registers for the |
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| 362 | * purpose of minimizing context saved during task switch and on interrupts. |
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| 363 | * If the cost of saving extra registers is minimal, simplicity is the |
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| 364 | * choice. Save the same context on interrupt entry as for tasks in |
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| 365 | * this case. |
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| 366 | * |
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| 367 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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| 368 | * care should be used in designing the context area. |
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| 369 | * |
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| 370 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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| 371 | * structure will not be used or it simply consist of an array of a |
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| 372 | * fixed number of bytes. This is done when the floating point context |
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| 373 | * is dumped by a "FP save context" type instruction and the format |
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| 374 | * is not really defined by the CPU. In this case, there is no need |
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| 375 | * to figure out the exact format -- only the size. Of course, although |
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| 376 | * this is enough information for RTEMS, it is probably not enough for |
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| 377 | * a debugger such as gdb. But that is another problem. |
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| 378 | */ |
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| 379 | |
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[9787ee22] | 380 | #ifndef ASM |
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[bd1ecb0] | 381 | |
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[7908ba5b] | 382 | /* WARNING: If this structure is modified, the constants in cpu.h must be updated. */ |
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[5194a28] | 383 | #if (__mips == 1) || (__mips == 32) |
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[5bb38e15] | 384 | #define __MIPS_REGISTER_TYPE uint32_t |
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| 385 | #define __MIPS_FPU_REGISTER_TYPE uint32_t |
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[2e549dad] | 386 | #elif __mips == 3 |
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[5bb38e15] | 387 | #define __MIPS_REGISTER_TYPE uint64_t |
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| 388 | #define __MIPS_FPU_REGISTER_TYPE uint64_t |
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[5d7bfce3] | 389 | #else |
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[2e549dad] | 390 | #error "mips register size: unknown architecture level!!" |
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[5d7bfce3] | 391 | #endif |
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[2e549dad] | 392 | typedef struct { |
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| 393 | __MIPS_REGISTER_TYPE s0; |
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| 394 | __MIPS_REGISTER_TYPE s1; |
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| 395 | __MIPS_REGISTER_TYPE s2; |
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| 396 | __MIPS_REGISTER_TYPE s3; |
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| 397 | __MIPS_REGISTER_TYPE s4; |
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| 398 | __MIPS_REGISTER_TYPE s5; |
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| 399 | __MIPS_REGISTER_TYPE s6; |
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| 400 | __MIPS_REGISTER_TYPE s7; |
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| 401 | __MIPS_REGISTER_TYPE sp; |
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| 402 | __MIPS_REGISTER_TYPE fp; |
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| 403 | __MIPS_REGISTER_TYPE ra; |
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| 404 | __MIPS_REGISTER_TYPE c0_sr; |
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[8264d23] | 405 | __MIPS_REGISTER_TYPE c0_epc; |
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[7908ba5b] | 406 | } Context_Control; |
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| 407 | |
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[0ca6d0d9] | 408 | #define _CPU_Context_Get_SP( _context ) \ |
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[a0cb87c] | 409 | (uintptr_t) (_context)->sp |
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[0ca6d0d9] | 410 | |
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[2e549dad] | 411 | /* WARNING: If this structure is modified, the constants in cpu.h |
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| 412 | * must also be updated. |
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| 413 | */ |
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| 414 | |
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[7908ba5b] | 415 | typedef struct { |
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[2e549dad] | 416 | #if ( CPU_HARDWARE_FP == TRUE ) |
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| 417 | __MIPS_FPU_REGISTER_TYPE fp0; |
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| 418 | __MIPS_FPU_REGISTER_TYPE fp1; |
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| 419 | __MIPS_FPU_REGISTER_TYPE fp2; |
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| 420 | __MIPS_FPU_REGISTER_TYPE fp3; |
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| 421 | __MIPS_FPU_REGISTER_TYPE fp4; |
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| 422 | __MIPS_FPU_REGISTER_TYPE fp5; |
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| 423 | __MIPS_FPU_REGISTER_TYPE fp6; |
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| 424 | __MIPS_FPU_REGISTER_TYPE fp7; |
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| 425 | __MIPS_FPU_REGISTER_TYPE fp8; |
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| 426 | __MIPS_FPU_REGISTER_TYPE fp9; |
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| 427 | __MIPS_FPU_REGISTER_TYPE fp10; |
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| 428 | __MIPS_FPU_REGISTER_TYPE fp11; |
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| 429 | __MIPS_FPU_REGISTER_TYPE fp12; |
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| 430 | __MIPS_FPU_REGISTER_TYPE fp13; |
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| 431 | __MIPS_FPU_REGISTER_TYPE fp14; |
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| 432 | __MIPS_FPU_REGISTER_TYPE fp15; |
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| 433 | __MIPS_FPU_REGISTER_TYPE fp16; |
---|
| 434 | __MIPS_FPU_REGISTER_TYPE fp17; |
---|
| 435 | __MIPS_FPU_REGISTER_TYPE fp18; |
---|
| 436 | __MIPS_FPU_REGISTER_TYPE fp19; |
---|
| 437 | __MIPS_FPU_REGISTER_TYPE fp20; |
---|
| 438 | __MIPS_FPU_REGISTER_TYPE fp21; |
---|
| 439 | __MIPS_FPU_REGISTER_TYPE fp22; |
---|
| 440 | __MIPS_FPU_REGISTER_TYPE fp23; |
---|
| 441 | __MIPS_FPU_REGISTER_TYPE fp24; |
---|
| 442 | __MIPS_FPU_REGISTER_TYPE fp25; |
---|
| 443 | __MIPS_FPU_REGISTER_TYPE fp26; |
---|
| 444 | __MIPS_FPU_REGISTER_TYPE fp27; |
---|
| 445 | __MIPS_FPU_REGISTER_TYPE fp28; |
---|
| 446 | __MIPS_FPU_REGISTER_TYPE fp29; |
---|
| 447 | __MIPS_FPU_REGISTER_TYPE fp30; |
---|
| 448 | __MIPS_FPU_REGISTER_TYPE fp31; |
---|
[7c99007] | 449 | uint32_t fpcs; |
---|
[2e549dad] | 450 | #endif |
---|
[7908ba5b] | 451 | } Context_Control_fp; |
---|
| 452 | |
---|
[e2040ba] | 453 | /* |
---|
[a37b8f95] | 454 | * This struct reflects the stack frame employed in ISR_Handler. Note |
---|
| 455 | * that the ISR routine save some of the registers to this frame for |
---|
| 456 | * all interrupts and exceptions. Other registers are saved only on |
---|
[5bb38e15] | 457 | * exceptions, while others are not touched at all. The untouched |
---|
| 458 | * registers are not normally disturbed by high-level language |
---|
[a37b8f95] | 459 | * programs so they can be accessed when required. |
---|
| 460 | * |
---|
| 461 | * The registers and their ordering in this struct must directly |
---|
| 462 | * correspond to the layout and ordering of * shown in iregdef.h, |
---|
[5bb38e15] | 463 | * as cpu_asm.S uses those definitions to fill the stack frame. |
---|
[a37b8f95] | 464 | * This struct provides access to the stack frame for C code. |
---|
| 465 | * |
---|
| 466 | * Similarly, this structure is used by debugger stubs and exception |
---|
| 467 | * processing routines so be careful when changing the format. |
---|
| 468 | * |
---|
[9099a85] | 469 | * NOTE: The comments with this structure and cpu_asm.S should be kept |
---|
[a37b8f95] | 470 | * in sync. When in doubt, look in the code to see if the |
---|
| 471 | * registers you're interested in are actually treated as expected. |
---|
[9099a85] | 472 | * The order of the first portion of this structure follows the |
---|
| 473 | * order of registers expected by gdb. |
---|
[a37b8f95] | 474 | */ |
---|
[e2040ba] | 475 | |
---|
| 476 | typedef struct |
---|
| 477 | { |
---|
[9099a85] | 478 | __MIPS_REGISTER_TYPE r0; /* 0 -- NOT FILLED IN */ |
---|
| 479 | __MIPS_REGISTER_TYPE at; /* 1 -- saved always */ |
---|
| 480 | __MIPS_REGISTER_TYPE v0; /* 2 -- saved always */ |
---|
| 481 | __MIPS_REGISTER_TYPE v1; /* 3 -- saved always */ |
---|
| 482 | __MIPS_REGISTER_TYPE a0; /* 4 -- saved always */ |
---|
| 483 | __MIPS_REGISTER_TYPE a1; /* 5 -- saved always */ |
---|
| 484 | __MIPS_REGISTER_TYPE a2; /* 6 -- saved always */ |
---|
| 485 | __MIPS_REGISTER_TYPE a3; /* 7 -- saved always */ |
---|
| 486 | __MIPS_REGISTER_TYPE t0; /* 8 -- saved always */ |
---|
| 487 | __MIPS_REGISTER_TYPE t1; /* 9 -- saved always */ |
---|
| 488 | __MIPS_REGISTER_TYPE t2; /* 10 -- saved always */ |
---|
| 489 | __MIPS_REGISTER_TYPE t3; /* 11 -- saved always */ |
---|
| 490 | __MIPS_REGISTER_TYPE t4; /* 12 -- saved always */ |
---|
| 491 | __MIPS_REGISTER_TYPE t5; /* 13 -- saved always */ |
---|
| 492 | __MIPS_REGISTER_TYPE t6; /* 14 -- saved always */ |
---|
| 493 | __MIPS_REGISTER_TYPE t7; /* 15 -- saved always */ |
---|
| 494 | __MIPS_REGISTER_TYPE s0; /* 16 -- saved on exceptions */ |
---|
| 495 | __MIPS_REGISTER_TYPE s1; /* 17 -- saved on exceptions */ |
---|
| 496 | __MIPS_REGISTER_TYPE s2; /* 18 -- saved on exceptions */ |
---|
| 497 | __MIPS_REGISTER_TYPE s3; /* 19 -- saved on exceptions */ |
---|
| 498 | __MIPS_REGISTER_TYPE s4; /* 20 -- saved on exceptions */ |
---|
| 499 | __MIPS_REGISTER_TYPE s5; /* 21 -- saved on exceptions */ |
---|
| 500 | __MIPS_REGISTER_TYPE s6; /* 22 -- saved on exceptions */ |
---|
| 501 | __MIPS_REGISTER_TYPE s7; /* 23 -- saved on exceptions */ |
---|
| 502 | __MIPS_REGISTER_TYPE t8; /* 24 -- saved always */ |
---|
| 503 | __MIPS_REGISTER_TYPE t9; /* 25 -- saved always */ |
---|
| 504 | __MIPS_REGISTER_TYPE k0; /* 26 -- NOT FILLED IN, kernel tmp reg */ |
---|
| 505 | __MIPS_REGISTER_TYPE k1; /* 27 -- NOT FILLED IN, kernel tmp reg */ |
---|
| 506 | __MIPS_REGISTER_TYPE gp; /* 28 -- saved always */ |
---|
| 507 | __MIPS_REGISTER_TYPE sp; /* 29 -- saved on exceptions NOT RESTORED */ |
---|
| 508 | __MIPS_REGISTER_TYPE fp; /* 30 -- saved always */ |
---|
| 509 | __MIPS_REGISTER_TYPE ra; /* 31 -- saved always */ |
---|
| 510 | __MIPS_REGISTER_TYPE c0_sr; /* 32 -- saved always, some bits are */ |
---|
[a37b8f95] | 511 | /* manipulated per-thread */ |
---|
[9099a85] | 512 | __MIPS_REGISTER_TYPE mdlo; /* 33 -- saved always */ |
---|
| 513 | __MIPS_REGISTER_TYPE mdhi; /* 34 -- saved always */ |
---|
| 514 | __MIPS_REGISTER_TYPE badvaddr; /* 35 -- saved on exceptions, read-only */ |
---|
| 515 | __MIPS_REGISTER_TYPE cause; /* 36 -- saved on exceptions NOT restored */ |
---|
| 516 | __MIPS_REGISTER_TYPE epc; /* 37 -- saved always, read-only register */ |
---|
| 517 | /* but logically restored */ |
---|
| 518 | __MIPS_FPU_REGISTER_TYPE f0; /* 38 -- saved if FP enabled */ |
---|
| 519 | __MIPS_FPU_REGISTER_TYPE f1; /* 39 -- saved if FP enabled */ |
---|
| 520 | __MIPS_FPU_REGISTER_TYPE f2; /* 40 -- saved if FP enabled */ |
---|
| 521 | __MIPS_FPU_REGISTER_TYPE f3; /* 41 -- saved if FP enabled */ |
---|
| 522 | __MIPS_FPU_REGISTER_TYPE f4; /* 42 -- saved if FP enabled */ |
---|
| 523 | __MIPS_FPU_REGISTER_TYPE f5; /* 43 -- saved if FP enabled */ |
---|
| 524 | __MIPS_FPU_REGISTER_TYPE f6; /* 44 -- saved if FP enabled */ |
---|
| 525 | __MIPS_FPU_REGISTER_TYPE f7; /* 45 -- saved if FP enabled */ |
---|
| 526 | __MIPS_FPU_REGISTER_TYPE f8; /* 46 -- saved if FP enabled */ |
---|
| 527 | __MIPS_FPU_REGISTER_TYPE f9; /* 47 -- saved if FP enabled */ |
---|
| 528 | __MIPS_FPU_REGISTER_TYPE f10; /* 48 -- saved if FP enabled */ |
---|
| 529 | __MIPS_FPU_REGISTER_TYPE f11; /* 49 -- saved if FP enabled */ |
---|
| 530 | __MIPS_FPU_REGISTER_TYPE f12; /* 50 -- saved if FP enabled */ |
---|
| 531 | __MIPS_FPU_REGISTER_TYPE f13; /* 51 -- saved if FP enabled */ |
---|
| 532 | __MIPS_FPU_REGISTER_TYPE f14; /* 52 -- saved if FP enabled */ |
---|
| 533 | __MIPS_FPU_REGISTER_TYPE f15; /* 53 -- saved if FP enabled */ |
---|
| 534 | __MIPS_FPU_REGISTER_TYPE f16; /* 54 -- saved if FP enabled */ |
---|
| 535 | __MIPS_FPU_REGISTER_TYPE f17; /* 55 -- saved if FP enabled */ |
---|
| 536 | __MIPS_FPU_REGISTER_TYPE f18; /* 56 -- saved if FP enabled */ |
---|
| 537 | __MIPS_FPU_REGISTER_TYPE f19; /* 57 -- saved if FP enabled */ |
---|
| 538 | __MIPS_FPU_REGISTER_TYPE f20; /* 58 -- saved if FP enabled */ |
---|
| 539 | __MIPS_FPU_REGISTER_TYPE f21; /* 59 -- saved if FP enabled */ |
---|
| 540 | __MIPS_FPU_REGISTER_TYPE f22; /* 60 -- saved if FP enabled */ |
---|
| 541 | __MIPS_FPU_REGISTER_TYPE f23; /* 61 -- saved if FP enabled */ |
---|
| 542 | __MIPS_FPU_REGISTER_TYPE f24; /* 62 -- saved if FP enabled */ |
---|
| 543 | __MIPS_FPU_REGISTER_TYPE f25; /* 63 -- saved if FP enabled */ |
---|
| 544 | __MIPS_FPU_REGISTER_TYPE f26; /* 64 -- saved if FP enabled */ |
---|
| 545 | __MIPS_FPU_REGISTER_TYPE f27; /* 65 -- saved if FP enabled */ |
---|
| 546 | __MIPS_FPU_REGISTER_TYPE f28; /* 66 -- saved if FP enabled */ |
---|
| 547 | __MIPS_FPU_REGISTER_TYPE f29; /* 67 -- saved if FP enabled */ |
---|
| 548 | __MIPS_FPU_REGISTER_TYPE f30; /* 68 -- saved if FP enabled */ |
---|
| 549 | __MIPS_FPU_REGISTER_TYPE f31; /* 69 -- saved if FP enabled */ |
---|
| 550 | __MIPS_REGISTER_TYPE fcsr; /* 70 -- saved on exceptions */ |
---|
| 551 | /* (oddly not documented on MGV) */ |
---|
| 552 | __MIPS_REGISTER_TYPE feir; /* 71 -- saved on exceptions */ |
---|
| 553 | /* (oddly not documented on MGV) */ |
---|
[a37b8f95] | 554 | |
---|
[9099a85] | 555 | /* GDB does not seem to care about anything past this point */ |
---|
| 556 | |
---|
| 557 | __MIPS_REGISTER_TYPE tlbhi; /* 72 - NOT FILLED IN, doesn't exist on */ |
---|
[a37b8f95] | 558 | /* all MIPS CPUs (at least MGV) */ |
---|
[e2040ba] | 559 | #if __mips == 1 |
---|
[9099a85] | 560 | __MIPS_REGISTER_TYPE tlblo; /* 73 - NOT FILLED IN, doesn't exist on */ |
---|
[a37b8f95] | 561 | /* all MIPS CPUs (at least MGV) */ |
---|
[e2040ba] | 562 | #endif |
---|
[5194a28] | 563 | #if (__mips == 3) || (__mips == 32) |
---|
[9099a85] | 564 | __MIPS_REGISTER_TYPE tlblo0; /* 73 - NOT FILLED IN, doesn't exist on */ |
---|
[a37b8f95] | 565 | /* all MIPS CPUs (at least MGV) */ |
---|
[e2040ba] | 566 | #endif |
---|
[a37b8f95] | 567 | |
---|
[9099a85] | 568 | __MIPS_REGISTER_TYPE inx; /* 74 -- NOT FILLED IN, doesn't exist on */ |
---|
[a37b8f95] | 569 | /* all MIPS CPUs (at least MGV) */ |
---|
[9099a85] | 570 | __MIPS_REGISTER_TYPE rand; /* 75 -- NOT FILLED IN, doesn't exist on */ |
---|
[a37b8f95] | 571 | /* all MIPS CPUs (at least MGV) */ |
---|
[9099a85] | 572 | __MIPS_REGISTER_TYPE ctxt; /* 76 -- NOT FILLED IN, doesn't exist on */ |
---|
[a37b8f95] | 573 | /* all MIPS CPUs (at least MGV) */ |
---|
[9099a85] | 574 | __MIPS_REGISTER_TYPE exctype; /* 77 -- NOT FILLED IN (not enough info) */ |
---|
| 575 | __MIPS_REGISTER_TYPE mode; /* 78 -- NOT FILLED IN (not enough info) */ |
---|
| 576 | __MIPS_REGISTER_TYPE prid; /* 79 -- NOT FILLED IN (not need to do so) */ |
---|
[293c0e30] | 577 | __MIPS_REGISTER_TYPE tar ; /* 80 -- target address register, filled on exceptions */ |
---|
| 578 | /* end of __mips == 1 so NREGS == 81 */ |
---|
[5194a28] | 579 | #if (__mips == 3) || (__mips == 32) |
---|
[293c0e30] | 580 | __MIPS_REGISTER_TYPE tlblo1; /* 81 -- NOT FILLED IN */ |
---|
| 581 | __MIPS_REGISTER_TYPE pagemask; /* 82 -- NOT FILLED IN */ |
---|
| 582 | __MIPS_REGISTER_TYPE wired; /* 83 -- NOT FILLED IN */ |
---|
| 583 | __MIPS_REGISTER_TYPE count; /* 84 -- NOT FILLED IN */ |
---|
| 584 | __MIPS_REGISTER_TYPE compare; /* 85 -- NOT FILLED IN */ |
---|
| 585 | __MIPS_REGISTER_TYPE config; /* 86 -- NOT FILLED IN */ |
---|
| 586 | __MIPS_REGISTER_TYPE lladdr; /* 87 -- NOT FILLED IN */ |
---|
| 587 | __MIPS_REGISTER_TYPE watchlo; /* 88 -- NOT FILLED IN */ |
---|
| 588 | __MIPS_REGISTER_TYPE watchhi; /* 89 -- NOT FILLED IN */ |
---|
| 589 | __MIPS_REGISTER_TYPE ecc; /* 90 -- NOT FILLED IN */ |
---|
| 590 | __MIPS_REGISTER_TYPE cacheerr; /* 91 -- NOT FILLED IN */ |
---|
| 591 | __MIPS_REGISTER_TYPE taglo; /* 92 -- NOT FILLED IN */ |
---|
| 592 | __MIPS_REGISTER_TYPE taghi; /* 93 -- NOT FILLED IN */ |
---|
| 593 | __MIPS_REGISTER_TYPE errpc; /* 94 -- NOT FILLED IN */ |
---|
| 594 | __MIPS_REGISTER_TYPE xctxt; /* 95 -- NOT FILLED IN */ |
---|
| 595 | /* end of __mips == 3 so NREGS == 96 */ |
---|
[a37b8f95] | 596 | #endif |
---|
| 597 | |
---|
[7908ba5b] | 598 | } CPU_Interrupt_frame; |
---|
| 599 | |
---|
| 600 | /* |
---|
| 601 | * This variable is optional. It is used on CPUs on which it is difficult |
---|
| 602 | * to generate an "uninitialized" FP context. It is filled in by |
---|
| 603 | * _CPU_Initialize and copied into the task's FP context area during |
---|
| 604 | * _CPU_Context_Initialize. |
---|
| 605 | */ |
---|
| 606 | |
---|
| 607 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
---|
| 608 | |
---|
| 609 | /* |
---|
| 610 | * Nothing prevents the porter from declaring more CPU specific variables. |
---|
| 611 | */ |
---|
| 612 | |
---|
| 613 | /* XXX: if needed, put more variables here */ |
---|
| 614 | |
---|
| 615 | /* |
---|
| 616 | * The size of the floating point context area. On some CPUs this |
---|
| 617 | * will not be a "sizeof" because the format of the floating point |
---|
| 618 | * area is not defined -- only the size is. This is usually on |
---|
| 619 | * CPUs with a "floating point save context" instruction. |
---|
| 620 | */ |
---|
| 621 | |
---|
| 622 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
| 623 | |
---|
| 624 | /* |
---|
| 625 | * Amount of extra stack (above minimum stack size) required by |
---|
| 626 | * system initialization thread. Remember that in a multiprocessor |
---|
| 627 | * system the system intialization thread becomes the MP server thread. |
---|
| 628 | */ |
---|
| 629 | |
---|
| 630 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
---|
| 631 | |
---|
| 632 | /* |
---|
| 633 | * This defines the number of entries in the ISR_Vector_table managed |
---|
| 634 | * by RTEMS. |
---|
| 635 | */ |
---|
| 636 | |
---|
[32f415d] | 637 | extern unsigned int mips_interrupt_number_of_vectors; |
---|
[797d88ba] | 638 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS (mips_interrupt_number_of_vectors) |
---|
[7908ba5b] | 639 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
---|
| 640 | |
---|
| 641 | /* |
---|
[ece004d] | 642 | * Should be large enough to run all RTEMS tests. This ensures |
---|
[7908ba5b] | 643 | * that a "reasonable" small application should not have any problems. |
---|
| 644 | */ |
---|
| 645 | |
---|
[5a5bfea5] | 646 | #define CPU_STACK_MINIMUM_SIZE (8 * 1024) |
---|
[7908ba5b] | 647 | |
---|
| 648 | /* |
---|
| 649 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
| 650 | * alignment does not take into account the requirements for the stack. |
---|
| 651 | */ |
---|
| 652 | |
---|
| 653 | #define CPU_ALIGNMENT 8 |
---|
| 654 | |
---|
| 655 | /* |
---|
| 656 | * This number corresponds to the byte alignment requirement for the |
---|
| 657 | * heap handler. This alignment requirement may be stricter than that |
---|
| 658 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
| 659 | * common for the heap to follow the same alignment requirement as |
---|
| 660 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
| 661 | * then this should be set to CPU_ALIGNMENT. |
---|
| 662 | * |
---|
| 663 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 664 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 665 | */ |
---|
| 666 | |
---|
| 667 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
| 668 | |
---|
| 669 | /* |
---|
| 670 | * This number corresponds to the byte alignment requirement for memory |
---|
| 671 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 672 | * may be stricter than that for the data types alignment specified by |
---|
| 673 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 674 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
| 675 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
| 676 | * |
---|
| 677 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 678 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 679 | */ |
---|
| 680 | |
---|
| 681 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
| 682 | |
---|
| 683 | /* |
---|
| 684 | * This number corresponds to the byte alignment requirement for the |
---|
| 685 | * stack. This alignment requirement may be stricter than that for the |
---|
| 686 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
| 687 | * is strict enough for the stack, then this should be set to 0. |
---|
| 688 | * |
---|
| 689 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
| 690 | */ |
---|
| 691 | |
---|
| 692 | #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT |
---|
| 693 | |
---|
[9fd4f5c5] | 694 | /* |
---|
| 695 | * ISR handler macros |
---|
| 696 | */ |
---|
| 697 | |
---|
| 698 | /* |
---|
| 699 | * Support routine to initialize the RTEMS vector table after it is allocated. |
---|
| 700 | */ |
---|
| 701 | |
---|
| 702 | #define _CPU_Initialize_vectors() |
---|
[7908ba5b] | 703 | |
---|
[7c99007] | 704 | /* |
---|
| 705 | * Declare the function that is present in the shared libcpu directory, |
---|
| 706 | * that returns the processor dependent interrupt mask. |
---|
| 707 | */ |
---|
| 708 | |
---|
| 709 | uint32_t mips_interrupt_mask( void ); |
---|
| 710 | |
---|
[7908ba5b] | 711 | /* |
---|
| 712 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
| 713 | * level is returned in _level. |
---|
| 714 | */ |
---|
| 715 | |
---|
[32f415d] | 716 | #define _CPU_ISR_Disable( _level ) \ |
---|
| 717 | do { \ |
---|
[293c0e30] | 718 | unsigned int _scratch; \ |
---|
| 719 | mips_get_sr( _scratch ); \ |
---|
| 720 | mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \ |
---|
| 721 | _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \ |
---|
[32f415d] | 722 | } while(0) |
---|
[7908ba5b] | 723 | |
---|
| 724 | /* |
---|
| 725 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
| 726 | * This indicates the end of an RTEMS critical section. The parameter |
---|
| 727 | * _level is not modified. |
---|
| 728 | */ |
---|
| 729 | |
---|
| 730 | #define _CPU_ISR_Enable( _level ) \ |
---|
[32f415d] | 731 | do { \ |
---|
[e6dec71c] | 732 | unsigned int _scratch; \ |
---|
| 733 | mips_get_sr( _scratch ); \ |
---|
| 734 | mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \ |
---|
[32f415d] | 735 | } while(0) |
---|
[7908ba5b] | 736 | |
---|
| 737 | /* |
---|
| 738 | * This temporarily restores the interrupt to _level before immediately |
---|
| 739 | * disabling them again. This is used to divide long RTEMS critical |
---|
| 740 | * sections into two or more parts. The parameter _level is not |
---|
[e6dec71c] | 741 | * modified. |
---|
[7908ba5b] | 742 | */ |
---|
| 743 | |
---|
| 744 | #define _CPU_ISR_Flash( _xlevel ) \ |
---|
[32f415d] | 745 | do { \ |
---|
[293c0e30] | 746 | unsigned int _scratch2 = _xlevel; \ |
---|
| 747 | _CPU_ISR_Enable( _scratch2 ); \ |
---|
| 748 | _CPU_ISR_Disable( _scratch2 ); \ |
---|
| 749 | _xlevel = _scratch2; \ |
---|
[32f415d] | 750 | } while(0) |
---|
[7908ba5b] | 751 | |
---|
| 752 | /* |
---|
| 753 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
| 754 | * actually provides. Currently, interrupt levels which do not |
---|
| 755 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
| 756 | * it would be nice if these were "mapped" by the application |
---|
| 757 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
| 758 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
| 759 | * This could be used to manage a programmable interrupt controller |
---|
| 760 | * via the rtems_task_mode directive. |
---|
[32f415d] | 761 | * |
---|
[e2040ba] | 762 | * On the MIPS, 0 is all on. Non-zero is all off. This only |
---|
[32f415d] | 763 | * manipulates the IEC. |
---|
[7908ba5b] | 764 | */ |
---|
[32f415d] | 765 | |
---|
[c346f33d] | 766 | uint32_t _CPU_ISR_Get_level( void ); /* in cpu.c */ |
---|
[2e549dad] | 767 | |
---|
[c346f33d] | 768 | void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */ |
---|
[7908ba5b] | 769 | |
---|
| 770 | /* end of ISR handler macros */ |
---|
| 771 | |
---|
| 772 | /* Context handler macros */ |
---|
| 773 | |
---|
| 774 | /* |
---|
| 775 | * Initialize the context to a state suitable for starting a |
---|
| 776 | * task after a context restore operation. Generally, this |
---|
| 777 | * involves: |
---|
| 778 | * |
---|
| 779 | * - setting a starting address |
---|
| 780 | * - preparing the stack |
---|
| 781 | * - preparing the stack and frame pointers |
---|
| 782 | * - setting the proper interrupt level in the context |
---|
| 783 | * - initializing the floating point context |
---|
| 784 | * |
---|
| 785 | * This routine generally does not set any unnecessary register |
---|
| 786 | * in the context. The state of the "general data" registers is |
---|
| 787 | * undefined at task start time. |
---|
| 788 | * |
---|
| 789 | * NOTE: This is_fp parameter is TRUE if the thread is to be a floating |
---|
| 790 | * point thread. This is typically only used on CPUs where the |
---|
| 791 | * FPU may be easily disabled by software such as on the SPARC |
---|
| 792 | * where the PSR contains an enable FPU bit. |
---|
[e6dec71c] | 793 | * |
---|
| 794 | * The per-thread status register holds the interrupt enable, FP enable |
---|
| 795 | * and global interrupt enable for that thread. It means each thread can |
---|
| 796 | * enable its own set of interrupts. If interrupts are disabled, RTEMS |
---|
[5bb38e15] | 797 | * can still dispatch via blocking calls. This is the function of the |
---|
| 798 | * "Interrupt Level", and on the MIPS, it controls the IEC bit and all |
---|
[e6dec71c] | 799 | * the hardware interrupts as defined in the SR. Software ints |
---|
[5bb38e15] | 800 | * are automatically enabled for all threads, as they will only occur under |
---|
| 801 | * program control anyhow. Besides, the interrupt level parm is only 8 bits, |
---|
[e6dec71c] | 802 | * and controlling the software ints plus the others would require 9. |
---|
| 803 | * |
---|
[5bb38e15] | 804 | * If the Interrupt Level is 0, all ints are on. Otherwise, the |
---|
| 805 | * Interrupt Level should supply a bit pattern to impose on the SR |
---|
[e6dec71c] | 806 | * interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6 |
---|
[5bb38e15] | 807 | * apply to the SR register Intr bits from bit 10 thru bit 15. Bit 7 of |
---|
[e6dec71c] | 808 | * the Interrupt Level parameter is unused at this time. |
---|
| 809 | * |
---|
| 810 | * These are the only per-thread SR bits, the others are maintained |
---|
| 811 | * globally & explicitly preserved by the Context Switch code in cpu_asm.s |
---|
[7908ba5b] | 812 | */ |
---|
| 813 | |
---|
[e6dec71c] | 814 | |
---|
[5194a28] | 815 | #if (__mips == 3) || (__mips == 32) |
---|
| 816 | #define _INTON SR_IE |
---|
[7c99007] | 817 | #if __mips_fpr==64 |
---|
| 818 | #define _EXTRABITS SR_FR |
---|
| 819 | #else |
---|
[bd1ecb0] | 820 | #define _EXTRABITS 0 |
---|
[7c99007] | 821 | #endif /* __mips_fpr==64 */ |
---|
| 822 | #endif /* __mips == 3 */ |
---|
[e6dec71c] | 823 | #if __mips == 1 |
---|
[bd1ecb0] | 824 | #define _INTON SR_IEC |
---|
| 825 | #define _EXTRABITS 0 /* make sure we're in user mode on MIPS1 processors */ |
---|
[7c99007] | 826 | #endif /* __mips == 1 */ |
---|
[e6dec71c] | 827 | |
---|
[7908ba5b] | 828 | |
---|
[a0cb87c] | 829 | void _CPU_Context_Initialize( |
---|
| 830 | Context_Control *the_context, |
---|
| 831 | uintptr_t *stack_base, |
---|
| 832 | uint32_t size, |
---|
| 833 | uint32_t new_level, |
---|
| 834 | void *entry_point, |
---|
| 835 | bool is_fp |
---|
| 836 | ); |
---|
[e6dec71c] | 837 | |
---|
| 838 | |
---|
[7908ba5b] | 839 | /* |
---|
| 840 | * This routine is responsible for somehow restarting the currently |
---|
| 841 | * executing task. If you are lucky, then all that is necessary |
---|
| 842 | * is restoring the context. Otherwise, there will need to be |
---|
| 843 | * a special assembly routine which does something special in this |
---|
| 844 | * case. Context_Restore should work most of the time. It will |
---|
| 845 | * not work if restarting self conflicts with the stack frame |
---|
| 846 | * assumptions of restoring a context. |
---|
| 847 | */ |
---|
| 848 | |
---|
| 849 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 850 | _CPU_Context_restore( (_the_context) ); |
---|
| 851 | |
---|
| 852 | /* |
---|
| 853 | * The purpose of this macro is to allow the initial pointer into |
---|
| 854 | * A floating point context area (used to save the floating point |
---|
| 855 | * context) to be at an arbitrary place in the floating point |
---|
| 856 | * context area. |
---|
| 857 | * |
---|
| 858 | * This is necessary because some FP units are designed to have |
---|
| 859 | * their context saved as a stack which grows into lower addresses. |
---|
| 860 | * Other FP units can be saved by simply moving registers into offsets |
---|
| 861 | * from the base of the context area. Finally some FP units provide |
---|
| 862 | * a "dump context" instruction which could fill in from high to low |
---|
| 863 | * or low to high based on the whim of the CPU designers. |
---|
| 864 | */ |
---|
| 865 | |
---|
| 866 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
| 867 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
| 868 | |
---|
| 869 | /* |
---|
| 870 | * This routine initializes the FP context area passed to it to. |
---|
| 871 | * There are a few standard ways in which to initialize the |
---|
| 872 | * floating point context. The code included for this macro assumes |
---|
| 873 | * that this is a CPU in which a "initial" FP context was saved into |
---|
| 874 | * _CPU_Null_fp_context and it simply copies it to the destination |
---|
| 875 | * context passed to it. |
---|
| 876 | * |
---|
| 877 | * Other models include (1) not doing anything, and (2) putting |
---|
| 878 | * a "null FP status word" in the correct place in the FP context. |
---|
| 879 | */ |
---|
| 880 | |
---|
[2e549dad] | 881 | #if ( CPU_HARDWARE_FP == TRUE ) |
---|
[7908ba5b] | 882 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
| 883 | { \ |
---|
[0edd196] | 884 | *(*(_destination)) = _CPU_Null_fp_context; \ |
---|
[7908ba5b] | 885 | } |
---|
[2e549dad] | 886 | #endif |
---|
[7908ba5b] | 887 | |
---|
| 888 | /* end of Context handler macros */ |
---|
| 889 | |
---|
| 890 | /* Fatal Error manager macros */ |
---|
| 891 | |
---|
| 892 | /* |
---|
| 893 | * This routine copies _error into a known place -- typically a stack |
---|
| 894 | * location or a register, optionally disables interrupts, and |
---|
| 895 | * halts/stops the CPU. |
---|
| 896 | */ |
---|
| 897 | |
---|
| 898 | #define _CPU_Fatal_halt( _error ) \ |
---|
[32f415d] | 899 | do { \ |
---|
| 900 | unsigned int _level; \ |
---|
| 901 | _CPU_ISR_Disable(_level); \ |
---|
[aa7f8a1f] | 902 | loop: goto loop; \ |
---|
[32f415d] | 903 | } while (0) |
---|
[7908ba5b] | 904 | |
---|
[aa7f8a1f] | 905 | |
---|
| 906 | extern void mips_break( int error ); |
---|
[7908ba5b] | 907 | |
---|
| 908 | /* Bitfield handler macros */ |
---|
| 909 | |
---|
| 910 | /* |
---|
| 911 | * This routine sets _output to the bit number of the first bit |
---|
[4ef13360] | 912 | * set in _value. _value is of CPU dependent type Priority_bit_map_Control. |
---|
[7908ba5b] | 913 | * This type may be either 16 or 32 bits wide although only the 16 |
---|
| 914 | * least significant bits will be used. |
---|
| 915 | * |
---|
| 916 | * There are a number of variables in using a "find first bit" type |
---|
| 917 | * instruction. |
---|
| 918 | * |
---|
| 919 | * (1) What happens when run on a value of zero? |
---|
| 920 | * (2) Bits may be numbered from MSB to LSB or vice-versa. |
---|
| 921 | * (3) The numbering may be zero or one based. |
---|
| 922 | * (4) The "find first bit" instruction may search from MSB or LSB. |
---|
| 923 | * |
---|
| 924 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
| 925 | * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and |
---|
| 926 | * _CPU_Priority_bits_index(). These three form a set of routines |
---|
| 927 | * which must logically operate together. Bits in the _value are |
---|
| 928 | * set and cleared based on masks built by _CPU_Priority_mask(). |
---|
| 929 | * The basic major and minor values calculated by _Priority_Major() |
---|
| 930 | * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() |
---|
| 931 | * to properly range between the values returned by the "find first bit" |
---|
| 932 | * instruction. This makes it possible for _Priority_Get_highest() to |
---|
| 933 | * calculate the major and directly index into the minor table. |
---|
| 934 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
| 935 | * is the first bit found. |
---|
| 936 | * |
---|
| 937 | * This entire "find first bit" and mapping process depends heavily |
---|
| 938 | * on the manner in which a priority is broken into a major and minor |
---|
| 939 | * components with the major being the 4 MSB of a priority and minor |
---|
| 940 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
| 941 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
| 942 | * to the lowest priority. |
---|
| 943 | * |
---|
| 944 | * If your CPU does not have a "find first bit" instruction, then |
---|
| 945 | * there are ways to make do without it. Here are a handful of ways |
---|
| 946 | * to implement this in software: |
---|
| 947 | * |
---|
| 948 | * - a series of 16 bit test instructions |
---|
| 949 | * - a "binary search using if's" |
---|
| 950 | * - _number = 0 |
---|
| 951 | * if _value > 0x00ff |
---|
| 952 | * _value >>=8 |
---|
| 953 | * _number = 8; |
---|
| 954 | * |
---|
| 955 | * if _value > 0x0000f |
---|
| 956 | * _value >=8 |
---|
| 957 | * _number += 4 |
---|
| 958 | * |
---|
| 959 | * _number += bit_set_table[ _value ] |
---|
| 960 | * |
---|
| 961 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
| 962 | * bit set |
---|
| 963 | */ |
---|
| 964 | |
---|
| 965 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
| 966 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
---|
| 967 | |
---|
| 968 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 969 | |
---|
| 970 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
| 971 | { \ |
---|
| 972 | (_output) = 0; /* do something to prevent warnings */ \ |
---|
| 973 | } |
---|
| 974 | |
---|
| 975 | #endif |
---|
| 976 | |
---|
| 977 | /* end of Bitfield handler macros */ |
---|
| 978 | |
---|
| 979 | /* |
---|
| 980 | * This routine builds the mask which corresponds to the bit fields |
---|
| 981 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
---|
| 982 | * for that routine. |
---|
| 983 | */ |
---|
| 984 | |
---|
| 985 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 986 | |
---|
| 987 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
| 988 | ( 1 << (_bit_number) ) |
---|
| 989 | |
---|
| 990 | #endif |
---|
| 991 | |
---|
| 992 | /* |
---|
| 993 | * This routine translates the bit numbers returned by |
---|
| 994 | * _CPU_Bitfield_Find_first_bit() into something suitable for use as |
---|
| 995 | * a major or minor component of a priority. See the discussion |
---|
| 996 | * for that routine. |
---|
| 997 | */ |
---|
| 998 | |
---|
| 999 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 1000 | |
---|
| 1001 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
| 1002 | (_priority) |
---|
| 1003 | |
---|
| 1004 | #endif |
---|
| 1005 | |
---|
| 1006 | /* end of Priority handler macros */ |
---|
| 1007 | |
---|
| 1008 | /* functions */ |
---|
| 1009 | |
---|
| 1010 | /* |
---|
| 1011 | * _CPU_Initialize |
---|
| 1012 | * |
---|
| 1013 | * This routine performs CPU dependent initialization. |
---|
| 1014 | */ |
---|
| 1015 | |
---|
[c03e2bc] | 1016 | void _CPU_Initialize(void); |
---|
[7908ba5b] | 1017 | |
---|
| 1018 | /* |
---|
| 1019 | * _CPU_ISR_install_raw_handler |
---|
| 1020 | * |
---|
[e2040ba] | 1021 | * This routine installs a "raw" interrupt handler directly into the |
---|
[7908ba5b] | 1022 | * processor's vector table. |
---|
| 1023 | */ |
---|
[e2040ba] | 1024 | |
---|
[7908ba5b] | 1025 | void _CPU_ISR_install_raw_handler( |
---|
[c346f33d] | 1026 | uint32_t vector, |
---|
[7908ba5b] | 1027 | proc_ptr new_handler, |
---|
| 1028 | proc_ptr *old_handler |
---|
| 1029 | ); |
---|
| 1030 | |
---|
| 1031 | /* |
---|
| 1032 | * _CPU_ISR_install_vector |
---|
| 1033 | * |
---|
| 1034 | * This routine installs an interrupt vector. |
---|
| 1035 | */ |
---|
| 1036 | |
---|
| 1037 | void _CPU_ISR_install_vector( |
---|
[c346f33d] | 1038 | uint32_t vector, |
---|
[7908ba5b] | 1039 | proc_ptr new_handler, |
---|
| 1040 | proc_ptr *old_handler |
---|
| 1041 | ); |
---|
| 1042 | |
---|
| 1043 | /* |
---|
| 1044 | * _CPU_Install_interrupt_stack |
---|
| 1045 | * |
---|
| 1046 | * This routine installs the hardware interrupt stack pointer. |
---|
| 1047 | * |
---|
| 1048 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
| 1049 | * is TRUE. |
---|
| 1050 | */ |
---|
| 1051 | |
---|
| 1052 | void _CPU_Install_interrupt_stack( void ); |
---|
| 1053 | |
---|
| 1054 | /* |
---|
| 1055 | * _CPU_Internal_threads_Idle_thread_body |
---|
| 1056 | * |
---|
| 1057 | * This routine is the CPU dependent IDLE thread body. |
---|
| 1058 | * |
---|
| 1059 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
---|
| 1060 | * is TRUE. |
---|
| 1061 | */ |
---|
| 1062 | |
---|
[cca8379] | 1063 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
---|
[7908ba5b] | 1064 | |
---|
| 1065 | /* |
---|
| 1066 | * _CPU_Context_switch |
---|
| 1067 | * |
---|
| 1068 | * This routine switches from the run context to the heir context. |
---|
| 1069 | */ |
---|
| 1070 | |
---|
| 1071 | void _CPU_Context_switch( |
---|
| 1072 | Context_Control *run, |
---|
| 1073 | Context_Control *heir |
---|
| 1074 | ); |
---|
| 1075 | |
---|
| 1076 | /* |
---|
| 1077 | * _CPU_Context_restore |
---|
| 1078 | * |
---|
| 1079 | * This routine is generally used only to restart self in an |
---|
| 1080 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
| 1081 | * |
---|
| 1082 | * NOTE: May be unnecessary to reload some registers. |
---|
| 1083 | */ |
---|
| 1084 | |
---|
| 1085 | void _CPU_Context_restore( |
---|
| 1086 | Context_Control *new_context |
---|
| 1087 | ); |
---|
| 1088 | |
---|
| 1089 | /* |
---|
| 1090 | * _CPU_Context_save_fp |
---|
| 1091 | * |
---|
| 1092 | * This routine saves the floating point context passed to it. |
---|
| 1093 | */ |
---|
| 1094 | |
---|
| 1095 | void _CPU_Context_save_fp( |
---|
[0edd196] | 1096 | Context_Control_fp **fp_context_ptr |
---|
[7908ba5b] | 1097 | ); |
---|
| 1098 | |
---|
| 1099 | /* |
---|
| 1100 | * _CPU_Context_restore_fp |
---|
| 1101 | * |
---|
| 1102 | * This routine restores the floating point context passed to it. |
---|
| 1103 | */ |
---|
| 1104 | |
---|
| 1105 | void _CPU_Context_restore_fp( |
---|
[0edd196] | 1106 | Context_Control_fp **fp_context_ptr |
---|
[7908ba5b] | 1107 | ); |
---|
| 1108 | |
---|
| 1109 | /* The following routine swaps the endian format of an unsigned int. |
---|
| 1110 | * It must be static because it is referenced indirectly. |
---|
| 1111 | * |
---|
| 1112 | * This version will work on any processor, but if there is a better |
---|
| 1113 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
| 1114 | * |
---|
| 1115 | * swap least significant two bytes with 16-bit rotate |
---|
| 1116 | * swap upper and lower 16-bits |
---|
| 1117 | * swap most significant two bytes with 16-bit rotate |
---|
| 1118 | * |
---|
| 1119 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
| 1120 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
| 1121 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
[ece004d] | 1122 | * that interrupts would probably have to be disabled to ensure that |
---|
[7908ba5b] | 1123 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
| 1124 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
| 1125 | * endianness for ALL fetches -- both code and data -- so the code |
---|
| 1126 | * will be fetched incorrectly. |
---|
| 1127 | */ |
---|
[e2040ba] | 1128 | |
---|
[ec8973ed] | 1129 | static inline uint32_t CPU_swap_u32( |
---|
| 1130 | uint32_t value |
---|
[7908ba5b] | 1131 | ) |
---|
| 1132 | { |
---|
[c346f33d] | 1133 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
[e2040ba] | 1134 | |
---|
[7908ba5b] | 1135 | byte4 = (value >> 24) & 0xff; |
---|
| 1136 | byte3 = (value >> 16) & 0xff; |
---|
| 1137 | byte2 = (value >> 8) & 0xff; |
---|
| 1138 | byte1 = value & 0xff; |
---|
[e2040ba] | 1139 | |
---|
[7908ba5b] | 1140 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
| 1141 | return( swapped ); |
---|
| 1142 | } |
---|
| 1143 | |
---|
| 1144 | #define CPU_swap_u16( value ) \ |
---|
| 1145 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
| 1146 | |
---|
[bd1ecb0] | 1147 | |
---|
| 1148 | #endif |
---|
| 1149 | |
---|
| 1150 | |
---|
| 1151 | |
---|
[7908ba5b] | 1152 | #ifdef __cplusplus |
---|
| 1153 | } |
---|
| 1154 | #endif |
---|
| 1155 | |
---|
| 1156 | #endif |
---|