[0c0181d] | 1 | /** |
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| 2 | * @file |
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[a1f9934a] | 3 | * |
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| 4 | * @brief Mips CPU Dependent Header File |
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[bd90283] | 5 | */ |
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| 6 | |
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| 7 | /* |
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[aa7f8a1f] | 8 | * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and |
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| 9 | * Joel Sherrill <joel@OARcorp.com>. |
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[e2040ba] | 10 | * |
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[aa7f8a1f] | 11 | * These changes made the code conditional on standard cpp predefines, |
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| 12 | * merged the mips1 and mips3 code sequences as much as possible, |
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| 13 | * and moved some of the assembly code to C. Alan did much of the |
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| 14 | * initial analysis and rework. Joel took over from there and |
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| 15 | * wrote the JMR3904 BSP so this could be tested. Joel also |
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| 16 | * added the new interrupt vectoring support in libcpu and |
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| 17 | * tried to better support the various interrupt controllers. |
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[e2040ba] | 18 | * |
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[0c0181d] | 19 | */ |
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| 20 | |
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| 21 | /* |
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[aa7f8a1f] | 22 | * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> |
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[e2040ba] | 23 | * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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[aa7f8a1f] | 24 | * |
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| 25 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 26 | * without any express or implied warranty: |
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[7908ba5b] | 27 | * permission to use, copy, modify, and distribute this file |
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| 28 | * for any purpose is hereby granted without fee, provided that |
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| 29 | * the above copyright notice and this notice appears in all |
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| 30 | * copies, and that the name of Transition Networks not be used in |
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| 31 | * advertising or publicity pertaining to distribution of the |
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| 32 | * software without specific, written prior permission. |
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| 33 | * Transition Networks makes no representations about the suitability |
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| 34 | * of this software for any purpose. |
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| 35 | * |
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[0c0181d] | 36 | * COPYRIGHT (c) 1989-2012. |
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[7908ba5b] | 37 | * On-Line Applications Research Corporation (OAR). |
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| 38 | * |
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| 39 | * The license and distribution terms for this file may be |
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| 40 | * found in the file LICENSE in this distribution or at |
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[c499856] | 41 | * http://www.rtems.org/license/LICENSE. |
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[7908ba5b] | 42 | */ |
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| 43 | |
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[7f70d1b7] | 44 | #ifndef _RTEMS_SCORE_CPU_H |
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| 45 | #define _RTEMS_SCORE_CPU_H |
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[7908ba5b] | 46 | |
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[a1f9934a] | 47 | /** |
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| 48 | * @defgroup ScoreCPU CPU CPU |
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| 49 | * |
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| 50 | * @ingroup Score |
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| 51 | * |
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| 52 | */ |
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| 53 | /**@{*/ |
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| 54 | |
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[7908ba5b] | 55 | #ifdef __cplusplus |
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| 56 | extern "C" { |
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| 57 | #endif |
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| 58 | |
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[eb4536c] | 59 | #include <rtems/score/types.h> |
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[89b85e51] | 60 | #include <rtems/score/mips.h> |
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[5194a28] | 61 | |
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[7908ba5b] | 62 | /* conditional compilation parameters */ |
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| 63 | |
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| 64 | /* |
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| 65 | * Does RTEMS manage a dedicated interrupt stack in software? |
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| 66 | * |
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[fda47cd] | 67 | * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. |
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[7908ba5b] | 68 | * If FALSE, nothing is done. |
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| 69 | * |
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| 70 | * If the CPU supports a dedicated interrupt stack in hardware, |
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| 71 | * then it is generally the responsibility of the BSP to allocate it |
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| 72 | * and set it up. |
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| 73 | * |
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| 74 | * If the CPU does not support a dedicated interrupt stack, then |
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| 75 | * the porter has two options: (1) execute interrupts on the |
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| 76 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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| 77 | * interrupt stack. |
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| 78 | * |
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| 79 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 80 | * |
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| 81 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 82 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 83 | * possible that both are FALSE for a particular CPU. Although it |
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| 84 | * is unclear what that would imply about the interrupt processing |
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| 85 | * procedure on that CPU. |
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| 86 | */ |
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| 87 | |
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| 88 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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| 89 | |
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[2fd427c] | 90 | /* |
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| 91 | * Does the CPU follow the simple vectored interrupt model? |
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| 92 | * |
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| 93 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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| 94 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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| 95 | * table |
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| 96 | * |
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| 97 | * MIPS Specific Information: |
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| 98 | * |
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[3e5ff08] | 99 | * Up to and including RTEMS 4.10, the MIPS port used simple vectored |
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| 100 | * interrupts. But this was changed to the PIC model after 4.10. |
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[2fd427c] | 101 | */ |
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[0c0181d] | 102 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
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[2fd427c] | 103 | |
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[7908ba5b] | 104 | /* |
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| 105 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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| 106 | * |
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| 107 | * If TRUE, then it must be installed during initialization. |
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| 108 | * If FALSE, then no installation is performed. |
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| 109 | * |
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| 110 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 111 | * |
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| 112 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 113 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 114 | * possible that both are FALSE for a particular CPU. Although it |
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| 115 | * is unclear what that would imply about the interrupt processing |
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| 116 | * procedure on that CPU. |
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| 117 | */ |
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| 118 | |
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| 119 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 120 | |
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| 121 | /* |
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| 122 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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| 123 | * |
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| 124 | * If TRUE, then the memory is allocated during initialization. |
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| 125 | * If FALSE, then the memory is allocated during initialization. |
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| 126 | * |
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[ece004d] | 127 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. |
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[7908ba5b] | 128 | */ |
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| 129 | |
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| 130 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
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| 131 | |
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| 132 | /* |
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| 133 | * Does the RTEMS invoke the user's ISR with the vector number and |
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[e2040ba] | 134 | * a pointer to the saved interrupt frame (1) or just the vector |
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[7908ba5b] | 135 | * number (0)? |
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[e2040ba] | 136 | * |
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[7908ba5b] | 137 | */ |
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| 138 | |
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[141e16d] | 139 | #define CPU_ISR_PASSES_FRAME_POINTER TRUE |
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[e2040ba] | 140 | |
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| 141 | |
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[7908ba5b] | 142 | |
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| 143 | /* |
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| 144 | * Does the CPU have hardware floating point? |
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| 145 | * |
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| 146 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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| 147 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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| 148 | * |
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| 149 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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| 150 | * the answer is TRUE. |
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| 151 | * |
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[fda47cd] | 152 | * The macro name "MIPS_HAS_FPU" should be made CPU specific. |
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[7908ba5b] | 153 | * It indicates whether or not this CPU model has FP support. For |
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| 154 | * example, it would be possible to have an i386_nofp CPU model |
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| 155 | * which set this to false to indicate that you have an i386 without |
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| 156 | * an i387 and wish to leave floating point support out of RTEMS. |
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| 157 | */ |
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| 158 | |
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[fda47cd] | 159 | #if ( MIPS_HAS_FPU == 1 ) |
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[7908ba5b] | 160 | #define CPU_HARDWARE_FP TRUE |
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| 161 | #else |
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| 162 | #define CPU_HARDWARE_FP FALSE |
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| 163 | #endif |
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| 164 | |
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| 165 | /* |
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| 166 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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| 167 | * |
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| 168 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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| 169 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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| 170 | * |
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[5194a28] | 171 | * So far, the only CPU in which this option has been used is the |
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| 172 | * HP PA-RISC. The HP C compiler and gcc both implicitly use the |
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| 173 | * floating point registers to perform integer multiplies. If |
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| 174 | * a function which you would not think utilize the FP unit DOES, |
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| 175 | * then one can not easily predict which tasks will use the FP hardware. |
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| 176 | * In this case, this option should be TRUE. |
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| 177 | * |
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[7908ba5b] | 178 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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[0c0181d] | 179 | * |
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| 180 | * Mips Note: It appears the GCC can implicitly generate FPU |
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| 181 | * and Altivec instructions when you least expect them. So make |
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| 182 | * all tasks floating point. |
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[7908ba5b] | 183 | */ |
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| 184 | |
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[a1f9934a] | 185 | #define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP |
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[7908ba5b] | 186 | |
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| 187 | /* |
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| 188 | * Should the IDLE task have a floating point context? |
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| 189 | * |
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| 190 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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| 191 | * and it has a floating point context which is switched in and out. |
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| 192 | * If FALSE, then the IDLE task does not have a floating point context. |
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| 193 | * |
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| 194 | * Setting this to TRUE negatively impacts the time required to preempt |
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| 195 | * the IDLE task from an interrupt because the floating point context |
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| 196 | * must be saved as part of the preemption. |
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| 197 | */ |
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| 198 | |
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[0bc5329] | 199 | #define CPU_IDLE_TASK_IS_FP FALSE |
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[7908ba5b] | 200 | |
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| 201 | /* |
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| 202 | * Should the saving of the floating point registers be deferred |
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| 203 | * until a context switch is made to another different floating point |
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| 204 | * task? |
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| 205 | * |
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| 206 | * If TRUE, then the floating point context will not be stored until |
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| 207 | * necessary. It will remain in the floating point registers and not |
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| 208 | * disturned until another floating point task is switched to. |
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| 209 | * |
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| 210 | * If FALSE, then the floating point context is saved when a floating |
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| 211 | * point task is switched out and restored when the next floating point |
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| 212 | * task is restored. The state of the floating point registers between |
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| 213 | * those two operations is not specified. |
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| 214 | * |
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| 215 | * If the floating point context does NOT have to be saved as part of |
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| 216 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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| 217 | * |
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| 218 | * Setting this flag to TRUE results in using a different algorithm |
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| 219 | * for deciding when to save and restore the floating point context. |
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| 220 | * The deferred FP switch algorithm minimizes the number of times |
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| 221 | * the FP context is saved and restored. The FP context is not saved |
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| 222 | * until a context switch is made to another, different FP task. |
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| 223 | * Thus in a system with only one FP task, the FP context will never |
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| 224 | * be saved or restored. |
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| 225 | */ |
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| 226 | |
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| 227 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 228 | |
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[84e6f15] | 229 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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| 230 | |
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[7908ba5b] | 231 | /* |
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| 232 | * Does this port provide a CPU dependent IDLE task implementation? |
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| 233 | * |
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| 234 | * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body |
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| 235 | * must be provided and is the default IDLE thread body instead of |
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| 236 | * _Internal_threads_Idle_thread_body. |
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| 237 | * |
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| 238 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 239 | * not provide one. |
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| 240 | * |
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| 241 | * This is intended to allow for supporting processors which have |
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| 242 | * a low power or idle mode. When the IDLE thread is executed, then |
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| 243 | * the CPU can be powered down. |
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| 244 | * |
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| 245 | * The order of precedence for selecting the IDLE thread body is: |
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| 246 | * |
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| 247 | * 1. BSP provided |
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| 248 | * 2. CPU dependent (if provided) |
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| 249 | * 3. generic (if no BSP and no CPU dependent) |
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| 250 | */ |
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| 251 | |
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| 252 | /* we can use the low power wait instruction for the IDLE thread */ |
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[e2040ba] | 253 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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[7908ba5b] | 254 | |
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| 255 | /* |
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| 256 | * Does the stack grow up (toward higher addresses) or down |
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| 257 | * (toward lower addresses)? |
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| 258 | * |
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| 259 | * If TRUE, then the grows upward. |
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| 260 | * If FALSE, then the grows toward smaller addresses. |
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| 261 | */ |
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| 262 | |
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| 263 | /* our stack grows down */ |
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| 264 | #define CPU_STACK_GROWS_UP FALSE |
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| 265 | |
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[a8865f8] | 266 | /* FIXME: Is this the right value? */ |
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| 267 | #define CPU_CACHE_LINE_BYTES 16 |
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[7908ba5b] | 268 | |
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[a8865f8] | 269 | #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
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[7908ba5b] | 270 | |
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| 271 | /* |
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| 272 | * The following defines the number of bits actually used in the |
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| 273 | * interrupt field of the task mode. How those bits map to the |
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| 274 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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| 275 | */ |
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| 276 | |
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[bd1ecb0] | 277 | #define CPU_MODES_INTERRUPT_MASK 0x000000ff |
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[7908ba5b] | 278 | |
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[f1738ed] | 279 | #define CPU_SIZEOF_POINTER 4 |
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| 280 | |
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[decff899] | 281 | #define CPU_MAXIMUM_PROCESSORS 32 |
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| 282 | |
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[7908ba5b] | 283 | /* |
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[5194a28] | 284 | * Processor defined structures |
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| 285 | * |
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| 286 | * Examples structures include the descriptor tables from the i386 |
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| 287 | * and the processor control structure on the i960ca. |
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[7908ba5b] | 288 | */ |
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| 289 | |
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| 290 | /* may need to put some structures here. */ |
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| 291 | |
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| 292 | /* |
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| 293 | * Contexts |
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| 294 | * |
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| 295 | * Generally there are 2 types of context to save. |
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| 296 | * 1. Interrupt registers to save |
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| 297 | * 2. Task level registers to save |
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| 298 | * |
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| 299 | * This means we have the following 3 context items: |
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| 300 | * 1. task level context stuff:: Context_Control |
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| 301 | * 2. floating point task stuff:: Context_Control_fp |
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| 302 | * 3. special interrupt level context :: Context_Control_interrupt |
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| 303 | * |
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| 304 | * On some processors, it is cost-effective to save only the callee |
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| 305 | * preserved registers during a task context switch. This means |
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| 306 | * that the ISR code needs to save those registers which do not |
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| 307 | * persist across function calls. It is not mandatory to make this |
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| 308 | * distinctions between the caller/callee saves registers for the |
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| 309 | * purpose of minimizing context saved during task switch and on interrupts. |
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| 310 | * If the cost of saving extra registers is minimal, simplicity is the |
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| 311 | * choice. Save the same context on interrupt entry as for tasks in |
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| 312 | * this case. |
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| 313 | * |
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| 314 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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| 315 | * care should be used in designing the context area. |
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| 316 | * |
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| 317 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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| 318 | * structure will not be used or it simply consist of an array of a |
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| 319 | * fixed number of bytes. This is done when the floating point context |
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| 320 | * is dumped by a "FP save context" type instruction and the format |
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| 321 | * is not really defined by the CPU. In this case, there is no need |
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| 322 | * to figure out the exact format -- only the size. Of course, although |
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| 323 | * this is enough information for RTEMS, it is probably not enough for |
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| 324 | * a debugger such as gdb. But that is another problem. |
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| 325 | */ |
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| 326 | |
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[9787ee22] | 327 | #ifndef ASM |
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[bd1ecb0] | 328 | |
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[7908ba5b] | 329 | /* WARNING: If this structure is modified, the constants in cpu.h must be updated. */ |
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[5194a28] | 330 | #if (__mips == 1) || (__mips == 32) |
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[5bb38e15] | 331 | #define __MIPS_REGISTER_TYPE uint32_t |
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| 332 | #define __MIPS_FPU_REGISTER_TYPE uint32_t |
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[2e549dad] | 333 | #elif __mips == 3 |
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[5bb38e15] | 334 | #define __MIPS_REGISTER_TYPE uint64_t |
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| 335 | #define __MIPS_FPU_REGISTER_TYPE uint64_t |
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[5d7bfce3] | 336 | #else |
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[2e549dad] | 337 | #error "mips register size: unknown architecture level!!" |
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[5d7bfce3] | 338 | #endif |
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[2e549dad] | 339 | typedef struct { |
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| 340 | __MIPS_REGISTER_TYPE s0; |
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| 341 | __MIPS_REGISTER_TYPE s1; |
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| 342 | __MIPS_REGISTER_TYPE s2; |
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| 343 | __MIPS_REGISTER_TYPE s3; |
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| 344 | __MIPS_REGISTER_TYPE s4; |
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| 345 | __MIPS_REGISTER_TYPE s5; |
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| 346 | __MIPS_REGISTER_TYPE s6; |
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| 347 | __MIPS_REGISTER_TYPE s7; |
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| 348 | __MIPS_REGISTER_TYPE sp; |
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| 349 | __MIPS_REGISTER_TYPE fp; |
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| 350 | __MIPS_REGISTER_TYPE ra; |
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| 351 | __MIPS_REGISTER_TYPE c0_sr; |
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[8264d23] | 352 | __MIPS_REGISTER_TYPE c0_epc; |
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[7908ba5b] | 353 | } Context_Control; |
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| 354 | |
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[0ca6d0d9] | 355 | #define _CPU_Context_Get_SP( _context ) \ |
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[a0cb87c] | 356 | (uintptr_t) (_context)->sp |
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[0ca6d0d9] | 357 | |
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[2e549dad] | 358 | /* WARNING: If this structure is modified, the constants in cpu.h |
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| 359 | * must also be updated. |
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| 360 | */ |
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| 361 | |
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[7908ba5b] | 362 | typedef struct { |
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[2e549dad] | 363 | #if ( CPU_HARDWARE_FP == TRUE ) |
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| 364 | __MIPS_FPU_REGISTER_TYPE fp0; |
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| 365 | __MIPS_FPU_REGISTER_TYPE fp1; |
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| 366 | __MIPS_FPU_REGISTER_TYPE fp2; |
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| 367 | __MIPS_FPU_REGISTER_TYPE fp3; |
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| 368 | __MIPS_FPU_REGISTER_TYPE fp4; |
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| 369 | __MIPS_FPU_REGISTER_TYPE fp5; |
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| 370 | __MIPS_FPU_REGISTER_TYPE fp6; |
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| 371 | __MIPS_FPU_REGISTER_TYPE fp7; |
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| 372 | __MIPS_FPU_REGISTER_TYPE fp8; |
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| 373 | __MIPS_FPU_REGISTER_TYPE fp9; |
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| 374 | __MIPS_FPU_REGISTER_TYPE fp10; |
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| 375 | __MIPS_FPU_REGISTER_TYPE fp11; |
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| 376 | __MIPS_FPU_REGISTER_TYPE fp12; |
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| 377 | __MIPS_FPU_REGISTER_TYPE fp13; |
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| 378 | __MIPS_FPU_REGISTER_TYPE fp14; |
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| 379 | __MIPS_FPU_REGISTER_TYPE fp15; |
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| 380 | __MIPS_FPU_REGISTER_TYPE fp16; |
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| 381 | __MIPS_FPU_REGISTER_TYPE fp17; |
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| 382 | __MIPS_FPU_REGISTER_TYPE fp18; |
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| 383 | __MIPS_FPU_REGISTER_TYPE fp19; |
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| 384 | __MIPS_FPU_REGISTER_TYPE fp20; |
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| 385 | __MIPS_FPU_REGISTER_TYPE fp21; |
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| 386 | __MIPS_FPU_REGISTER_TYPE fp22; |
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| 387 | __MIPS_FPU_REGISTER_TYPE fp23; |
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| 388 | __MIPS_FPU_REGISTER_TYPE fp24; |
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| 389 | __MIPS_FPU_REGISTER_TYPE fp25; |
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| 390 | __MIPS_FPU_REGISTER_TYPE fp26; |
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| 391 | __MIPS_FPU_REGISTER_TYPE fp27; |
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| 392 | __MIPS_FPU_REGISTER_TYPE fp28; |
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| 393 | __MIPS_FPU_REGISTER_TYPE fp29; |
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| 394 | __MIPS_FPU_REGISTER_TYPE fp30; |
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| 395 | __MIPS_FPU_REGISTER_TYPE fp31; |
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[7c99007] | 396 | uint32_t fpcs; |
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[2e549dad] | 397 | #endif |
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[7908ba5b] | 398 | } Context_Control_fp; |
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| 399 | |
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[e2040ba] | 400 | /* |
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[a37b8f95] | 401 | * This struct reflects the stack frame employed in ISR_Handler. Note |
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| 402 | * that the ISR routine save some of the registers to this frame for |
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| 403 | * all interrupts and exceptions. Other registers are saved only on |
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[5bb38e15] | 404 | * exceptions, while others are not touched at all. The untouched |
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| 405 | * registers are not normally disturbed by high-level language |
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[a37b8f95] | 406 | * programs so they can be accessed when required. |
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| 407 | * |
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| 408 | * The registers and their ordering in this struct must directly |
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| 409 | * correspond to the layout and ordering of * shown in iregdef.h, |
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[5bb38e15] | 410 | * as cpu_asm.S uses those definitions to fill the stack frame. |
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[a37b8f95] | 411 | * This struct provides access to the stack frame for C code. |
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| 412 | * |
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| 413 | * Similarly, this structure is used by debugger stubs and exception |
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| 414 | * processing routines so be careful when changing the format. |
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| 415 | * |
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[9099a85] | 416 | * NOTE: The comments with this structure and cpu_asm.S should be kept |
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[a37b8f95] | 417 | * in sync. When in doubt, look in the code to see if the |
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| 418 | * registers you're interested in are actually treated as expected. |
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[9099a85] | 419 | * The order of the first portion of this structure follows the |
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| 420 | * order of registers expected by gdb. |
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[a37b8f95] | 421 | */ |
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[e2040ba] | 422 | |
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| 423 | typedef struct |
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| 424 | { |
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[9099a85] | 425 | __MIPS_REGISTER_TYPE r0; /* 0 -- NOT FILLED IN */ |
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| 426 | __MIPS_REGISTER_TYPE at; /* 1 -- saved always */ |
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| 427 | __MIPS_REGISTER_TYPE v0; /* 2 -- saved always */ |
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| 428 | __MIPS_REGISTER_TYPE v1; /* 3 -- saved always */ |
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| 429 | __MIPS_REGISTER_TYPE a0; /* 4 -- saved always */ |
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| 430 | __MIPS_REGISTER_TYPE a1; /* 5 -- saved always */ |
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| 431 | __MIPS_REGISTER_TYPE a2; /* 6 -- saved always */ |
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| 432 | __MIPS_REGISTER_TYPE a3; /* 7 -- saved always */ |
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| 433 | __MIPS_REGISTER_TYPE t0; /* 8 -- saved always */ |
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| 434 | __MIPS_REGISTER_TYPE t1; /* 9 -- saved always */ |
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| 435 | __MIPS_REGISTER_TYPE t2; /* 10 -- saved always */ |
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| 436 | __MIPS_REGISTER_TYPE t3; /* 11 -- saved always */ |
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| 437 | __MIPS_REGISTER_TYPE t4; /* 12 -- saved always */ |
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| 438 | __MIPS_REGISTER_TYPE t5; /* 13 -- saved always */ |
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| 439 | __MIPS_REGISTER_TYPE t6; /* 14 -- saved always */ |
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| 440 | __MIPS_REGISTER_TYPE t7; /* 15 -- saved always */ |
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| 441 | __MIPS_REGISTER_TYPE s0; /* 16 -- saved on exceptions */ |
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| 442 | __MIPS_REGISTER_TYPE s1; /* 17 -- saved on exceptions */ |
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| 443 | __MIPS_REGISTER_TYPE s2; /* 18 -- saved on exceptions */ |
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| 444 | __MIPS_REGISTER_TYPE s3; /* 19 -- saved on exceptions */ |
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| 445 | __MIPS_REGISTER_TYPE s4; /* 20 -- saved on exceptions */ |
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| 446 | __MIPS_REGISTER_TYPE s5; /* 21 -- saved on exceptions */ |
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| 447 | __MIPS_REGISTER_TYPE s6; /* 22 -- saved on exceptions */ |
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| 448 | __MIPS_REGISTER_TYPE s7; /* 23 -- saved on exceptions */ |
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| 449 | __MIPS_REGISTER_TYPE t8; /* 24 -- saved always */ |
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| 450 | __MIPS_REGISTER_TYPE t9; /* 25 -- saved always */ |
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| 451 | __MIPS_REGISTER_TYPE k0; /* 26 -- NOT FILLED IN, kernel tmp reg */ |
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| 452 | __MIPS_REGISTER_TYPE k1; /* 27 -- NOT FILLED IN, kernel tmp reg */ |
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| 453 | __MIPS_REGISTER_TYPE gp; /* 28 -- saved always */ |
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| 454 | __MIPS_REGISTER_TYPE sp; /* 29 -- saved on exceptions NOT RESTORED */ |
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| 455 | __MIPS_REGISTER_TYPE fp; /* 30 -- saved always */ |
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| 456 | __MIPS_REGISTER_TYPE ra; /* 31 -- saved always */ |
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| 457 | __MIPS_REGISTER_TYPE c0_sr; /* 32 -- saved always, some bits are */ |
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[a37b8f95] | 458 | /* manipulated per-thread */ |
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[9099a85] | 459 | __MIPS_REGISTER_TYPE mdlo; /* 33 -- saved always */ |
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| 460 | __MIPS_REGISTER_TYPE mdhi; /* 34 -- saved always */ |
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| 461 | __MIPS_REGISTER_TYPE badvaddr; /* 35 -- saved on exceptions, read-only */ |
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| 462 | __MIPS_REGISTER_TYPE cause; /* 36 -- saved on exceptions NOT restored */ |
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| 463 | __MIPS_REGISTER_TYPE epc; /* 37 -- saved always, read-only register */ |
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| 464 | /* but logically restored */ |
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| 465 | __MIPS_FPU_REGISTER_TYPE f0; /* 38 -- saved if FP enabled */ |
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| 466 | __MIPS_FPU_REGISTER_TYPE f1; /* 39 -- saved if FP enabled */ |
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| 467 | __MIPS_FPU_REGISTER_TYPE f2; /* 40 -- saved if FP enabled */ |
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| 468 | __MIPS_FPU_REGISTER_TYPE f3; /* 41 -- saved if FP enabled */ |
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| 469 | __MIPS_FPU_REGISTER_TYPE f4; /* 42 -- saved if FP enabled */ |
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| 470 | __MIPS_FPU_REGISTER_TYPE f5; /* 43 -- saved if FP enabled */ |
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| 471 | __MIPS_FPU_REGISTER_TYPE f6; /* 44 -- saved if FP enabled */ |
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| 472 | __MIPS_FPU_REGISTER_TYPE f7; /* 45 -- saved if FP enabled */ |
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| 473 | __MIPS_FPU_REGISTER_TYPE f8; /* 46 -- saved if FP enabled */ |
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| 474 | __MIPS_FPU_REGISTER_TYPE f9; /* 47 -- saved if FP enabled */ |
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| 475 | __MIPS_FPU_REGISTER_TYPE f10; /* 48 -- saved if FP enabled */ |
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| 476 | __MIPS_FPU_REGISTER_TYPE f11; /* 49 -- saved if FP enabled */ |
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| 477 | __MIPS_FPU_REGISTER_TYPE f12; /* 50 -- saved if FP enabled */ |
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| 478 | __MIPS_FPU_REGISTER_TYPE f13; /* 51 -- saved if FP enabled */ |
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| 479 | __MIPS_FPU_REGISTER_TYPE f14; /* 52 -- saved if FP enabled */ |
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| 480 | __MIPS_FPU_REGISTER_TYPE f15; /* 53 -- saved if FP enabled */ |
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| 481 | __MIPS_FPU_REGISTER_TYPE f16; /* 54 -- saved if FP enabled */ |
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| 482 | __MIPS_FPU_REGISTER_TYPE f17; /* 55 -- saved if FP enabled */ |
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| 483 | __MIPS_FPU_REGISTER_TYPE f18; /* 56 -- saved if FP enabled */ |
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| 484 | __MIPS_FPU_REGISTER_TYPE f19; /* 57 -- saved if FP enabled */ |
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| 485 | __MIPS_FPU_REGISTER_TYPE f20; /* 58 -- saved if FP enabled */ |
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| 486 | __MIPS_FPU_REGISTER_TYPE f21; /* 59 -- saved if FP enabled */ |
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| 487 | __MIPS_FPU_REGISTER_TYPE f22; /* 60 -- saved if FP enabled */ |
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| 488 | __MIPS_FPU_REGISTER_TYPE f23; /* 61 -- saved if FP enabled */ |
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| 489 | __MIPS_FPU_REGISTER_TYPE f24; /* 62 -- saved if FP enabled */ |
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| 490 | __MIPS_FPU_REGISTER_TYPE f25; /* 63 -- saved if FP enabled */ |
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| 491 | __MIPS_FPU_REGISTER_TYPE f26; /* 64 -- saved if FP enabled */ |
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| 492 | __MIPS_FPU_REGISTER_TYPE f27; /* 65 -- saved if FP enabled */ |
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| 493 | __MIPS_FPU_REGISTER_TYPE f28; /* 66 -- saved if FP enabled */ |
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| 494 | __MIPS_FPU_REGISTER_TYPE f29; /* 67 -- saved if FP enabled */ |
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| 495 | __MIPS_FPU_REGISTER_TYPE f30; /* 68 -- saved if FP enabled */ |
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| 496 | __MIPS_FPU_REGISTER_TYPE f31; /* 69 -- saved if FP enabled */ |
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| 497 | __MIPS_REGISTER_TYPE fcsr; /* 70 -- saved on exceptions */ |
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| 498 | /* (oddly not documented on MGV) */ |
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| 499 | __MIPS_REGISTER_TYPE feir; /* 71 -- saved on exceptions */ |
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| 500 | /* (oddly not documented on MGV) */ |
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[a37b8f95] | 501 | |
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[9099a85] | 502 | /* GDB does not seem to care about anything past this point */ |
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| 503 | |
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| 504 | __MIPS_REGISTER_TYPE tlbhi; /* 72 - NOT FILLED IN, doesn't exist on */ |
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[a37b8f95] | 505 | /* all MIPS CPUs (at least MGV) */ |
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[e2040ba] | 506 | #if __mips == 1 |
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[9099a85] | 507 | __MIPS_REGISTER_TYPE tlblo; /* 73 - NOT FILLED IN, doesn't exist on */ |
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[a37b8f95] | 508 | /* all MIPS CPUs (at least MGV) */ |
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[e2040ba] | 509 | #endif |
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[5194a28] | 510 | #if (__mips == 3) || (__mips == 32) |
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[9099a85] | 511 | __MIPS_REGISTER_TYPE tlblo0; /* 73 - NOT FILLED IN, doesn't exist on */ |
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[a37b8f95] | 512 | /* all MIPS CPUs (at least MGV) */ |
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[e2040ba] | 513 | #endif |
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[a37b8f95] | 514 | |
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[9099a85] | 515 | __MIPS_REGISTER_TYPE inx; /* 74 -- NOT FILLED IN, doesn't exist on */ |
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[a37b8f95] | 516 | /* all MIPS CPUs (at least MGV) */ |
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[9099a85] | 517 | __MIPS_REGISTER_TYPE rand; /* 75 -- NOT FILLED IN, doesn't exist on */ |
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[a37b8f95] | 518 | /* all MIPS CPUs (at least MGV) */ |
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[9099a85] | 519 | __MIPS_REGISTER_TYPE ctxt; /* 76 -- NOT FILLED IN, doesn't exist on */ |
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[a37b8f95] | 520 | /* all MIPS CPUs (at least MGV) */ |
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[9099a85] | 521 | __MIPS_REGISTER_TYPE exctype; /* 77 -- NOT FILLED IN (not enough info) */ |
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| 522 | __MIPS_REGISTER_TYPE mode; /* 78 -- NOT FILLED IN (not enough info) */ |
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| 523 | __MIPS_REGISTER_TYPE prid; /* 79 -- NOT FILLED IN (not need to do so) */ |
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[293c0e30] | 524 | __MIPS_REGISTER_TYPE tar ; /* 80 -- target address register, filled on exceptions */ |
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| 525 | /* end of __mips == 1 so NREGS == 81 */ |
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[5194a28] | 526 | #if (__mips == 3) || (__mips == 32) |
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[293c0e30] | 527 | __MIPS_REGISTER_TYPE tlblo1; /* 81 -- NOT FILLED IN */ |
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| 528 | __MIPS_REGISTER_TYPE pagemask; /* 82 -- NOT FILLED IN */ |
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| 529 | __MIPS_REGISTER_TYPE wired; /* 83 -- NOT FILLED IN */ |
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| 530 | __MIPS_REGISTER_TYPE count; /* 84 -- NOT FILLED IN */ |
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| 531 | __MIPS_REGISTER_TYPE compare; /* 85 -- NOT FILLED IN */ |
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| 532 | __MIPS_REGISTER_TYPE config; /* 86 -- NOT FILLED IN */ |
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| 533 | __MIPS_REGISTER_TYPE lladdr; /* 87 -- NOT FILLED IN */ |
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| 534 | __MIPS_REGISTER_TYPE watchlo; /* 88 -- NOT FILLED IN */ |
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| 535 | __MIPS_REGISTER_TYPE watchhi; /* 89 -- NOT FILLED IN */ |
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| 536 | __MIPS_REGISTER_TYPE ecc; /* 90 -- NOT FILLED IN */ |
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| 537 | __MIPS_REGISTER_TYPE cacheerr; /* 91 -- NOT FILLED IN */ |
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| 538 | __MIPS_REGISTER_TYPE taglo; /* 92 -- NOT FILLED IN */ |
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| 539 | __MIPS_REGISTER_TYPE taghi; /* 93 -- NOT FILLED IN */ |
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| 540 | __MIPS_REGISTER_TYPE errpc; /* 94 -- NOT FILLED IN */ |
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| 541 | __MIPS_REGISTER_TYPE xctxt; /* 95 -- NOT FILLED IN */ |
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| 542 | /* end of __mips == 3 so NREGS == 96 */ |
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[a37b8f95] | 543 | #endif |
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| 544 | |
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[7908ba5b] | 545 | } CPU_Interrupt_frame; |
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| 546 | |
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[815994f] | 547 | typedef CPU_Interrupt_frame CPU_Exception_frame; |
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| 548 | |
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[7908ba5b] | 549 | /* |
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| 550 | * This variable is optional. It is used on CPUs on which it is difficult |
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| 551 | * to generate an "uninitialized" FP context. It is filled in by |
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| 552 | * _CPU_Initialize and copied into the task's FP context area during |
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| 553 | * _CPU_Context_Initialize. |
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| 554 | */ |
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| 555 | |
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[d638aca] | 556 | extern Context_Control_fp _CPU_Null_fp_context; |
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[7908ba5b] | 557 | |
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| 558 | /* |
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| 559 | * Nothing prevents the porter from declaring more CPU specific variables. |
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| 560 | */ |
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| 561 | |
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| 562 | /* XXX: if needed, put more variables here */ |
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| 563 | |
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| 564 | /* |
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| 565 | * The size of the floating point context area. On some CPUs this |
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| 566 | * will not be a "sizeof" because the format of the floating point |
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| 567 | * area is not defined -- only the size is. This is usually on |
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| 568 | * CPUs with a "floating point save context" instruction. |
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| 569 | */ |
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| 570 | |
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| 571 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 572 | |
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| 573 | /* |
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| 574 | * Amount of extra stack (above minimum stack size) required by |
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| 575 | * system initialization thread. Remember that in a multiprocessor |
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| 576 | * system the system intialization thread becomes the MP server thread. |
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| 577 | */ |
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| 578 | |
---|
| 579 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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| 580 | |
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| 581 | /* |
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[ece004d] | 582 | * Should be large enough to run all RTEMS tests. This ensures |
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[7908ba5b] | 583 | * that a "reasonable" small application should not have any problems. |
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| 584 | */ |
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| 585 | |
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[5a5bfea5] | 586 | #define CPU_STACK_MINIMUM_SIZE (8 * 1024) |
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[7908ba5b] | 587 | |
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| 588 | /* |
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| 589 | * CPU's worst alignment requirement for data types on a byte boundary. This |
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| 590 | * alignment does not take into account the requirements for the stack. |
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| 591 | */ |
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| 592 | |
---|
| 593 | #define CPU_ALIGNMENT 8 |
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| 594 | |
---|
| 595 | /* |
---|
| 596 | * This number corresponds to the byte alignment requirement for the |
---|
| 597 | * heap handler. This alignment requirement may be stricter than that |
---|
| 598 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
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| 599 | * common for the heap to follow the same alignment requirement as |
---|
| 600 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
| 601 | * then this should be set to CPU_ALIGNMENT. |
---|
| 602 | * |
---|
| 603 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 604 | * be greater or equal to than CPU_ALIGNMENT. |
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| 605 | */ |
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| 606 | |
---|
| 607 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 608 | |
---|
| 609 | /* |
---|
| 610 | * This number corresponds to the byte alignment requirement for memory |
---|
| 611 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 612 | * may be stricter than that for the data types alignment specified by |
---|
| 613 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 614 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
| 615 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
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| 616 | * |
---|
| 617 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 618 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 619 | */ |
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| 620 | |
---|
| 621 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
| 622 | |
---|
| 623 | /* |
---|
| 624 | * This number corresponds to the byte alignment requirement for the |
---|
| 625 | * stack. This alignment requirement may be stricter than that for the |
---|
| 626 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
| 627 | * is strict enough for the stack, then this should be set to 0. |
---|
| 628 | * |
---|
| 629 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
| 630 | */ |
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| 631 | |
---|
| 632 | #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT |
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| 633 | |
---|
[815994f] | 634 | void mips_vector_exceptions( CPU_Interrupt_frame *frame ); |
---|
| 635 | |
---|
[9fd4f5c5] | 636 | /* |
---|
| 637 | * ISR handler macros |
---|
| 638 | */ |
---|
| 639 | |
---|
[7c99007] | 640 | /* |
---|
| 641 | * Declare the function that is present in the shared libcpu directory, |
---|
| 642 | * that returns the processor dependent interrupt mask. |
---|
| 643 | */ |
---|
| 644 | |
---|
| 645 | uint32_t mips_interrupt_mask( void ); |
---|
| 646 | |
---|
[7908ba5b] | 647 | /* |
---|
| 648 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
| 649 | * level is returned in _level. |
---|
| 650 | */ |
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| 651 | |
---|
[32f415d] | 652 | #define _CPU_ISR_Disable( _level ) \ |
---|
| 653 | do { \ |
---|
[293c0e30] | 654 | unsigned int _scratch; \ |
---|
| 655 | mips_get_sr( _scratch ); \ |
---|
| 656 | mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \ |
---|
| 657 | _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \ |
---|
[32f415d] | 658 | } while(0) |
---|
[7908ba5b] | 659 | |
---|
| 660 | /* |
---|
| 661 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
| 662 | * This indicates the end of an RTEMS critical section. The parameter |
---|
| 663 | * _level is not modified. |
---|
| 664 | */ |
---|
| 665 | |
---|
| 666 | #define _CPU_ISR_Enable( _level ) \ |
---|
[32f415d] | 667 | do { \ |
---|
[e6dec71c] | 668 | unsigned int _scratch; \ |
---|
| 669 | mips_get_sr( _scratch ); \ |
---|
| 670 | mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \ |
---|
[32f415d] | 671 | } while(0) |
---|
[7908ba5b] | 672 | |
---|
| 673 | /* |
---|
| 674 | * This temporarily restores the interrupt to _level before immediately |
---|
| 675 | * disabling them again. This is used to divide long RTEMS critical |
---|
| 676 | * sections into two or more parts. The parameter _level is not |
---|
[e6dec71c] | 677 | * modified. |
---|
[7908ba5b] | 678 | */ |
---|
| 679 | |
---|
| 680 | #define _CPU_ISR_Flash( _xlevel ) \ |
---|
[32f415d] | 681 | do { \ |
---|
[293c0e30] | 682 | unsigned int _scratch2 = _xlevel; \ |
---|
| 683 | _CPU_ISR_Enable( _scratch2 ); \ |
---|
| 684 | _CPU_ISR_Disable( _scratch2 ); \ |
---|
| 685 | _xlevel = _scratch2; \ |
---|
[32f415d] | 686 | } while(0) |
---|
[7908ba5b] | 687 | |
---|
[408609f6] | 688 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
---|
| 689 | { |
---|
| 690 | return ( level & SR_INTERRUPT_ENABLE_BITS ) != 0; |
---|
| 691 | } |
---|
| 692 | |
---|
[7908ba5b] | 693 | /* |
---|
| 694 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
| 695 | * actually provides. Currently, interrupt levels which do not |
---|
| 696 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
| 697 | * it would be nice if these were "mapped" by the application |
---|
| 698 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
| 699 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
| 700 | * This could be used to manage a programmable interrupt controller |
---|
| 701 | * via the rtems_task_mode directive. |
---|
[32f415d] | 702 | * |
---|
[e2040ba] | 703 | * On the MIPS, 0 is all on. Non-zero is all off. This only |
---|
[32f415d] | 704 | * manipulates the IEC. |
---|
[7908ba5b] | 705 | */ |
---|
[32f415d] | 706 | |
---|
[c346f33d] | 707 | uint32_t _CPU_ISR_Get_level( void ); /* in cpu.c */ |
---|
[2e549dad] | 708 | |
---|
[c346f33d] | 709 | void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */ |
---|
[7908ba5b] | 710 | |
---|
| 711 | /* end of ISR handler macros */ |
---|
| 712 | |
---|
| 713 | /* Context handler macros */ |
---|
| 714 | |
---|
| 715 | /* |
---|
| 716 | * Initialize the context to a state suitable for starting a |
---|
| 717 | * task after a context restore operation. Generally, this |
---|
| 718 | * involves: |
---|
| 719 | * |
---|
| 720 | * - setting a starting address |
---|
| 721 | * - preparing the stack |
---|
| 722 | * - preparing the stack and frame pointers |
---|
| 723 | * - setting the proper interrupt level in the context |
---|
| 724 | * - initializing the floating point context |
---|
| 725 | * |
---|
| 726 | * This routine generally does not set any unnecessary register |
---|
| 727 | * in the context. The state of the "general data" registers is |
---|
| 728 | * undefined at task start time. |
---|
| 729 | * |
---|
| 730 | * NOTE: This is_fp parameter is TRUE if the thread is to be a floating |
---|
| 731 | * point thread. This is typically only used on CPUs where the |
---|
| 732 | * FPU may be easily disabled by software such as on the SPARC |
---|
| 733 | * where the PSR contains an enable FPU bit. |
---|
[e6dec71c] | 734 | * |
---|
| 735 | * The per-thread status register holds the interrupt enable, FP enable |
---|
| 736 | * and global interrupt enable for that thread. It means each thread can |
---|
| 737 | * enable its own set of interrupts. If interrupts are disabled, RTEMS |
---|
[5bb38e15] | 738 | * can still dispatch via blocking calls. This is the function of the |
---|
| 739 | * "Interrupt Level", and on the MIPS, it controls the IEC bit and all |
---|
[e6dec71c] | 740 | * the hardware interrupts as defined in the SR. Software ints |
---|
[5bb38e15] | 741 | * are automatically enabled for all threads, as they will only occur under |
---|
| 742 | * program control anyhow. Besides, the interrupt level parm is only 8 bits, |
---|
[e6dec71c] | 743 | * and controlling the software ints plus the others would require 9. |
---|
| 744 | * |
---|
[5bb38e15] | 745 | * If the Interrupt Level is 0, all ints are on. Otherwise, the |
---|
| 746 | * Interrupt Level should supply a bit pattern to impose on the SR |
---|
[e6dec71c] | 747 | * interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6 |
---|
[5bb38e15] | 748 | * apply to the SR register Intr bits from bit 10 thru bit 15. Bit 7 of |
---|
[e6dec71c] | 749 | * the Interrupt Level parameter is unused at this time. |
---|
| 750 | * |
---|
| 751 | * These are the only per-thread SR bits, the others are maintained |
---|
| 752 | * globally & explicitly preserved by the Context Switch code in cpu_asm.s |
---|
[7908ba5b] | 753 | */ |
---|
| 754 | |
---|
[e6dec71c] | 755 | |
---|
[5194a28] | 756 | #if (__mips == 3) || (__mips == 32) |
---|
| 757 | #define _INTON SR_IE |
---|
[7c99007] | 758 | #if __mips_fpr==64 |
---|
| 759 | #define _EXTRABITS SR_FR |
---|
| 760 | #else |
---|
[bd1ecb0] | 761 | #define _EXTRABITS 0 |
---|
[7c99007] | 762 | #endif /* __mips_fpr==64 */ |
---|
| 763 | #endif /* __mips == 3 */ |
---|
[e6dec71c] | 764 | #if __mips == 1 |
---|
[bd1ecb0] | 765 | #define _INTON SR_IEC |
---|
| 766 | #define _EXTRABITS 0 /* make sure we're in user mode on MIPS1 processors */ |
---|
[7c99007] | 767 | #endif /* __mips == 1 */ |
---|
[e6dec71c] | 768 | |
---|
[7908ba5b] | 769 | |
---|
[a0cb87c] | 770 | void _CPU_Context_Initialize( |
---|
| 771 | Context_Control *the_context, |
---|
| 772 | uintptr_t *stack_base, |
---|
| 773 | uint32_t size, |
---|
| 774 | uint32_t new_level, |
---|
| 775 | void *entry_point, |
---|
[022851a] | 776 | bool is_fp, |
---|
| 777 | void *tls_area |
---|
[a0cb87c] | 778 | ); |
---|
[e6dec71c] | 779 | |
---|
| 780 | |
---|
[7908ba5b] | 781 | /* |
---|
| 782 | * This routine is responsible for somehow restarting the currently |
---|
| 783 | * executing task. If you are lucky, then all that is necessary |
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| 784 | * is restoring the context. Otherwise, there will need to be |
---|
| 785 | * a special assembly routine which does something special in this |
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| 786 | * case. Context_Restore should work most of the time. It will |
---|
| 787 | * not work if restarting self conflicts with the stack frame |
---|
| 788 | * assumptions of restoring a context. |
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| 789 | */ |
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| 790 | |
---|
| 791 | #define _CPU_Context_Restart_self( _the_context ) \ |
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| 792 | _CPU_Context_restore( (_the_context) ); |
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| 793 | |
---|
| 794 | /* |
---|
| 795 | * This routine initializes the FP context area passed to it to. |
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| 796 | * There are a few standard ways in which to initialize the |
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| 797 | * floating point context. The code included for this macro assumes |
---|
| 798 | * that this is a CPU in which a "initial" FP context was saved into |
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| 799 | * _CPU_Null_fp_context and it simply copies it to the destination |
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| 800 | * context passed to it. |
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| 801 | * |
---|
| 802 | * Other models include (1) not doing anything, and (2) putting |
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| 803 | * a "null FP status word" in the correct place in the FP context. |
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| 804 | */ |
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| 805 | |
---|
[2e549dad] | 806 | #if ( CPU_HARDWARE_FP == TRUE ) |
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[7908ba5b] | 807 | #define _CPU_Context_Initialize_fp( _destination ) \ |
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| 808 | { \ |
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[0edd196] | 809 | *(*(_destination)) = _CPU_Null_fp_context; \ |
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[7908ba5b] | 810 | } |
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[2e549dad] | 811 | #endif |
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[7908ba5b] | 812 | |
---|
| 813 | /* end of Context handler macros */ |
---|
| 814 | |
---|
| 815 | /* Fatal Error manager macros */ |
---|
| 816 | |
---|
| 817 | /* |
---|
| 818 | * This routine copies _error into a known place -- typically a stack |
---|
| 819 | * location or a register, optionally disables interrupts, and |
---|
| 820 | * halts/stops the CPU. |
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| 821 | */ |
---|
| 822 | |
---|
[f82752a4] | 823 | #define _CPU_Fatal_halt( _source, _error ) \ |
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[32f415d] | 824 | do { \ |
---|
| 825 | unsigned int _level; \ |
---|
| 826 | _CPU_ISR_Disable(_level); \ |
---|
[59c0559] | 827 | (void)_level; \ |
---|
[aa7f8a1f] | 828 | loop: goto loop; \ |
---|
[32f415d] | 829 | } while (0) |
---|
[7908ba5b] | 830 | |
---|
[aa7f8a1f] | 831 | |
---|
| 832 | extern void mips_break( int error ); |
---|
[7908ba5b] | 833 | |
---|
| 834 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
| 835 | |
---|
| 836 | /* functions */ |
---|
| 837 | |
---|
| 838 | /* |
---|
| 839 | * _CPU_Initialize |
---|
| 840 | * |
---|
| 841 | * This routine performs CPU dependent initialization. |
---|
| 842 | */ |
---|
| 843 | |
---|
[c03e2bc] | 844 | void _CPU_Initialize(void); |
---|
[7908ba5b] | 845 | |
---|
| 846 | /* |
---|
| 847 | * _CPU_ISR_install_raw_handler |
---|
| 848 | * |
---|
[e2040ba] | 849 | * This routine installs a "raw" interrupt handler directly into the |
---|
[7908ba5b] | 850 | * processor's vector table. |
---|
| 851 | */ |
---|
[e2040ba] | 852 | |
---|
[7908ba5b] | 853 | void _CPU_ISR_install_raw_handler( |
---|
[c346f33d] | 854 | uint32_t vector, |
---|
[7908ba5b] | 855 | proc_ptr new_handler, |
---|
| 856 | proc_ptr *old_handler |
---|
| 857 | ); |
---|
| 858 | |
---|
| 859 | /* |
---|
| 860 | * _CPU_ISR_install_vector |
---|
| 861 | * |
---|
| 862 | * This routine installs an interrupt vector. |
---|
| 863 | */ |
---|
| 864 | |
---|
| 865 | void _CPU_ISR_install_vector( |
---|
[c346f33d] | 866 | uint32_t vector, |
---|
[7908ba5b] | 867 | proc_ptr new_handler, |
---|
| 868 | proc_ptr *old_handler |
---|
| 869 | ); |
---|
| 870 | |
---|
| 871 | /* |
---|
| 872 | * _CPU_Install_interrupt_stack |
---|
| 873 | * |
---|
| 874 | * This routine installs the hardware interrupt stack pointer. |
---|
| 875 | * |
---|
| 876 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
| 877 | * is TRUE. |
---|
| 878 | */ |
---|
| 879 | |
---|
| 880 | void _CPU_Install_interrupt_stack( void ); |
---|
| 881 | |
---|
| 882 | /* |
---|
| 883 | * _CPU_Internal_threads_Idle_thread_body |
---|
| 884 | * |
---|
| 885 | * This routine is the CPU dependent IDLE thread body. |
---|
| 886 | * |
---|
| 887 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
---|
| 888 | * is TRUE. |
---|
| 889 | */ |
---|
| 890 | |
---|
[cca8379] | 891 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
---|
[7908ba5b] | 892 | |
---|
| 893 | /* |
---|
| 894 | * _CPU_Context_switch |
---|
| 895 | * |
---|
| 896 | * This routine switches from the run context to the heir context. |
---|
| 897 | */ |
---|
| 898 | |
---|
| 899 | void _CPU_Context_switch( |
---|
| 900 | Context_Control *run, |
---|
| 901 | Context_Control *heir |
---|
| 902 | ); |
---|
| 903 | |
---|
| 904 | /* |
---|
| 905 | * _CPU_Context_restore |
---|
| 906 | * |
---|
| 907 | * This routine is generally used only to restart self in an |
---|
| 908 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
| 909 | * |
---|
| 910 | * NOTE: May be unnecessary to reload some registers. |
---|
| 911 | */ |
---|
| 912 | |
---|
| 913 | void _CPU_Context_restore( |
---|
| 914 | Context_Control *new_context |
---|
[143696a] | 915 | ) RTEMS_NO_RETURN; |
---|
[7908ba5b] | 916 | |
---|
| 917 | /* |
---|
| 918 | * _CPU_Context_save_fp |
---|
| 919 | * |
---|
| 920 | * This routine saves the floating point context passed to it. |
---|
| 921 | */ |
---|
| 922 | |
---|
| 923 | void _CPU_Context_save_fp( |
---|
[0edd196] | 924 | Context_Control_fp **fp_context_ptr |
---|
[7908ba5b] | 925 | ); |
---|
| 926 | |
---|
| 927 | /* |
---|
| 928 | * _CPU_Context_restore_fp |
---|
| 929 | * |
---|
| 930 | * This routine restores the floating point context passed to it. |
---|
| 931 | */ |
---|
| 932 | |
---|
| 933 | void _CPU_Context_restore_fp( |
---|
[0edd196] | 934 | Context_Control_fp **fp_context_ptr |
---|
[7908ba5b] | 935 | ); |
---|
| 936 | |
---|
[39993d6] | 937 | static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) |
---|
| 938 | { |
---|
| 939 | /* TODO */ |
---|
| 940 | } |
---|
| 941 | |
---|
| 942 | static inline void _CPU_Context_validate( uintptr_t pattern ) |
---|
| 943 | { |
---|
| 944 | while (1) { |
---|
| 945 | /* TODO */ |
---|
| 946 | } |
---|
| 947 | } |
---|
| 948 | |
---|
[c48cf0bd] | 949 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
[815994f] | 950 | |
---|
[7908ba5b] | 951 | /* The following routine swaps the endian format of an unsigned int. |
---|
| 952 | * It must be static because it is referenced indirectly. |
---|
| 953 | * |
---|
| 954 | * This version will work on any processor, but if there is a better |
---|
| 955 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
| 956 | * |
---|
| 957 | * swap least significant two bytes with 16-bit rotate |
---|
| 958 | * swap upper and lower 16-bits |
---|
| 959 | * swap most significant two bytes with 16-bit rotate |
---|
| 960 | * |
---|
| 961 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
| 962 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
| 963 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
[ece004d] | 964 | * that interrupts would probably have to be disabled to ensure that |
---|
[7908ba5b] | 965 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
| 966 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
| 967 | * endianness for ALL fetches -- both code and data -- so the code |
---|
| 968 | * will be fetched incorrectly. |
---|
| 969 | */ |
---|
[e2040ba] | 970 | |
---|
[ec8973ed] | 971 | static inline uint32_t CPU_swap_u32( |
---|
| 972 | uint32_t value |
---|
[7908ba5b] | 973 | ) |
---|
| 974 | { |
---|
[c346f33d] | 975 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
[e2040ba] | 976 | |
---|
[7908ba5b] | 977 | byte4 = (value >> 24) & 0xff; |
---|
| 978 | byte3 = (value >> 16) & 0xff; |
---|
| 979 | byte2 = (value >> 8) & 0xff; |
---|
| 980 | byte1 = value & 0xff; |
---|
[e2040ba] | 981 | |
---|
[7908ba5b] | 982 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
| 983 | return( swapped ); |
---|
| 984 | } |
---|
| 985 | |
---|
| 986 | #define CPU_swap_u16( value ) \ |
---|
| 987 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
| 988 | |
---|
[24bf11e] | 989 | typedef uint32_t CPU_Counter_ticks; |
---|
| 990 | |
---|
| 991 | CPU_Counter_ticks _CPU_Counter_read( void ); |
---|
| 992 | |
---|
| 993 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
---|
| 994 | CPU_Counter_ticks second, |
---|
| 995 | CPU_Counter_ticks first |
---|
| 996 | ) |
---|
| 997 | { |
---|
| 998 | return second - first; |
---|
| 999 | } |
---|
[bd1ecb0] | 1000 | |
---|
| 1001 | #endif |
---|
| 1002 | |
---|
| 1003 | |
---|
| 1004 | |
---|
[7908ba5b] | 1005 | #ifdef __cplusplus |
---|
| 1006 | } |
---|
| 1007 | #endif |
---|
| 1008 | |
---|
[a1f9934a] | 1009 | /**@}*/ |
---|
[b10825c] | 1010 | #endif |
---|