source: rtems/cpukit/score/cpu/mips/rtems/mips/idtcpu.h @ bd1ecb0

4.104.114.84.95
Last change on this file since bd1ecb0 was bd1ecb0, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 1, 2002 at 4:21:12 PM

2002-02-27 Greg Menke <gregory.menke@…>

  • cpu_asm.S: Fixed exception return address, modified FP context switch so FPU is properly enabled and also doesn't screw up the exception FP handling.
  • idtcpu.h: Added C0_TAR, the MIPS target address register used for returning from exceptions.
  • iregdef.h: Added R_TAR to the stack frame so the target address can be saved on a per-exception basis. The new entry is past the end of the frame gdb cares about, so doesn't affect gdb or cpu.h stuff.
  • rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it to obtain FPU defines without systax errors generated by the C defintions.
  • cpu.c: Improved interrupt level saves & restores.
  • Property mode set to 100644
File size: 14.4 KB
Line 
1/*
2
3Based upon IDT provided code with the following release:
4
5This source code has been made available to you by IDT on an AS-IS
6basis. Anyone receiving this source is licensed under IDT copyrights
7to use it in any way he or she deems fit, including copying it,
8modifying it, compiling it, and redistributing it either with or
9without modifications.  No license under IDT patents or patent
10applications is to be implied by the copyright license.
11
12Any user of this software should understand that IDT cannot provide
13technical support for this software and will not be responsible for
14any consequences resulting from the use of this software.
15
16Any person who transfers this source code or any derivative work must
17include the IDT copyright notice, this paragraph, and the preceeding
18two paragraphs in the transferred software.
19
20COPYRIGHT IDT CORPORATION 1996
21LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
22
23  $Id$
24*/ 
25
26/*
27** idtcpu.h -- cpu related defines
28*/
29
30#ifndef _IDTCPU_H__
31#define _IDTCPU_H__
32
33/*
34 * 950313: Ketan added Register definition for XContext reg.
35 *               added define for WAIT instruction.
36 * 950421: Ketan added Register definition for Config reg (R3081)
37 */
38
39/*
40** memory configuration and mapping
41*/
42#define K0BASE  0x80000000
43#define K0SIZE  0x20000000
44#define K1BASE  0xa0000000
45#define K1SIZE  0x20000000
46#define K2BASE  0xc0000000
47#define K2SIZE  0x20000000
48#if  __mips == 3
49#define KSBASE  0xe0000000
50#define KSSIZE  0x20000000
51#endif
52
53#define KUBASE  0
54#define KUSIZE  0x80000000
55
56/*
57** Exception Vectors
58*/
59#if  __mips == 1
60#define UT_VEC  K0BASE                  /* utlbmiss vector */
61#define E_VEC   (K0BASE+0x80)           /* exception vevtor */
62#elif  __mips == 3
63#define T_VEC   (K0BASE+0x000)          /* tlbmiss vector */
64#define X_VEC   (K0BASE+0x080)          /* xtlbmiss vector */
65#define C_VEC   (K0BASE+0x100)          /* cache error vector */
66#define E_VEC   (K0BASE+0x180)          /* exception vector */
67#else
68#error "EXCEPTION VECTORS: unknown ISA level"
69#endif
70#define R_VEC   (K1BASE+0x1fc00000)     /* reset vector */
71
72/*
73** Address conversion macros
74*/
75#ifdef CLANGUAGE
76#define CAST(as) (as)
77#else
78#define CAST(as)
79#endif
80#define K0_TO_K1(x)     (CAST(unsigned)(x)|0xA0000000)  /* kseg0 to kseg1 */
81#define K1_TO_K0(x)     (CAST(unsigned)(x)&0x9FFFFFFF)  /* kseg1 to kseg0 */
82#define K0_TO_PHYS(x)   (CAST(unsigned)(x)&0x1FFFFFFF)  /* kseg0 to physical */
83#define K1_TO_PHYS(x)   (CAST(unsigned)(x)&0x1FFFFFFF)  /* kseg1 to physical */
84#define PHYS_TO_K0(x)   (CAST(unsigned)(x)|0x80000000)  /* physical to kseg0 */
85#define PHYS_TO_K1(x)   (CAST(unsigned)(x)|0xA0000000)  /* physical to kseg1 */
86
87/*
88**      Cache size constants
89*/
90#define MINCACHE        0x200           /* 512       For 3041. */
91#define MAXCACHE        0x40000         /* 256*1024   256k */   
92
93#if  __mips == 3
94/* R4000 configuration register definitions */
95#define CFG_CM          0x80000000      /* Master-Checker mode */
96#define CFG_ECMASK      0x70000000      /* System Clock Ratio */
97#define CFG_ECBY2       0x00000000      /* divide by 2 */
98#define CFG_ECBY3       0x10000000      /* divide by 3 */
99#define CFG_ECBY4       0x20000000      /* divide by 4 */
100#define CFG_EPMASK      0x0f000000      /* Transmit data pattern */
101#define CFG_EPD         0x00000000      /* D */
102#define CFG_EPDDX       0x01000000      /* DDX */
103#define CFG_EPDDXX      0x02000000      /* DDXX */
104#define CFG_EPDXDX      0x03000000      /* DXDX */
105#define CFG_EPDDXXX     0x04000000      /* DDXXX */
106#define CFG_EPDDXXXX    0x05000000      /* DDXXXX */
107#define CFG_EPDXXDXX    0x06000000      /* DXXDXX */
108#define CFG_EPDDXXXXX   0x07000000      /* DDXXXXX */
109#define CFG_EPDXXXDXXX  0x08000000      /* DXXXDXXX */
110#define CFG_SBMASK      0x00c00000      /* Secondary cache block size */
111#define CFG_SBSHIFT     22
112#define CFG_SB4         0x00000000      /* 4 words */
113#define CFG_SB8         0x00400000      /* 8 words */
114#define CFG_SB16        0x00800000      /* 16 words */
115#define CFG_SB32        0x00c00000      /* 32 words */
116#define CFG_SS          0x00200000      /* Split secondary cache */
117#define CFG_SW          0x00100000      /* Secondary cache port width */
118#define CFG_EWMASK      0x000c0000      /* System port width */
119#define CFG_EWSHIFT     18
120#define CFG_EW64        0x00000000      /* 64 bit */
121#define CFG_EW32        0x00010000      /* 32 bit */
122#define CFG_SC          0x00020000      /* Secondary cache absent */
123#define CFG_SM          0x00010000      /* Dirty Shared mode disabled */
124#define CFG_BE          0x00008000      /* Big Endian */
125#define CFG_EM          0x00004000      /* ECC mode enable */
126#define CFG_EB          0x00002000      /* Block ordering */
127#define CFG_ICMASK      0x00000e00      /* Instruction cache size */
128#define CFG_ICSHIFT     9
129#define CFG_DCMASK      0x000001c0      /* Data cache size */
130#define CFG_DCSHIFT     6
131#define CFG_IB          0x00000020      /* Instruction cache block size */
132#define CFG_DB          0x00000010      /* Data cache block size */
133#define CFG_CU          0x00000008      /* Update on Store Conditional */
134#define CFG_K0MASK      0x00000007      /* KSEG0 coherency algorithm */
135
136/*
137 * R4000 primary cache mode
138 */
139#define CFG_C_UNCACHED          2
140#define CFG_C_NONCOHERENT       3
141#define CFG_C_COHERENTXCL       4
142#define CFG_C_COHERENTXCLW      5
143#define CFG_C_COHERENTUPD       6
144
145/*
146 * R4000 cache operations (should be in assembler...?)
147 */
148#define Index_Invalidate_I               0x0         /* 0       0 */
149#define Index_Writeback_Inv_D            0x1         /* 0       1 */
150#define Index_Invalidate_SI              0x2         /* 0       2 */
151#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
152#define Index_Load_Tag_I                 0x4         /* 1       0 */
153#define Index_Load_Tag_D                 0x5         /* 1       1 */
154#define Index_Load_Tag_SI                0x6         /* 1       2 */
155#define Index_Load_Tag_SD                0x7         /* 1       3 */
156#define Index_Store_Tag_I                0x8         /* 2       0 */
157#define Index_Store_Tag_D                0x9         /* 2       1 */
158#define Index_Store_Tag_SI               0xA         /* 2       2 */
159#define Index_Store_Tag_SD               0xB         /* 2       3 */
160#define Create_Dirty_Exc_D               0xD         /* 3       1 */
161#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
162#define Hit_Invalidate_I                 0x10        /* 4       0 */
163#define Hit_Invalidate_D                 0x11        /* 4       1 */
164#define Hit_Invalidate_SI                0x12        /* 4       2 */
165#define Hit_Invalidate_SD                0x13        /* 4       3 */
166#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
167#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
168#define Fill_I                           0x14        /* 5       0 */
169#define Hit_Writeback_D                  0x19        /* 6       1 */
170#define Hit_Writeback_SD                 0x1B        /* 6       3 */
171#define Hit_Writeback_I                  0x18        /* 6       0 */
172#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
173#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
174
175#ifndef WAIT
176#define WAIT .word 0x42000020
177#endif WAIT
178
179/* Disabled by joel -- horrible overload of common word.
180#ifndef wait
181#define wait .word 0x42000020
182#endif wait
183*/
184
185#endif
186
187/*
188** TLB resource defines
189*/
190#if  __mips == 1
191#define N_TLB_ENTRIES   64
192#define TLB_PGSIZE      0x1000
193#define RANDBASE        8
194#define TLBLO_PFNMASK   0xfffff000
195#define TLBLO_PFNSHIFT  12
196#define TLBLO_N         0x800   /* non-cacheable */
197#define TLBLO_D         0x400   /* writeable */
198#define TLBLO_V         0x200   /* valid bit */
199#define TLBLO_G         0x100   /* global access bit */
200
201#define TLBHI_VPNMASK   0xfffff000
202#define TLBHI_VPNSHIFT  12
203#define TLBHI_PIDMASK   0xfc0
204#define TLBHI_PIDSHIFT  6
205#define TLBHI_NPID      64
206
207#define TLBINX_PROBE    0x80000000
208#define TLBINX_INXMASK  0x00003f00
209#define TLBINX_INXSHIFT 8
210
211#define TLBRAND_RANDMASK        0x00003f00
212#define TLBRAND_RANDSHIFT       8
213
214#define TLBCTXT_BASEMASK        0xffe00000
215#define TLBCTXT_BASESHIFT       21
216
217#define TLBCTXT_VPNMASK         0x001ffffc
218#define TLBCTXT_VPNSHIFT        2
219#endif
220#if  __mips == 3
221#define N_TLB_ENTRIES   48
222
223#define TLBHI_VPN2MASK  0xffffe000
224#define TLBHI_PIDMASK   0x000000ff
225#define TLBHI_NPID      256
226
227#define TLBLO_PFNMASK   0x3fffffc0
228#define TLBLO_PFNSHIFT  6
229#define TLBLO_D         0x00000004      /* writeable */
230#define TLBLO_V         0x00000002      /* valid bit */
231#define TLBLO_G         0x00000001      /* global access bit */
232#define TLBLO_CMASK     0x00000038      /* cache algorithm mask */
233#define TLBLO_CSHIFT    3
234
235#define TLBLO_UNCACHED          (CFG_C_UNCACHED<<TLBLO_CSHIFT)
236#define TLBLO_NONCOHERENT       (CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
237#define TLBLO_COHERENTXCL       (CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
238#define TLBLO_COHERENTXCLW      (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
239#define TLBLO_COHERENTUPD       (CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
240
241#define TLBINX_PROBE    0x80000000
242#define TLBINX_INXMASK  0x0000003f
243
244#define TLBRAND_RANDMASK        0x0000003f
245
246#define TLBCTXT_BASEMASK        0xff800000
247#define TLBCTXT_BASESHIFT       23
248
249#define TLBCTXT_VPN2MASK        0x007ffff0
250#define TLBCTXT_VPN2SHIFT       4
251
252#define TLBPGMASK_MASK          0x01ffe000
253#endif
254
255#if  __mips == 1
256#define SR_CUMASK       0xf0000000      /* coproc usable bits */
257#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
258#define SR_CU2          0x40000000      /* Coprocessor 2 usable */
259#define SR_CU1          0x20000000      /* Coprocessor 1 usable */
260#define SR_CU0          0x10000000      /* Coprocessor 0 usable */
261
262#define SR_BEV          0x00400000      /* use boot exception vectors */
263
264/* Cache control bits */
265#define SR_TS           0x00200000      /* TLB shutdown */
266#define SR_PE           0x00100000      /* cache parity error */
267#define SR_CM           0x00080000      /* cache miss */
268#define SR_PZ           0x00040000      /* cache parity zero */
269#define SR_SWC          0x00020000      /* swap cache */
270#define SR_ISC          0x00010000      /* Isolate data cache */
271
272/*
273**      status register interrupt masks and bits
274*/
275
276#define SR_IMASK        0x0000ff00      /* Interrupt mask */
277#define SR_IMASK8       0x00000000      /* mask level 8 */
278#define SR_IMASK7       0x00008000      /* mask level 7 */
279#define SR_IMASK6       0x0000c000      /* mask level 6 */
280#define SR_IMASK5       0x0000e000      /* mask level 5 */
281#define SR_IMASK4       0x0000f000      /* mask level 4 */
282#define SR_IMASK3       0x0000f800      /* mask level 3 */
283#define SR_IMASK2       0x0000fc00      /* mask level 2 */
284#define SR_IMASK1       0x0000fe00      /* mask level 1 */
285#define SR_IMASK0       0x0000ff00      /* mask level 0 */
286
287#define SR_IMASKSHIFT   8
288
289#define SR_IBIT8        0x00008000      /* bit level 8 */
290#define SR_IBIT7        0x00004000      /* bit level 7 */
291#define SR_IBIT6        0x00002000      /* bit level 6 */
292#define SR_IBIT5        0x00001000      /* bit level 5 */
293#define SR_IBIT4        0x00000800      /* bit level 4 */
294#define SR_IBIT3        0x00000400      /* bit level 3 */
295#define SR_IBIT2        0x00000200      /* bit level 2 */
296#define SR_IBIT1        0x00000100      /* bit level 1 */
297
298#define SR_KUO          0x00000020      /* old kernel/user, 0 => k, 1 => u */
299#define SR_IEO          0x00000010      /* old interrupt enable, 1 => enable */
300#define SR_KUP          0x00000008      /* prev kernel/user, 0 => k, 1 => u */
301#define SR_IEP          0x00000004      /* prev interrupt enable, 1 => enable */
302#define SR_KUC          0x00000002      /* cur kernel/user, 0 => k, 1 => u */
303#define SR_IEC          0x00000001      /* cur interrupt enable, 1 => enable */
304#endif
305
306#if  __mips == 3
307#define SR_CUMASK       0xf0000000      /* coproc usable bits */
308#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
309#define SR_CU2          0x40000000      /* Coprocessor 2 usable */
310#define SR_CU1          0x20000000      /* Coprocessor 1 usable */
311#define SR_CU0          0x10000000      /* Coprocessor 0 usable */
312
313#define SR_RP           0x08000000      /* Reduced power operation */
314#define SR_FR           0x04000000      /* Additional floating point registers */
315#define SR_RE           0x02000000      /* Reverse endian in user mode */
316
317#define SR_BEV          0x00400000      /* Use boot exception vectors */
318#define SR_TS           0x00200000      /* TLB shutdown */
319#define SR_SR           0x00100000      /* Soft reset */
320#define SR_CH           0x00040000      /* Cache hit */
321#define SR_CE           0x00020000      /* Use cache ECC  */
322#define SR_DE           0x00010000      /* Disable cache exceptions */
323
324/*
325**      status register interrupt masks and bits
326*/
327
328#define SR_IMASK        0x0000ff00      /* Interrupt mask */
329#define SR_IMASK8       0x00000000      /* mask level 8 */
330#define SR_IMASK7       0x00008000      /* mask level 7 */
331#define SR_IMASK6       0x0000c000      /* mask level 6 */
332#define SR_IMASK5       0x0000e000      /* mask level 5 */
333#define SR_IMASK4       0x0000f000      /* mask level 4 */
334#define SR_IMASK3       0x0000f800      /* mask level 3 */
335#define SR_IMASK2       0x0000fc00      /* mask level 2 */
336#define SR_IMASK1       0x0000fe00      /* mask level 1 */
337#define SR_IMASK0       0x0000ff00      /* mask level 0 */
338
339#define SR_IMASKSHIFT   8
340
341#define SR_IBIT8        0x00008000      /* bit level 8 */
342#define SR_IBIT7        0x00004000      /* bit level 7 */
343#define SR_IBIT6        0x00002000      /* bit level 6 */
344#define SR_IBIT5        0x00001000      /* bit level 5 */
345#define SR_IBIT4        0x00000800      /* bit level 4 */
346#define SR_IBIT3        0x00000400      /* bit level 3 */
347#define SR_IBIT2        0x00000200      /* bit level 2 */
348#define SR_IBIT1        0x00000100      /* bit level 1 */
349
350#define SR_KSMASK       0x00000018      /* Kernel mode mask */
351#define SR_KSUSER       0x00000010      /* User mode */
352#define SR_KSSUPER      0x00000008      /* Supervisor mode */
353#define SR_KSKERNEL     0x00000000      /* Kernel mode */
354#define SR_ERL          0x00000004      /* Error level */
355#define SR_EXL          0x00000002      /* Exception level */
356#define SR_IE           0x00000001      /* Interrupts enabled */
357#endif
358
359
360
361/*
362 * Cause Register
363 */
364#define CAUSE_BD        0x80000000      /* Branch delay slot */
365#define CAUSE_BT        0x40000000      /* Branch Taken */
366#define CAUSE_CEMASK    0x30000000      /* coprocessor error */
367#define CAUSE_CESHIFT   28
368
369
370#define CAUSE_IPMASK    0x0000FF00      /* Pending interrupt mask */
371#define CAUSE_IPSHIFT   8
372
373#define CAUSE_EXCMASK   0x0000003C      /* Cause code bits */
374#define CAUSE_EXCSHIFT  2
375
376#ifndef XDS
377/*
378**  Coprocessor 0 registers
379*/
380#define C0_INX          $0              /* tlb index */
381#define C0_RAND         $1              /* tlb random */
382#if  __mips == 1
383#define C0_TLBLO        $2              /* tlb entry low */
384#endif
385#if  __mips == 3
386#define C0_TLBLO0       $2              /* tlb entry low 0 */
387#define C0_TLBLO1       $3              /* tlb entry low 1 */
388#endif
389
390#define C0_CTXT         $4              /* tlb context */
391
392#if  __mips == 3
393#define C0_PAGEMASK     $5              /* tlb page mask */
394#define C0_WIRED        $6              /* number of wired tlb entries */
395#endif
396
397#if  __mips == 1
398#define C0_TAR          $6
399#endif
400
401#define C0_BADVADDR     $8              /* bad virtual address */
402
403#if  __mips == 3
404#define C0_COUNT        $9              /* cycle count */
405#endif
406
407#define C0_TLBHI        $10             /* tlb entry hi */
408
409#if  __mips == 3
410#define C0_COMPARE      $11             /* cyccle count comparator  */
411#endif
412
413#define C0_SR           $12             /* status register */
414#define C0_CAUSE        $13             /* exception cause */
415#define C0_EPC          $14             /* exception pc */
416#define C0_PRID         $15             /* revision identifier */
417
418#if  __mips == 1
419#define C0_CONFIG   $3     /* configuration register R3081*/
420#endif
421
422#if  __mips == 3
423#define C0_CONFIG       $16             /* configuration register */
424#define C0_LLADDR       $17             /* linked load address */
425#define C0_WATCHLO      $18             /* watchpoint trap register */
426#define C0_WATCHHI      $19             /* watchpoint trap register */
427#define C0_XCTXT    $20     /* extended tlb context */
428#define C0_ECC          $26             /* secondary cache ECC control */
429#define C0_CACHEERR     $27             /* cache error status */
430#define C0_TAGLO        $28             /* cache tag lo */
431#define C0_TAGHI        $29             /* cache tag hi */
432#define C0_ERRPC        $30             /* cache error pc */
433#endif
434
435#define C1_REVISION     $0
436#define C1_STATUS       $31
437
438#endif XDS
439
440#ifdef R4650
441#define IWATCH $18
442#define DWATCH $19
443#define IBASE  $0
444#define IBOUND $1
445#define DBASE  $2
446#define DBOUND $3
447#define CALG    $17
448#endif
449
450#endif /* _IDTCPU_H__ */
451
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