source: rtems/cpukit/score/cpu/mips/include/rtems/score/cpu.h @ ee38c54

5
Last change on this file since ee38c54 was 5526527e, checked in by Sebastian Huber <sebastian.huber@…>, on 03/25/19 at 09:45:25

score: Rename ScoreCPU Doxygen group

Update #3706.
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1/**
2 *  @file
3 *
4 *  @brief Mips CPU Dependent Header File
5 */
6
7/*
8 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
9 *           Joel Sherrill <joel@OARcorp.com>.
10 *
11 *    These changes made the code conditional on standard cpp predefines,
12 *    merged the mips1 and mips3 code sequences as much as possible,
13 *    and moved some of the assembly code to C.  Alan did much of the
14 *    initial analysis and rework.  Joel took over from there and
15 *    wrote the JMR3904 BSP so this could be tested.  Joel also
16 *    added the new interrupt vectoring support in libcpu and
17 *    tried to better support the various interrupt controllers.
18 *
19 */
20
21/*
22 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
23 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
24 *
25 *    To anyone who acknowledges that this file is provided "AS IS"
26 *    without any express or implied warranty:
27 *      permission to use, copy, modify, and distribute this file
28 *      for any purpose is hereby granted without fee, provided that
29 *      the above copyright notice and this notice appears in all
30 *      copies, and that the name of Transition Networks not be used in
31 *      advertising or publicity pertaining to distribution of the
32 *      software without specific, written prior permission.
33 *      Transition Networks makes no representations about the suitability
34 *      of this software for any purpose.
35 *
36 *  COPYRIGHT (c) 1989-2012.
37 *  On-Line Applications Research Corporation (OAR).
38 *
39 *  The license and distribution terms for this file may be
40 *  found in the file LICENSE in this distribution or at
41 *  http://www.rtems.org/license/LICENSE.
42 */
43
44#ifndef _RTEMS_SCORE_CPU_H
45#define _RTEMS_SCORE_CPU_H
46
47/**
48 *  @defgroup RTEMSScoreCPU CPU CPU
49 *
50 *  @ingroup Score
51 *
52 */
53/**@{*/
54
55#ifdef __cplusplus
56extern "C" {
57#endif
58
59#include <rtems/score/basedefs.h>
60#include <rtems/score/mips.h>
61
62/* conditional compilation parameters */
63
64/*
65 *  Does the CPU follow the simple vectored interrupt model?
66 *
67 *  If TRUE, then RTEMS allocates the vector table it internally manages.
68 *  If FALSE, then the BSP is assumed to allocate and manage the vector
69 *  table
70 *
71 *  MIPS Specific Information:
72 *
73 *  Up to and including RTEMS 4.10, the MIPS port used simple vectored
74 *  interrupts. But this was changed to the PIC model after 4.10.
75 */
76#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
77
78/*
79 *  Does the RTEMS invoke the user's ISR with the vector number and
80 *  a pointer to the saved interrupt frame (1) or just the vector
81 *  number (0)?
82 *
83 */
84
85#define CPU_ISR_PASSES_FRAME_POINTER TRUE
86
87
88
89/*
90 *  Does the CPU have hardware floating point?
91 *
92 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
93 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
94 *
95 *  If there is a FP coprocessor such as the i387 or mc68881, then
96 *  the answer is TRUE.
97 *
98 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
99 *  It indicates whether or not this CPU model has FP support.  For
100 *  example, it would be possible to have an i386_nofp CPU model
101 *  which set this to false to indicate that you have an i386 without
102 *  an i387 and wish to leave floating point support out of RTEMS.
103 */
104
105#if ( MIPS_HAS_FPU == 1 )
106#define CPU_HARDWARE_FP     TRUE
107#else
108#define CPU_HARDWARE_FP     FALSE
109#endif
110
111/*
112 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
113 *
114 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
115 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
116 *
117 *  So far, the only CPU in which this option has been used is the
118 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
119 *  floating point registers to perform integer multiplies.  If
120 *  a function which you would not think utilize the FP unit DOES,
121 *  then one can not easily predict which tasks will use the FP hardware.
122 *  In this case, this option should be TRUE.
123 *
124 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
125 *
126 *  Mips Note: It appears the GCC can implicitly generate FPU
127 *  and Altivec instructions when you least expect them.  So make
128 *  all tasks floating point.
129 */
130
131#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
132
133/*
134 *  Should the IDLE task have a floating point context?
135 *
136 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
137 *  and it has a floating point context which is switched in and out.
138 *  If FALSE, then the IDLE task does not have a floating point context.
139 *
140 *  Setting this to TRUE negatively impacts the time required to preempt
141 *  the IDLE task from an interrupt because the floating point context
142 *  must be saved as part of the preemption.
143 */
144
145#define CPU_IDLE_TASK_IS_FP      FALSE
146
147/*
148 *  Should the saving of the floating point registers be deferred
149 *  until a context switch is made to another different floating point
150 *  task?
151 *
152 *  If TRUE, then the floating point context will not be stored until
153 *  necessary.  It will remain in the floating point registers and not
154 *  disturned until another floating point task is switched to.
155 *
156 *  If FALSE, then the floating point context is saved when a floating
157 *  point task is switched out and restored when the next floating point
158 *  task is restored.  The state of the floating point registers between
159 *  those two operations is not specified.
160 *
161 *  If the floating point context does NOT have to be saved as part of
162 *  interrupt dispatching, then it should be safe to set this to TRUE.
163 *
164 *  Setting this flag to TRUE results in using a different algorithm
165 *  for deciding when to save and restore the floating point context.
166 *  The deferred FP switch algorithm minimizes the number of times
167 *  the FP context is saved and restored.  The FP context is not saved
168 *  until a context switch is made to another, different FP task.
169 *  Thus in a system with only one FP task, the FP context will never
170 *  be saved or restored.
171 */
172
173#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
174
175#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
176
177/*
178 *  Does the stack grow up (toward higher addresses) or down
179 *  (toward lower addresses)?
180 *
181 *  If TRUE, then the grows upward.
182 *  If FALSE, then the grows toward smaller addresses.
183 */
184
185/* our stack grows down */
186#define CPU_STACK_GROWS_UP               FALSE
187
188/* FIXME: Is this the right value? */
189#define CPU_CACHE_LINE_BYTES 16
190
191#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
192
193/*
194 *  The following defines the number of bits actually used in the
195 *  interrupt field of the task mode.  How those bits map to the
196 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
197 */
198
199#define CPU_MODES_INTERRUPT_MASK   0x000000ff
200
201#define CPU_SIZEOF_POINTER 4
202
203#define CPU_MAXIMUM_PROCESSORS 32
204
205/*
206 *  Processor defined structures
207 *
208 *  Examples structures include the descriptor tables from the i386
209 *  and the processor control structure on the i960ca.
210 */
211
212/* may need to put some structures here.  */
213
214/*
215 * Contexts
216 *
217 *  Generally there are 2 types of context to save.
218 *     1. Interrupt registers to save
219 *     2. Task level registers to save
220 *
221 *  This means we have the following 3 context items:
222 *     1. task level context stuff::  Context_Control
223 *     2. floating point task stuff:: Context_Control_fp
224 *     3. special interrupt level context :: Context_Control_interrupt
225 *
226 *  On some processors, it is cost-effective to save only the callee
227 *  preserved registers during a task context switch.  This means
228 *  that the ISR code needs to save those registers which do not
229 *  persist across function calls.  It is not mandatory to make this
230 *  distinctions between the caller/callee saves registers for the
231 *  purpose of minimizing context saved during task switch and on interrupts.
232 *  If the cost of saving extra registers is minimal, simplicity is the
233 *  choice.  Save the same context on interrupt entry as for tasks in
234 *  this case.
235 *
236 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
237 *  care should be used in designing the context area.
238 *
239 *  On some CPUs with hardware floating point support, the Context_Control_fp
240 *  structure will not be used or it simply consist of an array of a
241 *  fixed number of bytes.   This is done when the floating point context
242 *  is dumped by a "FP save context" type instruction and the format
243 *  is not really defined by the CPU.  In this case, there is no need
244 *  to figure out the exact format -- only the size.  Of course, although
245 *  this is enough information for RTEMS, it is probably not enough for
246 *  a debugger such as gdb.  But that is another problem.
247 */
248
249#ifndef ASM
250
251/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
252#if (__mips == 1) || (__mips == 32)
253#define __MIPS_REGISTER_TYPE     uint32_t
254#define __MIPS_FPU_REGISTER_TYPE uint32_t
255#elif __mips == 3
256#define __MIPS_REGISTER_TYPE     uint64_t
257#define __MIPS_FPU_REGISTER_TYPE uint64_t
258#else
259#error "mips register size: unknown architecture level!!"
260#endif
261typedef struct {
262    __MIPS_REGISTER_TYPE s0;
263    __MIPS_REGISTER_TYPE s1;
264    __MIPS_REGISTER_TYPE s2;
265    __MIPS_REGISTER_TYPE s3;
266    __MIPS_REGISTER_TYPE s4;
267    __MIPS_REGISTER_TYPE s5;
268    __MIPS_REGISTER_TYPE s6;
269    __MIPS_REGISTER_TYPE s7;
270    __MIPS_REGISTER_TYPE sp;
271    __MIPS_REGISTER_TYPE fp;
272    __MIPS_REGISTER_TYPE ra;
273    __MIPS_REGISTER_TYPE c0_sr;
274    __MIPS_REGISTER_TYPE c0_epc;
275} Context_Control;
276
277#define _CPU_Context_Get_SP( _context ) \
278  (uintptr_t) (_context)->sp
279
280/* WARNING: If this structure is modified, the constants in cpu.h
281 *          must also be updated.
282 */
283
284typedef struct {
285#if ( CPU_HARDWARE_FP == TRUE )
286    __MIPS_FPU_REGISTER_TYPE fp0;
287    __MIPS_FPU_REGISTER_TYPE fp1;
288    __MIPS_FPU_REGISTER_TYPE fp2;
289    __MIPS_FPU_REGISTER_TYPE fp3;
290    __MIPS_FPU_REGISTER_TYPE fp4;
291    __MIPS_FPU_REGISTER_TYPE fp5;
292    __MIPS_FPU_REGISTER_TYPE fp6;
293    __MIPS_FPU_REGISTER_TYPE fp7;
294    __MIPS_FPU_REGISTER_TYPE fp8;
295    __MIPS_FPU_REGISTER_TYPE fp9;
296    __MIPS_FPU_REGISTER_TYPE fp10;
297    __MIPS_FPU_REGISTER_TYPE fp11;
298    __MIPS_FPU_REGISTER_TYPE fp12;
299    __MIPS_FPU_REGISTER_TYPE fp13;
300    __MIPS_FPU_REGISTER_TYPE fp14;
301    __MIPS_FPU_REGISTER_TYPE fp15;
302    __MIPS_FPU_REGISTER_TYPE fp16;
303    __MIPS_FPU_REGISTER_TYPE fp17;
304    __MIPS_FPU_REGISTER_TYPE fp18;
305    __MIPS_FPU_REGISTER_TYPE fp19;
306    __MIPS_FPU_REGISTER_TYPE fp20;
307    __MIPS_FPU_REGISTER_TYPE fp21;
308    __MIPS_FPU_REGISTER_TYPE fp22;
309    __MIPS_FPU_REGISTER_TYPE fp23;
310    __MIPS_FPU_REGISTER_TYPE fp24;
311    __MIPS_FPU_REGISTER_TYPE fp25;
312    __MIPS_FPU_REGISTER_TYPE fp26;
313    __MIPS_FPU_REGISTER_TYPE fp27;
314    __MIPS_FPU_REGISTER_TYPE fp28;
315    __MIPS_FPU_REGISTER_TYPE fp29;
316    __MIPS_FPU_REGISTER_TYPE fp30;
317    __MIPS_FPU_REGISTER_TYPE fp31;
318    uint32_t fpcs;
319#endif
320} Context_Control_fp;
321
322/*
323 *  This struct reflects the stack frame employed in ISR_Handler.  Note
324 *  that the ISR routine save some of the registers to this frame for
325 *  all interrupts and exceptions.  Other registers are saved only on
326 *  exceptions, while others are not touched at all.  The untouched
327 *  registers are not normally disturbed by high-level language
328 *  programs so they can be accessed when required.
329 *
330 *  The registers and their ordering in this struct must directly
331 *  correspond to the layout and ordering of * shown in iregdef.h,
332 *  as cpu_asm.S uses those definitions to fill the stack frame.
333 *  This struct provides access to the stack frame for C code.
334 *
335 *  Similarly, this structure is used by debugger stubs and exception
336 *  processing routines so be careful when changing the format.
337 *
338 *  NOTE: The comments with this structure and cpu_asm.S should be kept
339 *        in sync.  When in doubt, look in the  code to see if the
340 *        registers you're interested in are actually treated as expected.
341 *        The order of the first portion of this structure follows the
342 *        order of registers expected by gdb.
343 */
344
345typedef struct
346{
347  __MIPS_REGISTER_TYPE  r0;       /*  0 -- NOT FILLED IN */
348  __MIPS_REGISTER_TYPE  at;       /*  1 -- saved always */
349  __MIPS_REGISTER_TYPE  v0;       /*  2 -- saved always */
350  __MIPS_REGISTER_TYPE  v1;       /*  3 -- saved always */
351  __MIPS_REGISTER_TYPE  a0;       /*  4 -- saved always */
352  __MIPS_REGISTER_TYPE  a1;       /*  5 -- saved always */
353  __MIPS_REGISTER_TYPE  a2;       /*  6 -- saved always */
354  __MIPS_REGISTER_TYPE  a3;       /*  7 -- saved always */
355  __MIPS_REGISTER_TYPE  t0;       /*  8 -- saved always */
356  __MIPS_REGISTER_TYPE  t1;       /*  9 -- saved always */
357  __MIPS_REGISTER_TYPE  t2;       /* 10 -- saved always */
358  __MIPS_REGISTER_TYPE  t3;       /* 11 -- saved always */
359  __MIPS_REGISTER_TYPE  t4;       /* 12 -- saved always */
360  __MIPS_REGISTER_TYPE  t5;       /* 13 -- saved always */
361  __MIPS_REGISTER_TYPE  t6;       /* 14 -- saved always */
362  __MIPS_REGISTER_TYPE  t7;       /* 15 -- saved always */
363  __MIPS_REGISTER_TYPE  s0;       /* 16 -- saved on exceptions */
364  __MIPS_REGISTER_TYPE  s1;       /* 17 -- saved on exceptions */
365  __MIPS_REGISTER_TYPE  s2;       /* 18 -- saved on exceptions */
366  __MIPS_REGISTER_TYPE  s3;       /* 19 -- saved on exceptions */
367  __MIPS_REGISTER_TYPE  s4;       /* 20 -- saved on exceptions */
368  __MIPS_REGISTER_TYPE  s5;       /* 21 -- saved on exceptions */
369  __MIPS_REGISTER_TYPE  s6;       /* 22 -- saved on exceptions */
370  __MIPS_REGISTER_TYPE  s7;       /* 23 -- saved on exceptions */
371  __MIPS_REGISTER_TYPE  t8;       /* 24 -- saved always */
372  __MIPS_REGISTER_TYPE  t9;       /* 25 -- saved always */
373  __MIPS_REGISTER_TYPE  k0;       /* 26 -- NOT FILLED IN, kernel tmp reg */
374  __MIPS_REGISTER_TYPE  k1;       /* 27 -- NOT FILLED IN, kernel tmp reg */
375  __MIPS_REGISTER_TYPE  gp;       /* 28 -- saved always */
376  __MIPS_REGISTER_TYPE  sp;       /* 29 -- saved on exceptions NOT RESTORED */
377  __MIPS_REGISTER_TYPE  fp;       /* 30 -- saved always */
378  __MIPS_REGISTER_TYPE  ra;       /* 31 -- saved always */
379  __MIPS_REGISTER_TYPE  c0_sr;    /* 32 -- saved always, some bits are */
380                                  /*    manipulated per-thread          */
381  __MIPS_REGISTER_TYPE  mdlo;     /* 33 -- saved always */
382  __MIPS_REGISTER_TYPE  mdhi;     /* 34 -- saved always */
383  __MIPS_REGISTER_TYPE  badvaddr; /* 35 -- saved on exceptions, read-only */
384  __MIPS_REGISTER_TYPE  cause;    /* 36 -- saved on exceptions NOT restored */
385  __MIPS_REGISTER_TYPE  epc;      /* 37 -- saved always, read-only register */
386                                  /*        but logically restored */
387  __MIPS_FPU_REGISTER_TYPE f0;    /* 38 -- saved if FP enabled */
388  __MIPS_FPU_REGISTER_TYPE f1;    /* 39 -- saved if FP enabled */
389  __MIPS_FPU_REGISTER_TYPE f2;    /* 40 -- saved if FP enabled */
390  __MIPS_FPU_REGISTER_TYPE f3;    /* 41 -- saved if FP enabled */
391  __MIPS_FPU_REGISTER_TYPE f4;    /* 42 -- saved if FP enabled */
392  __MIPS_FPU_REGISTER_TYPE f5;    /* 43 -- saved if FP enabled */
393  __MIPS_FPU_REGISTER_TYPE f6;    /* 44 -- saved if FP enabled */
394  __MIPS_FPU_REGISTER_TYPE f7;    /* 45 -- saved if FP enabled */
395  __MIPS_FPU_REGISTER_TYPE f8;    /* 46 -- saved if FP enabled */
396  __MIPS_FPU_REGISTER_TYPE f9;    /* 47 -- saved if FP enabled */
397  __MIPS_FPU_REGISTER_TYPE f10;   /* 48 -- saved if FP enabled */
398  __MIPS_FPU_REGISTER_TYPE f11;   /* 49 -- saved if FP enabled */
399  __MIPS_FPU_REGISTER_TYPE f12;   /* 50 -- saved if FP enabled */
400  __MIPS_FPU_REGISTER_TYPE f13;   /* 51 -- saved if FP enabled */
401  __MIPS_FPU_REGISTER_TYPE f14;   /* 52 -- saved if FP enabled */
402  __MIPS_FPU_REGISTER_TYPE f15;   /* 53 -- saved if FP enabled */
403  __MIPS_FPU_REGISTER_TYPE f16;   /* 54 -- saved if FP enabled */
404  __MIPS_FPU_REGISTER_TYPE f17;   /* 55 -- saved if FP enabled */
405  __MIPS_FPU_REGISTER_TYPE f18;   /* 56 -- saved if FP enabled */
406  __MIPS_FPU_REGISTER_TYPE f19;   /* 57 -- saved if FP enabled */
407  __MIPS_FPU_REGISTER_TYPE f20;   /* 58 -- saved if FP enabled */
408  __MIPS_FPU_REGISTER_TYPE f21;   /* 59 -- saved if FP enabled */
409  __MIPS_FPU_REGISTER_TYPE f22;   /* 60 -- saved if FP enabled */
410  __MIPS_FPU_REGISTER_TYPE f23;   /* 61 -- saved if FP enabled */
411  __MIPS_FPU_REGISTER_TYPE f24;   /* 62 -- saved if FP enabled */
412  __MIPS_FPU_REGISTER_TYPE f25;   /* 63 -- saved if FP enabled */
413  __MIPS_FPU_REGISTER_TYPE f26;   /* 64 -- saved if FP enabled */
414  __MIPS_FPU_REGISTER_TYPE f27;   /* 65 -- saved if FP enabled */
415  __MIPS_FPU_REGISTER_TYPE f28;   /* 66 -- saved if FP enabled */
416  __MIPS_FPU_REGISTER_TYPE f29;   /* 67 -- saved if FP enabled */
417  __MIPS_FPU_REGISTER_TYPE f30;   /* 68 -- saved if FP enabled */
418  __MIPS_FPU_REGISTER_TYPE f31;   /* 69 -- saved if FP enabled */
419  __MIPS_REGISTER_TYPE     fcsr;  /* 70 -- saved on exceptions */
420                                  /*    (oddly not documented on MGV) */
421  __MIPS_REGISTER_TYPE     feir;  /* 71 -- saved on exceptions */
422                                  /*    (oddly not documented on MGV) */
423
424  /* GDB does not seem to care about anything past this point */
425
426  __MIPS_REGISTER_TYPE  tlbhi;    /* 72 - NOT FILLED IN, doesn't exist on */
427                                  /*         all MIPS CPUs (at least MGV) */
428#if __mips == 1
429  __MIPS_REGISTER_TYPE  tlblo;    /* 73 - NOT FILLED IN, doesn't exist on */
430                                  /*         all MIPS CPUs (at least MGV) */
431#endif
432#if  (__mips == 3) || (__mips == 32)
433  __MIPS_REGISTER_TYPE  tlblo0;   /* 73 - NOT FILLED IN, doesn't exist on */
434                                  /*         all MIPS CPUs (at least MGV) */
435#endif
436
437  __MIPS_REGISTER_TYPE  inx;      /* 74 -- NOT FILLED IN, doesn't exist on */
438                                  /*         all MIPS CPUs (at least MGV) */
439  __MIPS_REGISTER_TYPE  rand;     /* 75 -- NOT FILLED IN, doesn't exist on */
440                                  /*         all MIPS CPUs (at least MGV) */
441  __MIPS_REGISTER_TYPE  ctxt;     /* 76 -- NOT FILLED IN, doesn't exist on */
442                                  /*         all MIPS CPUs (at least MGV) */
443  __MIPS_REGISTER_TYPE  exctype;  /* 77 -- NOT FILLED IN (not enough info) */
444  __MIPS_REGISTER_TYPE  mode;     /* 78 -- NOT FILLED IN (not enough info) */
445  __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
446  __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
447  /* end of __mips == 1 so NREGS == 81 */
448#if  (__mips == 3) || (__mips == 32)
449  __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
450  __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
451  __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
452  __MIPS_REGISTER_TYPE  count;    /* 84 -- NOT FILLED IN */
453  __MIPS_REGISTER_TYPE  compare;  /* 85 -- NOT FILLED IN */
454  __MIPS_REGISTER_TYPE  config;   /* 86 -- NOT FILLED IN */
455  __MIPS_REGISTER_TYPE  lladdr;   /* 87 -- NOT FILLED IN */
456  __MIPS_REGISTER_TYPE  watchlo;  /* 88 -- NOT FILLED IN */
457  __MIPS_REGISTER_TYPE  watchhi;  /* 89 -- NOT FILLED IN */
458  __MIPS_REGISTER_TYPE  ecc;      /* 90 -- NOT FILLED IN */
459  __MIPS_REGISTER_TYPE  cacheerr; /* 91 -- NOT FILLED IN */
460  __MIPS_REGISTER_TYPE  taglo;    /* 92 -- NOT FILLED IN */
461  __MIPS_REGISTER_TYPE  taghi;    /* 93 -- NOT FILLED IN */
462  __MIPS_REGISTER_TYPE  errpc;    /* 94 -- NOT FILLED IN */
463  __MIPS_REGISTER_TYPE  xctxt;    /* 95 -- NOT FILLED IN */
464 /* end of __mips == 3 so NREGS == 96 */
465#endif
466
467} CPU_Interrupt_frame;
468
469typedef CPU_Interrupt_frame CPU_Exception_frame;
470
471/*
472 *  This variable is optional.  It is used on CPUs on which it is difficult
473 *  to generate an "uninitialized" FP context.  It is filled in by
474 *  _CPU_Initialize and copied into the task's FP context area during
475 *  _CPU_Context_Initialize.
476 */
477
478extern Context_Control_fp _CPU_Null_fp_context;
479
480/*
481 *  Nothing prevents the porter from declaring more CPU specific variables.
482 */
483
484/* XXX: if needed, put more variables here */
485
486/*
487 *  The size of the floating point context area.  On some CPUs this
488 *  will not be a "sizeof" because the format of the floating point
489 *  area is not defined -- only the size is.  This is usually on
490 *  CPUs with a "floating point save context" instruction.
491 */
492
493#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
494
495/*
496 *  Amount of extra stack (above minimum stack size) required by
497 *  system initialization thread.  Remember that in a multiprocessor
498 *  system the system intialization thread becomes the MP server thread.
499 */
500
501#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
502
503/*
504 *  Should be large enough to run all RTEMS tests.  This ensures
505 *  that a "reasonable" small application should not have any problems.
506 */
507
508#define CPU_STACK_MINIMUM_SIZE          (8 * 1024)
509
510/*
511 *  CPU's worst alignment requirement for data types on a byte boundary.  This
512 *  alignment does not take into account the requirements for the stack.
513 */
514
515#define CPU_ALIGNMENT              8
516
517/*
518 *  This number corresponds to the byte alignment requirement for the
519 *  heap handler.  This alignment requirement may be stricter than that
520 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
521 *  common for the heap to follow the same alignment requirement as
522 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
523 *  then this should be set to CPU_ALIGNMENT.
524 *
525 *  NOTE:  This does not have to be a power of 2.  It does have to
526 *         be greater or equal to than CPU_ALIGNMENT.
527 */
528
529#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
530
531/*
532 *  This number corresponds to the byte alignment requirement for the
533 *  stack.  This alignment requirement may be stricter than that for the
534 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
535 *  is strict enough for the stack, then this should be set to 0.
536 *
537 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
538 */
539
540#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
541
542#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
543
544void mips_vector_exceptions( CPU_Interrupt_frame *frame );
545
546/*
547 *  ISR handler macros
548 */
549
550/*
551 *  Declare the function that is present in the shared libcpu directory,
552 *  that returns the processor dependent interrupt mask.
553 */
554
555uint32_t mips_interrupt_mask( void );
556
557/*
558 *  Disable all interrupts for an RTEMS critical section.  The previous
559 *  level is returned in _level.
560 */
561
562#define _CPU_ISR_Disable( _level ) \
563  do { \
564    unsigned int _scratch; \
565    mips_get_sr( _scratch ); \
566    mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
567    _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
568  } while(0)
569
570/*
571 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
572 *  This indicates the end of an RTEMS critical section.  The parameter
573 *  _level is not modified.
574 */
575
576#define _CPU_ISR_Enable( _level )  \
577  do { \
578    unsigned int _scratch; \
579    mips_get_sr( _scratch ); \
580    mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
581  } while(0)
582
583/*
584 *  This temporarily restores the interrupt to _level before immediately
585 *  disabling them again.  This is used to divide long RTEMS critical
586 *  sections into two or more parts.  The parameter _level is not
587 *  modified.
588 */
589
590#define _CPU_ISR_Flash( _xlevel ) \
591  do { \
592    unsigned int _scratch2 = _xlevel; \
593    _CPU_ISR_Enable( _scratch2 ); \
594    _CPU_ISR_Disable( _scratch2 ); \
595    _xlevel = _scratch2; \
596  } while(0)
597
598RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
599{
600  return ( level & SR_INTERRUPT_ENABLE_BITS ) != 0;
601}
602
603/*
604 *  Map interrupt level in task mode onto the hardware that the CPU
605 *  actually provides.  Currently, interrupt levels which do not
606 *  map onto the CPU in a generic fashion are undefined.  Someday,
607 *  it would be nice if these were "mapped" by the application
608 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
609 *  8 - 255 would be available for bsp/application specific meaning.
610 *  This could be used to manage a programmable interrupt controller
611 *  via the rtems_task_mode directive.
612 *
613 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
614 *  manipulates the IEC.
615 */
616
617uint32_t   _CPU_ISR_Get_level( void );  /* in cpu.c */
618
619void _CPU_ISR_Set_level( uint32_t   );  /* in cpu.c */
620
621/* end of ISR handler macros */
622
623/* Context handler macros */
624
625/*
626 *  Initialize the context to a state suitable for starting a
627 *  task after a context restore operation.  Generally, this
628 *  involves:
629 *
630 *     - setting a starting address
631 *     - preparing the stack
632 *     - preparing the stack and frame pointers
633 *     - setting the proper interrupt level in the context
634 *     - initializing the floating point context
635 *
636 *  This routine generally does not set any unnecessary register
637 *  in the context.  The state of the "general data" registers is
638 *  undefined at task start time.
639 *
640 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
641 *        point thread.  This is typically only used on CPUs where the
642 *        FPU may be easily disabled by software such as on the SPARC
643 *        where the PSR contains an enable FPU bit.
644 *
645 *  The per-thread status register holds the interrupt enable, FP enable
646 *  and global interrupt enable for that thread.  It means each thread can
647 *  enable its own set of interrupts.  If interrupts are disabled, RTEMS
648 *  can still dispatch via blocking calls.  This is the function of the
649 *  "Interrupt Level", and on the MIPS, it controls the IEC bit and all
650 *  the hardware interrupts as defined in the SR.  Software ints
651 *  are automatically enabled for all threads, as they will only occur under
652 *  program control anyhow.  Besides, the interrupt level parm is only 8 bits,
653 *  and controlling the software ints plus the others would require 9.
654 *
655 *  If the Interrupt Level is 0, all ints are on.  Otherwise, the
656 *  Interrupt Level should supply a bit pattern to impose on the SR
657 *  interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6
658 *  apply to the SR register Intr bits from bit 10 thru bit 15.  Bit 7 of
659 *  the Interrupt Level parameter is unused at this time.
660 *
661 *  These are the only per-thread SR bits, the others are maintained
662 *  globally & explicitly preserved by the Context Switch code in cpu_asm.s
663 */
664
665
666#if (__mips == 3) || (__mips == 32)
667#define _INTON          SR_IE
668#if __mips_fpr==64
669#define _EXTRABITS      SR_FR
670#else
671#define _EXTRABITS      0
672#endif /* __mips_fpr==64 */
673#endif /* __mips == 3 */
674#if __mips == 1
675#define _INTON          SR_IEC
676#define _EXTRABITS      0  /* make sure we're in user mode on MIPS1 processors */
677#endif /* __mips == 1 */
678
679
680void _CPU_Context_Initialize(
681  Context_Control  *the_context,
682  uintptr_t        *stack_base,
683  uint32_t          size,
684  uint32_t          new_level,
685  void             *entry_point,
686  bool              is_fp,
687  void             *tls_area
688);
689
690
691/*
692 *  This routine is responsible for somehow restarting the currently
693 *  executing task.  If you are lucky, then all that is necessary
694 *  is restoring the context.  Otherwise, there will need to be
695 *  a special assembly routine which does something special in this
696 *  case.  Context_Restore should work most of the time.  It will
697 *  not work if restarting self conflicts with the stack frame
698 *  assumptions of restoring a context.
699 */
700
701#define _CPU_Context_Restart_self( _the_context ) \
702   _CPU_Context_restore( (_the_context) );
703
704/*
705 *  This routine initializes the FP context area passed to it to.
706 *  There are a few standard ways in which to initialize the
707 *  floating point context.  The code included for this macro assumes
708 *  that this is a CPU in which a "initial" FP context was saved into
709 *  _CPU_Null_fp_context and it simply copies it to the destination
710 *  context passed to it.
711 *
712 *  Other models include (1) not doing anything, and (2) putting
713 *  a "null FP status word" in the correct place in the FP context.
714 */
715
716#if ( CPU_HARDWARE_FP == TRUE )
717#define _CPU_Context_Initialize_fp( _destination ) \
718  { \
719   *(*(_destination)) = _CPU_Null_fp_context; \
720  }
721#endif
722
723/* end of Context handler macros */
724
725/* Fatal Error manager macros */
726
727/*
728 *  This routine copies _error into a known place -- typically a stack
729 *  location or a register, optionally disables interrupts, and
730 *  halts/stops the CPU.
731 */
732
733#define _CPU_Fatal_halt( _source, _error ) \
734  do { \
735    unsigned int _level; \
736    _CPU_ISR_Disable(_level); \
737    (void)_level; \
738    loop: goto loop; \
739  } while (0)
740
741
742extern void mips_break( int error );
743
744#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
745
746/* functions */
747
748/*
749 *  _CPU_Initialize
750 *
751 *  This routine performs CPU dependent initialization.
752 */
753
754void _CPU_Initialize(void);
755
756void *_CPU_Thread_Idle_body( uintptr_t ignored );
757
758/*
759 *  _CPU_Context_switch
760 *
761 *  This routine switches from the run context to the heir context.
762 */
763
764void _CPU_Context_switch(
765  Context_Control  *run,
766  Context_Control  *heir
767);
768
769/*
770 *  _CPU_Context_restore
771 *
772 *  This routine is generally used only to restart self in an
773 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
774 *
775 *  NOTE: May be unnecessary to reload some registers.
776 */
777
778void _CPU_Context_restore(
779  Context_Control *new_context
780) RTEMS_NO_RETURN;
781
782/*
783 *  _CPU_Context_save_fp
784 *
785 *  This routine saves the floating point context passed to it.
786 */
787
788void _CPU_Context_save_fp(
789  Context_Control_fp **fp_context_ptr
790);
791
792/*
793 *  _CPU_Context_restore_fp
794 *
795 *  This routine restores the floating point context passed to it.
796 */
797
798void _CPU_Context_restore_fp(
799  Context_Control_fp **fp_context_ptr
800);
801
802void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
803
804/*  The following routine swaps the endian format of an unsigned int.
805 *  It must be static because it is referenced indirectly.
806 *
807 *  This version will work on any processor, but if there is a better
808 *  way for your CPU PLEASE use it.  The most common way to do this is to:
809 *
810 *     swap least significant two bytes with 16-bit rotate
811 *     swap upper and lower 16-bits
812 *     swap most significant two bytes with 16-bit rotate
813 *
814 *  Some CPUs have special instructions which swap a 32-bit quantity in
815 *  a single instruction (e.g. i486).  It is probably best to avoid
816 *  an "endian swapping control bit" in the CPU.  One good reason is
817 *  that interrupts would probably have to be disabled to ensure that
818 *  an interrupt does not try to access the same "chunk" with the wrong
819 *  endian.  Another good reason is that on some CPUs, the endian bit
820 *  endianness for ALL fetches -- both code and data -- so the code
821 *  will be fetched incorrectly.
822 */
823
824static inline uint32_t CPU_swap_u32(
825  uint32_t value
826)
827{
828  uint32_t   byte1, byte2, byte3, byte4, swapped;
829
830  byte4 = (value >> 24) & 0xff;
831  byte3 = (value >> 16) & 0xff;
832  byte2 = (value >> 8)  & 0xff;
833  byte1 =  value        & 0xff;
834
835  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
836  return( swapped );
837}
838
839#define CPU_swap_u16( value ) \
840  (((value&0xff) << 8) | ((value >> 8)&0xff))
841
842typedef uint32_t CPU_Counter_ticks;
843
844uint32_t _CPU_Counter_frequency( void );
845
846CPU_Counter_ticks _CPU_Counter_read( void );
847
848static inline CPU_Counter_ticks _CPU_Counter_difference(
849  CPU_Counter_ticks second,
850  CPU_Counter_ticks first
851)
852{
853  return second - first;
854}
855
856/** Type that can store a 32-bit integer or a pointer. */
857typedef uintptr_t CPU_Uint32ptr;
858
859#endif
860
861#ifdef __cplusplus
862}
863#endif
864
865/**@}*/
866#endif
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