source: rtems/cpukit/score/cpu/mips/include/rtems/score/cpu.h @ 27bbc05

Last change on this file since 27bbc05 was 27bbc05, checked in by Sebastian Huber <sebastian.huber@…>, on Aug 2, 2018 at 12:49:01 PM

score: Remove CPU_PARTITION_ALIGNMENT

Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment
requirement is defined by the use of Chain_Node (consisting of two
pointers) to manage the free chain of partitions.

It seems that previously the condition

CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node)

was true on all CPU ports. Now, we need an additional check.

Update #3482.

  • Property mode set to 100644
File size: 32.1 KB
Line 
1/**
2 *  @file
3 *
4 *  @brief Mips CPU Dependent Header File
5 */
6
7/*
8 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
9 *           Joel Sherrill <joel@OARcorp.com>.
10 *
11 *    These changes made the code conditional on standard cpp predefines,
12 *    merged the mips1 and mips3 code sequences as much as possible,
13 *    and moved some of the assembly code to C.  Alan did much of the
14 *    initial analysis and rework.  Joel took over from there and
15 *    wrote the JMR3904 BSP so this could be tested.  Joel also
16 *    added the new interrupt vectoring support in libcpu and
17 *    tried to better support the various interrupt controllers.
18 *
19 */
20
21/*
22 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
23 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
24 *
25 *    To anyone who acknowledges that this file is provided "AS IS"
26 *    without any express or implied warranty:
27 *      permission to use, copy, modify, and distribute this file
28 *      for any purpose is hereby granted without fee, provided that
29 *      the above copyright notice and this notice appears in all
30 *      copies, and that the name of Transition Networks not be used in
31 *      advertising or publicity pertaining to distribution of the
32 *      software without specific, written prior permission.
33 *      Transition Networks makes no representations about the suitability
34 *      of this software for any purpose.
35 *
36 *  COPYRIGHT (c) 1989-2012.
37 *  On-Line Applications Research Corporation (OAR).
38 *
39 *  The license and distribution terms for this file may be
40 *  found in the file LICENSE in this distribution or at
41 *  http://www.rtems.org/license/LICENSE.
42 */
43
44#ifndef _RTEMS_SCORE_CPU_H
45#define _RTEMS_SCORE_CPU_H
46
47/**
48 *  @defgroup ScoreCPU CPU CPU
49 *
50 *  @ingroup Score
51 *
52 */
53/**@{*/
54
55#ifdef __cplusplus
56extern "C" {
57#endif
58
59#include <rtems/score/basedefs.h>
60#include <rtems/score/mips.h>
61
62/* conditional compilation parameters */
63
64/*
65 *  Does the CPU follow the simple vectored interrupt model?
66 *
67 *  If TRUE, then RTEMS allocates the vector table it internally manages.
68 *  If FALSE, then the BSP is assumed to allocate and manage the vector
69 *  table
70 *
71 *  MIPS Specific Information:
72 *
73 *  Up to and including RTEMS 4.10, the MIPS port used simple vectored
74 *  interrupts. But this was changed to the PIC model after 4.10.
75 */
76#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
77
78/*
79 *  Does the RTEMS invoke the user's ISR with the vector number and
80 *  a pointer to the saved interrupt frame (1) or just the vector
81 *  number (0)?
82 *
83 */
84
85#define CPU_ISR_PASSES_FRAME_POINTER TRUE
86
87
88
89/*
90 *  Does the CPU have hardware floating point?
91 *
92 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
93 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
94 *
95 *  If there is a FP coprocessor such as the i387 or mc68881, then
96 *  the answer is TRUE.
97 *
98 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
99 *  It indicates whether or not this CPU model has FP support.  For
100 *  example, it would be possible to have an i386_nofp CPU model
101 *  which set this to false to indicate that you have an i386 without
102 *  an i387 and wish to leave floating point support out of RTEMS.
103 */
104
105#if ( MIPS_HAS_FPU == 1 )
106#define CPU_HARDWARE_FP     TRUE
107#else
108#define CPU_HARDWARE_FP     FALSE
109#endif
110
111/*
112 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
113 *
114 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
115 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
116 *
117 *  So far, the only CPU in which this option has been used is the
118 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
119 *  floating point registers to perform integer multiplies.  If
120 *  a function which you would not think utilize the FP unit DOES,
121 *  then one can not easily predict which tasks will use the FP hardware.
122 *  In this case, this option should be TRUE.
123 *
124 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
125 *
126 *  Mips Note: It appears the GCC can implicitly generate FPU
127 *  and Altivec instructions when you least expect them.  So make
128 *  all tasks floating point.
129 */
130
131#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
132
133/*
134 *  Should the IDLE task have a floating point context?
135 *
136 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
137 *  and it has a floating point context which is switched in and out.
138 *  If FALSE, then the IDLE task does not have a floating point context.
139 *
140 *  Setting this to TRUE negatively impacts the time required to preempt
141 *  the IDLE task from an interrupt because the floating point context
142 *  must be saved as part of the preemption.
143 */
144
145#define CPU_IDLE_TASK_IS_FP      FALSE
146
147/*
148 *  Should the saving of the floating point registers be deferred
149 *  until a context switch is made to another different floating point
150 *  task?
151 *
152 *  If TRUE, then the floating point context will not be stored until
153 *  necessary.  It will remain in the floating point registers and not
154 *  disturned until another floating point task is switched to.
155 *
156 *  If FALSE, then the floating point context is saved when a floating
157 *  point task is switched out and restored when the next floating point
158 *  task is restored.  The state of the floating point registers between
159 *  those two operations is not specified.
160 *
161 *  If the floating point context does NOT have to be saved as part of
162 *  interrupt dispatching, then it should be safe to set this to TRUE.
163 *
164 *  Setting this flag to TRUE results in using a different algorithm
165 *  for deciding when to save and restore the floating point context.
166 *  The deferred FP switch algorithm minimizes the number of times
167 *  the FP context is saved and restored.  The FP context is not saved
168 *  until a context switch is made to another, different FP task.
169 *  Thus in a system with only one FP task, the FP context will never
170 *  be saved or restored.
171 */
172
173#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
174
175#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
176
177/*
178 *  Does this port provide a CPU dependent IDLE task implementation?
179 *
180 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
181 *  must be provided and is the default IDLE thread body instead of
182 *  _Internal_threads_Idle_thread_body.
183 *
184 *  If FALSE, then use the generic IDLE thread body if the BSP does
185 *  not provide one.
186 *
187 *  This is intended to allow for supporting processors which have
188 *  a low power or idle mode.  When the IDLE thread is executed, then
189 *  the CPU can be powered down.
190 *
191 *  The order of precedence for selecting the IDLE thread body is:
192 *
193 *    1.  BSP provided
194 *    2.  CPU dependent (if provided)
195 *    3.  generic (if no BSP and no CPU dependent)
196 */
197
198/* we can use the low power wait instruction for the IDLE thread */
199#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
200
201/*
202 *  Does the stack grow up (toward higher addresses) or down
203 *  (toward lower addresses)?
204 *
205 *  If TRUE, then the grows upward.
206 *  If FALSE, then the grows toward smaller addresses.
207 */
208
209/* our stack grows down */
210#define CPU_STACK_GROWS_UP               FALSE
211
212/* FIXME: Is this the right value? */
213#define CPU_CACHE_LINE_BYTES 16
214
215#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
216
217/*
218 *  The following defines the number of bits actually used in the
219 *  interrupt field of the task mode.  How those bits map to the
220 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
221 */
222
223#define CPU_MODES_INTERRUPT_MASK   0x000000ff
224
225#define CPU_SIZEOF_POINTER 4
226
227#define CPU_MAXIMUM_PROCESSORS 32
228
229/*
230 *  Processor defined structures
231 *
232 *  Examples structures include the descriptor tables from the i386
233 *  and the processor control structure on the i960ca.
234 */
235
236/* may need to put some structures here.  */
237
238/*
239 * Contexts
240 *
241 *  Generally there are 2 types of context to save.
242 *     1. Interrupt registers to save
243 *     2. Task level registers to save
244 *
245 *  This means we have the following 3 context items:
246 *     1. task level context stuff::  Context_Control
247 *     2. floating point task stuff:: Context_Control_fp
248 *     3. special interrupt level context :: Context_Control_interrupt
249 *
250 *  On some processors, it is cost-effective to save only the callee
251 *  preserved registers during a task context switch.  This means
252 *  that the ISR code needs to save those registers which do not
253 *  persist across function calls.  It is not mandatory to make this
254 *  distinctions between the caller/callee saves registers for the
255 *  purpose of minimizing context saved during task switch and on interrupts.
256 *  If the cost of saving extra registers is minimal, simplicity is the
257 *  choice.  Save the same context on interrupt entry as for tasks in
258 *  this case.
259 *
260 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
261 *  care should be used in designing the context area.
262 *
263 *  On some CPUs with hardware floating point support, the Context_Control_fp
264 *  structure will not be used or it simply consist of an array of a
265 *  fixed number of bytes.   This is done when the floating point context
266 *  is dumped by a "FP save context" type instruction and the format
267 *  is not really defined by the CPU.  In this case, there is no need
268 *  to figure out the exact format -- only the size.  Of course, although
269 *  this is enough information for RTEMS, it is probably not enough for
270 *  a debugger such as gdb.  But that is another problem.
271 */
272
273#ifndef ASM
274
275/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
276#if (__mips == 1) || (__mips == 32)
277#define __MIPS_REGISTER_TYPE     uint32_t
278#define __MIPS_FPU_REGISTER_TYPE uint32_t
279#elif __mips == 3
280#define __MIPS_REGISTER_TYPE     uint64_t
281#define __MIPS_FPU_REGISTER_TYPE uint64_t
282#else
283#error "mips register size: unknown architecture level!!"
284#endif
285typedef struct {
286    __MIPS_REGISTER_TYPE s0;
287    __MIPS_REGISTER_TYPE s1;
288    __MIPS_REGISTER_TYPE s2;
289    __MIPS_REGISTER_TYPE s3;
290    __MIPS_REGISTER_TYPE s4;
291    __MIPS_REGISTER_TYPE s5;
292    __MIPS_REGISTER_TYPE s6;
293    __MIPS_REGISTER_TYPE s7;
294    __MIPS_REGISTER_TYPE sp;
295    __MIPS_REGISTER_TYPE fp;
296    __MIPS_REGISTER_TYPE ra;
297    __MIPS_REGISTER_TYPE c0_sr;
298    __MIPS_REGISTER_TYPE c0_epc;
299} Context_Control;
300
301#define _CPU_Context_Get_SP( _context ) \
302  (uintptr_t) (_context)->sp
303
304/* WARNING: If this structure is modified, the constants in cpu.h
305 *          must also be updated.
306 */
307
308typedef struct {
309#if ( CPU_HARDWARE_FP == TRUE )
310    __MIPS_FPU_REGISTER_TYPE fp0;
311    __MIPS_FPU_REGISTER_TYPE fp1;
312    __MIPS_FPU_REGISTER_TYPE fp2;
313    __MIPS_FPU_REGISTER_TYPE fp3;
314    __MIPS_FPU_REGISTER_TYPE fp4;
315    __MIPS_FPU_REGISTER_TYPE fp5;
316    __MIPS_FPU_REGISTER_TYPE fp6;
317    __MIPS_FPU_REGISTER_TYPE fp7;
318    __MIPS_FPU_REGISTER_TYPE fp8;
319    __MIPS_FPU_REGISTER_TYPE fp9;
320    __MIPS_FPU_REGISTER_TYPE fp10;
321    __MIPS_FPU_REGISTER_TYPE fp11;
322    __MIPS_FPU_REGISTER_TYPE fp12;
323    __MIPS_FPU_REGISTER_TYPE fp13;
324    __MIPS_FPU_REGISTER_TYPE fp14;
325    __MIPS_FPU_REGISTER_TYPE fp15;
326    __MIPS_FPU_REGISTER_TYPE fp16;
327    __MIPS_FPU_REGISTER_TYPE fp17;
328    __MIPS_FPU_REGISTER_TYPE fp18;
329    __MIPS_FPU_REGISTER_TYPE fp19;
330    __MIPS_FPU_REGISTER_TYPE fp20;
331    __MIPS_FPU_REGISTER_TYPE fp21;
332    __MIPS_FPU_REGISTER_TYPE fp22;
333    __MIPS_FPU_REGISTER_TYPE fp23;
334    __MIPS_FPU_REGISTER_TYPE fp24;
335    __MIPS_FPU_REGISTER_TYPE fp25;
336    __MIPS_FPU_REGISTER_TYPE fp26;
337    __MIPS_FPU_REGISTER_TYPE fp27;
338    __MIPS_FPU_REGISTER_TYPE fp28;
339    __MIPS_FPU_REGISTER_TYPE fp29;
340    __MIPS_FPU_REGISTER_TYPE fp30;
341    __MIPS_FPU_REGISTER_TYPE fp31;
342    uint32_t fpcs;
343#endif
344} Context_Control_fp;
345
346/*
347 *  This struct reflects the stack frame employed in ISR_Handler.  Note
348 *  that the ISR routine save some of the registers to this frame for
349 *  all interrupts and exceptions.  Other registers are saved only on
350 *  exceptions, while others are not touched at all.  The untouched
351 *  registers are not normally disturbed by high-level language
352 *  programs so they can be accessed when required.
353 *
354 *  The registers and their ordering in this struct must directly
355 *  correspond to the layout and ordering of * shown in iregdef.h,
356 *  as cpu_asm.S uses those definitions to fill the stack frame.
357 *  This struct provides access to the stack frame for C code.
358 *
359 *  Similarly, this structure is used by debugger stubs and exception
360 *  processing routines so be careful when changing the format.
361 *
362 *  NOTE: The comments with this structure and cpu_asm.S should be kept
363 *        in sync.  When in doubt, look in the  code to see if the
364 *        registers you're interested in are actually treated as expected.
365 *        The order of the first portion of this structure follows the
366 *        order of registers expected by gdb.
367 */
368
369typedef struct
370{
371  __MIPS_REGISTER_TYPE  r0;       /*  0 -- NOT FILLED IN */
372  __MIPS_REGISTER_TYPE  at;       /*  1 -- saved always */
373  __MIPS_REGISTER_TYPE  v0;       /*  2 -- saved always */
374  __MIPS_REGISTER_TYPE  v1;       /*  3 -- saved always */
375  __MIPS_REGISTER_TYPE  a0;       /*  4 -- saved always */
376  __MIPS_REGISTER_TYPE  a1;       /*  5 -- saved always */
377  __MIPS_REGISTER_TYPE  a2;       /*  6 -- saved always */
378  __MIPS_REGISTER_TYPE  a3;       /*  7 -- saved always */
379  __MIPS_REGISTER_TYPE  t0;       /*  8 -- saved always */
380  __MIPS_REGISTER_TYPE  t1;       /*  9 -- saved always */
381  __MIPS_REGISTER_TYPE  t2;       /* 10 -- saved always */
382  __MIPS_REGISTER_TYPE  t3;       /* 11 -- saved always */
383  __MIPS_REGISTER_TYPE  t4;       /* 12 -- saved always */
384  __MIPS_REGISTER_TYPE  t5;       /* 13 -- saved always */
385  __MIPS_REGISTER_TYPE  t6;       /* 14 -- saved always */
386  __MIPS_REGISTER_TYPE  t7;       /* 15 -- saved always */
387  __MIPS_REGISTER_TYPE  s0;       /* 16 -- saved on exceptions */
388  __MIPS_REGISTER_TYPE  s1;       /* 17 -- saved on exceptions */
389  __MIPS_REGISTER_TYPE  s2;       /* 18 -- saved on exceptions */
390  __MIPS_REGISTER_TYPE  s3;       /* 19 -- saved on exceptions */
391  __MIPS_REGISTER_TYPE  s4;       /* 20 -- saved on exceptions */
392  __MIPS_REGISTER_TYPE  s5;       /* 21 -- saved on exceptions */
393  __MIPS_REGISTER_TYPE  s6;       /* 22 -- saved on exceptions */
394  __MIPS_REGISTER_TYPE  s7;       /* 23 -- saved on exceptions */
395  __MIPS_REGISTER_TYPE  t8;       /* 24 -- saved always */
396  __MIPS_REGISTER_TYPE  t9;       /* 25 -- saved always */
397  __MIPS_REGISTER_TYPE  k0;       /* 26 -- NOT FILLED IN, kernel tmp reg */
398  __MIPS_REGISTER_TYPE  k1;       /* 27 -- NOT FILLED IN, kernel tmp reg */
399  __MIPS_REGISTER_TYPE  gp;       /* 28 -- saved always */
400  __MIPS_REGISTER_TYPE  sp;       /* 29 -- saved on exceptions NOT RESTORED */
401  __MIPS_REGISTER_TYPE  fp;       /* 30 -- saved always */
402  __MIPS_REGISTER_TYPE  ra;       /* 31 -- saved always */
403  __MIPS_REGISTER_TYPE  c0_sr;    /* 32 -- saved always, some bits are */
404                                  /*    manipulated per-thread          */
405  __MIPS_REGISTER_TYPE  mdlo;     /* 33 -- saved always */
406  __MIPS_REGISTER_TYPE  mdhi;     /* 34 -- saved always */
407  __MIPS_REGISTER_TYPE  badvaddr; /* 35 -- saved on exceptions, read-only */
408  __MIPS_REGISTER_TYPE  cause;    /* 36 -- saved on exceptions NOT restored */
409  __MIPS_REGISTER_TYPE  epc;      /* 37 -- saved always, read-only register */
410                                  /*        but logically restored */
411  __MIPS_FPU_REGISTER_TYPE f0;    /* 38 -- saved if FP enabled */
412  __MIPS_FPU_REGISTER_TYPE f1;    /* 39 -- saved if FP enabled */
413  __MIPS_FPU_REGISTER_TYPE f2;    /* 40 -- saved if FP enabled */
414  __MIPS_FPU_REGISTER_TYPE f3;    /* 41 -- saved if FP enabled */
415  __MIPS_FPU_REGISTER_TYPE f4;    /* 42 -- saved if FP enabled */
416  __MIPS_FPU_REGISTER_TYPE f5;    /* 43 -- saved if FP enabled */
417  __MIPS_FPU_REGISTER_TYPE f6;    /* 44 -- saved if FP enabled */
418  __MIPS_FPU_REGISTER_TYPE f7;    /* 45 -- saved if FP enabled */
419  __MIPS_FPU_REGISTER_TYPE f8;    /* 46 -- saved if FP enabled */
420  __MIPS_FPU_REGISTER_TYPE f9;    /* 47 -- saved if FP enabled */
421  __MIPS_FPU_REGISTER_TYPE f10;   /* 48 -- saved if FP enabled */
422  __MIPS_FPU_REGISTER_TYPE f11;   /* 49 -- saved if FP enabled */
423  __MIPS_FPU_REGISTER_TYPE f12;   /* 50 -- saved if FP enabled */
424  __MIPS_FPU_REGISTER_TYPE f13;   /* 51 -- saved if FP enabled */
425  __MIPS_FPU_REGISTER_TYPE f14;   /* 52 -- saved if FP enabled */
426  __MIPS_FPU_REGISTER_TYPE f15;   /* 53 -- saved if FP enabled */
427  __MIPS_FPU_REGISTER_TYPE f16;   /* 54 -- saved if FP enabled */
428  __MIPS_FPU_REGISTER_TYPE f17;   /* 55 -- saved if FP enabled */
429  __MIPS_FPU_REGISTER_TYPE f18;   /* 56 -- saved if FP enabled */
430  __MIPS_FPU_REGISTER_TYPE f19;   /* 57 -- saved if FP enabled */
431  __MIPS_FPU_REGISTER_TYPE f20;   /* 58 -- saved if FP enabled */
432  __MIPS_FPU_REGISTER_TYPE f21;   /* 59 -- saved if FP enabled */
433  __MIPS_FPU_REGISTER_TYPE f22;   /* 60 -- saved if FP enabled */
434  __MIPS_FPU_REGISTER_TYPE f23;   /* 61 -- saved if FP enabled */
435  __MIPS_FPU_REGISTER_TYPE f24;   /* 62 -- saved if FP enabled */
436  __MIPS_FPU_REGISTER_TYPE f25;   /* 63 -- saved if FP enabled */
437  __MIPS_FPU_REGISTER_TYPE f26;   /* 64 -- saved if FP enabled */
438  __MIPS_FPU_REGISTER_TYPE f27;   /* 65 -- saved if FP enabled */
439  __MIPS_FPU_REGISTER_TYPE f28;   /* 66 -- saved if FP enabled */
440  __MIPS_FPU_REGISTER_TYPE f29;   /* 67 -- saved if FP enabled */
441  __MIPS_FPU_REGISTER_TYPE f30;   /* 68 -- saved if FP enabled */
442  __MIPS_FPU_REGISTER_TYPE f31;   /* 69 -- saved if FP enabled */
443  __MIPS_REGISTER_TYPE     fcsr;  /* 70 -- saved on exceptions */
444                                  /*    (oddly not documented on MGV) */
445  __MIPS_REGISTER_TYPE     feir;  /* 71 -- saved on exceptions */
446                                  /*    (oddly not documented on MGV) */
447
448  /* GDB does not seem to care about anything past this point */
449
450  __MIPS_REGISTER_TYPE  tlbhi;    /* 72 - NOT FILLED IN, doesn't exist on */
451                                  /*         all MIPS CPUs (at least MGV) */
452#if __mips == 1
453  __MIPS_REGISTER_TYPE  tlblo;    /* 73 - NOT FILLED IN, doesn't exist on */
454                                  /*         all MIPS CPUs (at least MGV) */
455#endif
456#if  (__mips == 3) || (__mips == 32)
457  __MIPS_REGISTER_TYPE  tlblo0;   /* 73 - NOT FILLED IN, doesn't exist on */
458                                  /*         all MIPS CPUs (at least MGV) */
459#endif
460
461  __MIPS_REGISTER_TYPE  inx;      /* 74 -- NOT FILLED IN, doesn't exist on */
462                                  /*         all MIPS CPUs (at least MGV) */
463  __MIPS_REGISTER_TYPE  rand;     /* 75 -- NOT FILLED IN, doesn't exist on */
464                                  /*         all MIPS CPUs (at least MGV) */
465  __MIPS_REGISTER_TYPE  ctxt;     /* 76 -- NOT FILLED IN, doesn't exist on */
466                                  /*         all MIPS CPUs (at least MGV) */
467  __MIPS_REGISTER_TYPE  exctype;  /* 77 -- NOT FILLED IN (not enough info) */
468  __MIPS_REGISTER_TYPE  mode;     /* 78 -- NOT FILLED IN (not enough info) */
469  __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
470  __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
471  /* end of __mips == 1 so NREGS == 81 */
472#if  (__mips == 3) || (__mips == 32)
473  __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
474  __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
475  __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
476  __MIPS_REGISTER_TYPE  count;    /* 84 -- NOT FILLED IN */
477  __MIPS_REGISTER_TYPE  compare;  /* 85 -- NOT FILLED IN */
478  __MIPS_REGISTER_TYPE  config;   /* 86 -- NOT FILLED IN */
479  __MIPS_REGISTER_TYPE  lladdr;   /* 87 -- NOT FILLED IN */
480  __MIPS_REGISTER_TYPE  watchlo;  /* 88 -- NOT FILLED IN */
481  __MIPS_REGISTER_TYPE  watchhi;  /* 89 -- NOT FILLED IN */
482  __MIPS_REGISTER_TYPE  ecc;      /* 90 -- NOT FILLED IN */
483  __MIPS_REGISTER_TYPE  cacheerr; /* 91 -- NOT FILLED IN */
484  __MIPS_REGISTER_TYPE  taglo;    /* 92 -- NOT FILLED IN */
485  __MIPS_REGISTER_TYPE  taghi;    /* 93 -- NOT FILLED IN */
486  __MIPS_REGISTER_TYPE  errpc;    /* 94 -- NOT FILLED IN */
487  __MIPS_REGISTER_TYPE  xctxt;    /* 95 -- NOT FILLED IN */
488 /* end of __mips == 3 so NREGS == 96 */
489#endif
490
491} CPU_Interrupt_frame;
492
493typedef CPU_Interrupt_frame CPU_Exception_frame;
494
495/*
496 *  This variable is optional.  It is used on CPUs on which it is difficult
497 *  to generate an "uninitialized" FP context.  It is filled in by
498 *  _CPU_Initialize and copied into the task's FP context area during
499 *  _CPU_Context_Initialize.
500 */
501
502extern Context_Control_fp _CPU_Null_fp_context;
503
504/*
505 *  Nothing prevents the porter from declaring more CPU specific variables.
506 */
507
508/* XXX: if needed, put more variables here */
509
510/*
511 *  The size of the floating point context area.  On some CPUs this
512 *  will not be a "sizeof" because the format of the floating point
513 *  area is not defined -- only the size is.  This is usually on
514 *  CPUs with a "floating point save context" instruction.
515 */
516
517#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
518
519/*
520 *  Amount of extra stack (above minimum stack size) required by
521 *  system initialization thread.  Remember that in a multiprocessor
522 *  system the system intialization thread becomes the MP server thread.
523 */
524
525#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
526
527/*
528 *  Should be large enough to run all RTEMS tests.  This ensures
529 *  that a "reasonable" small application should not have any problems.
530 */
531
532#define CPU_STACK_MINIMUM_SIZE          (8 * 1024)
533
534/*
535 *  CPU's worst alignment requirement for data types on a byte boundary.  This
536 *  alignment does not take into account the requirements for the stack.
537 */
538
539#define CPU_ALIGNMENT              8
540
541/*
542 *  This number corresponds to the byte alignment requirement for the
543 *  heap handler.  This alignment requirement may be stricter than that
544 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
545 *  common for the heap to follow the same alignment requirement as
546 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
547 *  then this should be set to CPU_ALIGNMENT.
548 *
549 *  NOTE:  This does not have to be a power of 2.  It does have to
550 *         be greater or equal to than CPU_ALIGNMENT.
551 */
552
553#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
554
555/*
556 *  This number corresponds to the byte alignment requirement for the
557 *  stack.  This alignment requirement may be stricter than that for the
558 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
559 *  is strict enough for the stack, then this should be set to 0.
560 *
561 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
562 */
563
564#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
565
566#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
567
568void mips_vector_exceptions( CPU_Interrupt_frame *frame );
569
570/*
571 *  ISR handler macros
572 */
573
574/*
575 *  Declare the function that is present in the shared libcpu directory,
576 *  that returns the processor dependent interrupt mask.
577 */
578
579uint32_t mips_interrupt_mask( void );
580
581/*
582 *  Disable all interrupts for an RTEMS critical section.  The previous
583 *  level is returned in _level.
584 */
585
586#define _CPU_ISR_Disable( _level ) \
587  do { \
588    unsigned int _scratch; \
589    mips_get_sr( _scratch ); \
590    mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
591    _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
592  } while(0)
593
594/*
595 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
596 *  This indicates the end of an RTEMS critical section.  The parameter
597 *  _level is not modified.
598 */
599
600#define _CPU_ISR_Enable( _level )  \
601  do { \
602    unsigned int _scratch; \
603    mips_get_sr( _scratch ); \
604    mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
605  } while(0)
606
607/*
608 *  This temporarily restores the interrupt to _level before immediately
609 *  disabling them again.  This is used to divide long RTEMS critical
610 *  sections into two or more parts.  The parameter _level is not
611 *  modified.
612 */
613
614#define _CPU_ISR_Flash( _xlevel ) \
615  do { \
616    unsigned int _scratch2 = _xlevel; \
617    _CPU_ISR_Enable( _scratch2 ); \
618    _CPU_ISR_Disable( _scratch2 ); \
619    _xlevel = _scratch2; \
620  } while(0)
621
622RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
623{
624  return ( level & SR_INTERRUPT_ENABLE_BITS ) != 0;
625}
626
627/*
628 *  Map interrupt level in task mode onto the hardware that the CPU
629 *  actually provides.  Currently, interrupt levels which do not
630 *  map onto the CPU in a generic fashion are undefined.  Someday,
631 *  it would be nice if these were "mapped" by the application
632 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
633 *  8 - 255 would be available for bsp/application specific meaning.
634 *  This could be used to manage a programmable interrupt controller
635 *  via the rtems_task_mode directive.
636 *
637 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
638 *  manipulates the IEC.
639 */
640
641uint32_t   _CPU_ISR_Get_level( void );  /* in cpu.c */
642
643void _CPU_ISR_Set_level( uint32_t   );  /* in cpu.c */
644
645/* end of ISR handler macros */
646
647/* Context handler macros */
648
649/*
650 *  Initialize the context to a state suitable for starting a
651 *  task after a context restore operation.  Generally, this
652 *  involves:
653 *
654 *     - setting a starting address
655 *     - preparing the stack
656 *     - preparing the stack and frame pointers
657 *     - setting the proper interrupt level in the context
658 *     - initializing the floating point context
659 *
660 *  This routine generally does not set any unnecessary register
661 *  in the context.  The state of the "general data" registers is
662 *  undefined at task start time.
663 *
664 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
665 *        point thread.  This is typically only used on CPUs where the
666 *        FPU may be easily disabled by software such as on the SPARC
667 *        where the PSR contains an enable FPU bit.
668 *
669 *  The per-thread status register holds the interrupt enable, FP enable
670 *  and global interrupt enable for that thread.  It means each thread can
671 *  enable its own set of interrupts.  If interrupts are disabled, RTEMS
672 *  can still dispatch via blocking calls.  This is the function of the
673 *  "Interrupt Level", and on the MIPS, it controls the IEC bit and all
674 *  the hardware interrupts as defined in the SR.  Software ints
675 *  are automatically enabled for all threads, as they will only occur under
676 *  program control anyhow.  Besides, the interrupt level parm is only 8 bits,
677 *  and controlling the software ints plus the others would require 9.
678 *
679 *  If the Interrupt Level is 0, all ints are on.  Otherwise, the
680 *  Interrupt Level should supply a bit pattern to impose on the SR
681 *  interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6
682 *  apply to the SR register Intr bits from bit 10 thru bit 15.  Bit 7 of
683 *  the Interrupt Level parameter is unused at this time.
684 *
685 *  These are the only per-thread SR bits, the others are maintained
686 *  globally & explicitly preserved by the Context Switch code in cpu_asm.s
687 */
688
689
690#if (__mips == 3) || (__mips == 32)
691#define _INTON          SR_IE
692#if __mips_fpr==64
693#define _EXTRABITS      SR_FR
694#else
695#define _EXTRABITS      0
696#endif /* __mips_fpr==64 */
697#endif /* __mips == 3 */
698#if __mips == 1
699#define _INTON          SR_IEC
700#define _EXTRABITS      0  /* make sure we're in user mode on MIPS1 processors */
701#endif /* __mips == 1 */
702
703
704void _CPU_Context_Initialize(
705  Context_Control  *the_context,
706  uintptr_t        *stack_base,
707  uint32_t          size,
708  uint32_t          new_level,
709  void             *entry_point,
710  bool              is_fp,
711  void             *tls_area
712);
713
714
715/*
716 *  This routine is responsible for somehow restarting the currently
717 *  executing task.  If you are lucky, then all that is necessary
718 *  is restoring the context.  Otherwise, there will need to be
719 *  a special assembly routine which does something special in this
720 *  case.  Context_Restore should work most of the time.  It will
721 *  not work if restarting self conflicts with the stack frame
722 *  assumptions of restoring a context.
723 */
724
725#define _CPU_Context_Restart_self( _the_context ) \
726   _CPU_Context_restore( (_the_context) );
727
728/*
729 *  This routine initializes the FP context area passed to it to.
730 *  There are a few standard ways in which to initialize the
731 *  floating point context.  The code included for this macro assumes
732 *  that this is a CPU in which a "initial" FP context was saved into
733 *  _CPU_Null_fp_context and it simply copies it to the destination
734 *  context passed to it.
735 *
736 *  Other models include (1) not doing anything, and (2) putting
737 *  a "null FP status word" in the correct place in the FP context.
738 */
739
740#if ( CPU_HARDWARE_FP == TRUE )
741#define _CPU_Context_Initialize_fp( _destination ) \
742  { \
743   *(*(_destination)) = _CPU_Null_fp_context; \
744  }
745#endif
746
747/* end of Context handler macros */
748
749/* Fatal Error manager macros */
750
751/*
752 *  This routine copies _error into a known place -- typically a stack
753 *  location or a register, optionally disables interrupts, and
754 *  halts/stops the CPU.
755 */
756
757#define _CPU_Fatal_halt( _source, _error ) \
758  do { \
759    unsigned int _level; \
760    _CPU_ISR_Disable(_level); \
761    (void)_level; \
762    loop: goto loop; \
763  } while (0)
764
765
766extern void mips_break( int error );
767
768#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
769
770/* functions */
771
772/*
773 *  _CPU_Initialize
774 *
775 *  This routine performs CPU dependent initialization.
776 */
777
778void _CPU_Initialize(void);
779
780/*
781 *  _CPU_ISR_install_raw_handler
782 *
783 *  This routine installs a "raw" interrupt handler directly into the
784 *  processor's vector table.
785 */
786
787void _CPU_ISR_install_raw_handler(
788  uint32_t    vector,
789  proc_ptr    new_handler,
790  proc_ptr   *old_handler
791);
792
793/*
794 *  _CPU_ISR_install_vector
795 *
796 *  This routine installs an interrupt vector.
797 */
798
799void _CPU_ISR_install_vector(
800  uint32_t    vector,
801  proc_ptr    new_handler,
802  proc_ptr   *old_handler
803);
804
805/*
806 *  _CPU_Internal_threads_Idle_thread_body
807 *
808 *  This routine is the CPU dependent IDLE thread body.
809 *
810 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
811 *         is TRUE.
812 */
813
814void *_CPU_Thread_Idle_body( uintptr_t ignored );
815
816/*
817 *  _CPU_Context_switch
818 *
819 *  This routine switches from the run context to the heir context.
820 */
821
822void _CPU_Context_switch(
823  Context_Control  *run,
824  Context_Control  *heir
825);
826
827/*
828 *  _CPU_Context_restore
829 *
830 *  This routine is generally used only to restart self in an
831 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
832 *
833 *  NOTE: May be unnecessary to reload some registers.
834 */
835
836void _CPU_Context_restore(
837  Context_Control *new_context
838) RTEMS_NO_RETURN;
839
840/*
841 *  _CPU_Context_save_fp
842 *
843 *  This routine saves the floating point context passed to it.
844 */
845
846void _CPU_Context_save_fp(
847  Context_Control_fp **fp_context_ptr
848);
849
850/*
851 *  _CPU_Context_restore_fp
852 *
853 *  This routine restores the floating point context passed to it.
854 */
855
856void _CPU_Context_restore_fp(
857  Context_Control_fp **fp_context_ptr
858);
859
860void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
861
862/*  The following routine swaps the endian format of an unsigned int.
863 *  It must be static because it is referenced indirectly.
864 *
865 *  This version will work on any processor, but if there is a better
866 *  way for your CPU PLEASE use it.  The most common way to do this is to:
867 *
868 *     swap least significant two bytes with 16-bit rotate
869 *     swap upper and lower 16-bits
870 *     swap most significant two bytes with 16-bit rotate
871 *
872 *  Some CPUs have special instructions which swap a 32-bit quantity in
873 *  a single instruction (e.g. i486).  It is probably best to avoid
874 *  an "endian swapping control bit" in the CPU.  One good reason is
875 *  that interrupts would probably have to be disabled to ensure that
876 *  an interrupt does not try to access the same "chunk" with the wrong
877 *  endian.  Another good reason is that on some CPUs, the endian bit
878 *  endianness for ALL fetches -- both code and data -- so the code
879 *  will be fetched incorrectly.
880 */
881
882static inline uint32_t CPU_swap_u32(
883  uint32_t value
884)
885{
886  uint32_t   byte1, byte2, byte3, byte4, swapped;
887
888  byte4 = (value >> 24) & 0xff;
889  byte3 = (value >> 16) & 0xff;
890  byte2 = (value >> 8)  & 0xff;
891  byte1 =  value        & 0xff;
892
893  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
894  return( swapped );
895}
896
897#define CPU_swap_u16( value ) \
898  (((value&0xff) << 8) | ((value >> 8)&0xff))
899
900typedef uint32_t CPU_Counter_ticks;
901
902uint32_t _CPU_Counter_frequency( void );
903
904CPU_Counter_ticks _CPU_Counter_read( void );
905
906static inline CPU_Counter_ticks _CPU_Counter_difference(
907  CPU_Counter_ticks second,
908  CPU_Counter_ticks first
909)
910{
911  return second - first;
912}
913
914/** Type that can store a 32-bit integer or a pointer. */
915typedef uintptr_t CPU_Uint32ptr;
916
917#endif
918
919#ifdef __cplusplus
920}
921#endif
922
923/**@}*/
924#endif
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