| 1 | /* |
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| 2 | |
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| 3 | Based upon IDT provided code with the following release: |
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| 4 | |
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| 5 | This source code has been made available to you by IDT on an AS-IS |
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| 6 | basis. Anyone receiving this source is licensed under IDT copyrights |
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| 7 | to use it in any way he or she deems fit, including copying it, |
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| 8 | modifying it, compiling it, and redistributing it either with or |
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| 9 | without modifications. No license under IDT patents or patent |
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| 10 | applications is to be implied by the copyright license. |
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| 11 | |
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| 12 | Any user of this software should understand that IDT cannot provide |
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| 13 | technical support for this software and will not be responsible for |
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| 14 | any consequences resulting from the use of this software. |
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| 15 | |
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| 16 | Any person who transfers this source code or any derivative work must |
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| 17 | include the IDT copyright notice, this paragraph, and the preceeding |
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| 18 | two paragraphs in the transferred software. |
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| 19 | |
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| 20 | COPYRIGHT IDT CORPORATION 1996 |
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| 21 | LICENSED MATERIAL - PROGRAM PROPERTY OF IDT |
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| 22 | |
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| 23 | */ |
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| 24 | |
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| 25 | /* |
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| 26 | ** idtcpu.h -- cpu related defines |
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| 27 | */ |
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| 28 | |
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| 29 | #ifndef _IDTCPU_H__ |
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| 30 | #define _IDTCPU_H__ |
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| 31 | |
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| 32 | /* |
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| 33 | * 950313: Ketan added Register definition for XContext reg. |
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| 34 | * added define for WAIT instruction. |
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| 35 | * 950421: Ketan added Register definition for Config reg (R3081) |
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| 36 | */ |
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| 37 | |
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| 38 | /* |
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| 39 | ** memory configuration and mapping |
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| 40 | */ |
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| 41 | #define K0BASE 0x80000000 |
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| 42 | #define K0SIZE 0x20000000 |
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| 43 | #define K1BASE 0xa0000000 |
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| 44 | #define K1SIZE 0x20000000 |
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| 45 | #define K2BASE 0xc0000000 |
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| 46 | #define K2SIZE 0x20000000 |
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| 47 | #if defined(CPU_R4000) |
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| 48 | #define KSBASE 0xe0000000 |
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| 49 | #define KSSIZE 0x20000000 |
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| 50 | #endif |
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| 51 | |
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| 52 | #define KUBASE 0 |
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| 53 | #define KUSIZE 0x80000000 |
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| 54 | |
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| 55 | /* |
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| 56 | ** Exception Vectors |
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| 57 | */ |
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| 58 | #if defined(CPU_R3000) |
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| 59 | #define UT_VEC K0BASE /* utlbmiss vector */ |
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| 60 | #define E_VEC (K0BASE+0x80) /* exception vevtor */ |
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| 61 | #endif |
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| 62 | #if defined(CPU_R4000) |
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| 63 | #define T_VEC (K0BASE+0x000) /* tlbmiss vector */ |
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| 64 | #define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ |
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| 65 | #define C_VEC (K0BASE+0x100) /* cache error vector */ |
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| 66 | #define E_VEC (K0BASE+0x180) /* exception vector */ |
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| 67 | #endif |
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| 68 | #define R_VEC (K1BASE+0x1fc00000) /* reset vector */ |
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| 69 | |
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| 70 | /* |
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| 71 | ** Address conversion macros |
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| 72 | */ |
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| 73 | #ifdef CLANGUAGE |
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| 74 | #define CAST(as) (as) |
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| 75 | #else |
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| 76 | #define CAST(as) |
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| 77 | #endif |
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| 78 | #define K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */ |
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| 79 | #define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */ |
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| 80 | #define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */ |
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| 81 | #define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */ |
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| 82 | #define PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000) /* physical to kseg0 */ |
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| 83 | #define PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* physical to kseg1 */ |
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| 84 | |
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| 85 | /* |
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| 86 | ** Cache size constants |
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| 87 | */ |
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| 88 | #define MINCACHE 0x200 /* 512 For 3041. */ |
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| 89 | #define MAXCACHE 0x40000 /* 256*1024 256k */ |
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| 90 | |
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| 91 | #if defined(CPU_R4000) |
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| 92 | /* R4000 configuration register definitions */ |
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| 93 | #define CFG_CM 0x80000000 /* Master-Checker mode */ |
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| 94 | #define CFG_ECMASK 0x70000000 /* System Clock Ratio */ |
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| 95 | #define CFG_ECBY2 0x00000000 /* divide by 2 */ |
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| 96 | #define CFG_ECBY3 0x10000000 /* divide by 3 */ |
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| 97 | #define CFG_ECBY4 0x20000000 /* divide by 4 */ |
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| 98 | #define CFG_EPMASK 0x0f000000 /* Transmit data pattern */ |
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| 99 | #define CFG_EPD 0x00000000 /* D */ |
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| 100 | #define CFG_EPDDX 0x01000000 /* DDX */ |
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| 101 | #define CFG_EPDDXX 0x02000000 /* DDXX */ |
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| 102 | #define CFG_EPDXDX 0x03000000 /* DXDX */ |
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| 103 | #define CFG_EPDDXXX 0x04000000 /* DDXXX */ |
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| 104 | #define CFG_EPDDXXXX 0x05000000 /* DDXXXX */ |
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| 105 | #define CFG_EPDXXDXX 0x06000000 /* DXXDXX */ |
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| 106 | #define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */ |
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| 107 | #define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */ |
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| 108 | #define CFG_SBMASK 0x00c00000 /* Secondary cache block size */ |
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| 109 | #define CFG_SBSHIFT 22 |
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| 110 | #define CFG_SB4 0x00000000 /* 4 words */ |
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| 111 | #define CFG_SB8 0x00400000 /* 8 words */ |
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| 112 | #define CFG_SB16 0x00800000 /* 16 words */ |
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| 113 | #define CFG_SB32 0x00c00000 /* 32 words */ |
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| 114 | #define CFG_SS 0x00200000 /* Split secondary cache */ |
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| 115 | #define CFG_SW 0x00100000 /* Secondary cache port width */ |
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| 116 | #define CFG_EWMASK 0x000c0000 /* System port width */ |
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| 117 | #define CFG_EWSHIFT 18 |
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| 118 | #define CFG_EW64 0x00000000 /* 64 bit */ |
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| 119 | #define CFG_EW32 0x00010000 /* 32 bit */ |
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| 120 | #define CFG_SC 0x00020000 /* Secondary cache absent */ |
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| 121 | #define CFG_SM 0x00010000 /* Dirty Shared mode disabled */ |
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| 122 | #define CFG_BE 0x00008000 /* Big Endian */ |
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| 123 | #define CFG_EM 0x00004000 /* ECC mode enable */ |
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| 124 | #define CFG_EB 0x00002000 /* Block ordering */ |
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| 125 | #define CFG_ICMASK 0x00000e00 /* Instruction cache size */ |
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| 126 | #define CFG_ICSHIFT 9 |
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| 127 | #define CFG_DCMASK 0x000001c0 /* Data cache size */ |
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| 128 | #define CFG_DCSHIFT 6 |
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| 129 | #define CFG_IB 0x00000020 /* Instruction cache block size */ |
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| 130 | #define CFG_DB 0x00000010 /* Data cache block size */ |
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| 131 | #define CFG_CU 0x00000008 /* Update on Store Conditional */ |
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| 132 | #define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */ |
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| 133 | |
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| 134 | /* |
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| 135 | * R4000 primary cache mode |
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| 136 | */ |
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| 137 | #define CFG_C_UNCACHED 2 |
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| 138 | #define CFG_C_NONCOHERENT 3 |
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| 139 | #define CFG_C_COHERENTXCL 4 |
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| 140 | #define CFG_C_COHERENTXCLW 5 |
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| 141 | #define CFG_C_COHERENTUPD 6 |
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| 142 | |
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| 143 | /* |
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| 144 | * R4000 cache operations (should be in assembler...?) |
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| 145 | */ |
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| 146 | #define Index_Invalidate_I 0x0 /* 0 0 */ |
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| 147 | #define Index_Writeback_Inv_D 0x1 /* 0 1 */ |
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| 148 | #define Index_Invalidate_SI 0x2 /* 0 2 */ |
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| 149 | #define Index_Writeback_Inv_SD 0x3 /* 0 3 */ |
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| 150 | #define Index_Load_Tag_I 0x4 /* 1 0 */ |
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| 151 | #define Index_Load_Tag_D 0x5 /* 1 1 */ |
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| 152 | #define Index_Load_Tag_SI 0x6 /* 1 2 */ |
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| 153 | #define Index_Load_Tag_SD 0x7 /* 1 3 */ |
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| 154 | #define Index_Store_Tag_I 0x8 /* 2 0 */ |
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| 155 | #define Index_Store_Tag_D 0x9 /* 2 1 */ |
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| 156 | #define Index_Store_Tag_SI 0xA /* 2 2 */ |
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| 157 | #define Index_Store_Tag_SD 0xB /* 2 3 */ |
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| 158 | #define Create_Dirty_Exc_D 0xD /* 3 1 */ |
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| 159 | #define Create_Dirty_Exc_SD 0xF /* 3 3 */ |
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| 160 | #define Hit_Invalidate_I 0x10 /* 4 0 */ |
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| 161 | #define Hit_Invalidate_D 0x11 /* 4 1 */ |
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| 162 | #define Hit_Invalidate_SI 0x12 /* 4 2 */ |
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| 163 | #define Hit_Invalidate_SD 0x13 /* 4 3 */ |
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| 164 | #define Hit_Writeback_Inv_D 0x15 /* 5 1 */ |
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| 165 | #define Hit_Writeback_Inv_SD 0x17 /* 5 3 */ |
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| 166 | #define Fill_I 0x14 /* 5 0 */ |
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| 167 | #define Hit_Writeback_D 0x19 /* 6 1 */ |
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| 168 | #define Hit_Writeback_SD 0x1B /* 6 3 */ |
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| 169 | #define Hit_Writeback_I 0x18 /* 6 0 */ |
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| 170 | #define Hit_Set_Virtual_SI 0x1E /* 7 2 */ |
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| 171 | #define Hit_Set_Virtual_SD 0x1F /* 7 3 */ |
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| 172 | |
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| 173 | #ifndef WAIT |
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| 174 | #define WAIT .word 0x42000020 |
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| 175 | #endif WAIT |
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| 176 | |
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| 177 | #ifndef wait |
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| 178 | #define wait .word 0x42000020 |
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| 179 | #endif wait |
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| 180 | |
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| 181 | #endif |
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| 182 | |
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| 183 | /* |
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| 184 | ** TLB resource defines |
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| 185 | */ |
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| 186 | #if defined(CPU_R3000) |
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| 187 | #define N_TLB_ENTRIES 64 |
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| 188 | #define TLB_PGSIZE 0x1000 |
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| 189 | #define RANDBASE 8 |
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| 190 | #define TLBLO_PFNMASK 0xfffff000 |
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| 191 | #define TLBLO_PFNSHIFT 12 |
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| 192 | #define TLBLO_N 0x800 /* non-cacheable */ |
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| 193 | #define TLBLO_D 0x400 /* writeable */ |
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| 194 | #define TLBLO_V 0x200 /* valid bit */ |
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| 195 | #define TLBLO_G 0x100 /* global access bit */ |
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| 196 | |
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| 197 | #define TLBHI_VPNMASK 0xfffff000 |
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| 198 | #define TLBHI_VPNSHIFT 12 |
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| 199 | #define TLBHI_PIDMASK 0xfc0 |
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| 200 | #define TLBHI_PIDSHIFT 6 |
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| 201 | #define TLBHI_NPID 64 |
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| 202 | |
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| 203 | #define TLBINX_PROBE 0x80000000 |
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| 204 | #define TLBINX_INXMASK 0x00003f00 |
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| 205 | #define TLBINX_INXSHIFT 8 |
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| 206 | |
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| 207 | #define TLBRAND_RANDMASK 0x00003f00 |
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| 208 | #define TLBRAND_RANDSHIFT 8 |
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| 209 | |
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| 210 | #define TLBCTXT_BASEMASK 0xffe00000 |
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| 211 | #define TLBCTXT_BASESHIFT 21 |
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| 212 | |
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| 213 | #define TLBCTXT_VPNMASK 0x001ffffc |
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| 214 | #define TLBCTXT_VPNSHIFT 2 |
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| 215 | #endif |
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| 216 | #if defined(CPU_R4000) |
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| 217 | #define N_TLB_ENTRIES 48 |
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| 218 | |
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| 219 | #define TLBHI_VPN2MASK 0xffffe000 |
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| 220 | #define TLBHI_PIDMASK 0x000000ff |
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| 221 | #define TLBHI_NPID 256 |
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| 222 | |
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| 223 | #define TLBLO_PFNMASK 0x3fffffc0 |
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| 224 | #define TLBLO_PFNSHIFT 6 |
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| 225 | #define TLBLO_D 0x00000004 /* writeable */ |
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| 226 | #define TLBLO_V 0x00000002 /* valid bit */ |
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| 227 | #define TLBLO_G 0x00000001 /* global access bit */ |
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| 228 | #define TLBLO_CMASK 0x00000038 /* cache algorithm mask */ |
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| 229 | #define TLBLO_CSHIFT 3 |
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| 230 | |
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| 231 | #define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT) |
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| 232 | #define TLBLO_NONCOHERENT (CFG_C_NONCOHERENT<<TLBLO_CSHIFT) |
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| 233 | #define TLBLO_COHERENTXCL (CFG_C_COHERENTXCL<<TLBLO_CSHIFT) |
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| 234 | #define TLBLO_COHERENTXCLW (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT) |
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| 235 | #define TLBLO_COHERENTUPD (CFG_C_COHERENTUPD<<TLBLO_CSHIFT) |
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| 236 | |
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| 237 | #define TLBINX_PROBE 0x80000000 |
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| 238 | #define TLBINX_INXMASK 0x0000003f |
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| 239 | |
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| 240 | #define TLBRAND_RANDMASK 0x0000003f |
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| 241 | |
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| 242 | #define TLBCTXT_BASEMASK 0xff800000 |
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| 243 | #define TLBCTXT_BASESHIFT 23 |
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| 244 | |
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| 245 | #define TLBCTXT_VPN2MASK 0x007ffff0 |
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| 246 | #define TLBCTXT_VPN2SHIFT 4 |
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| 247 | |
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| 248 | #define TLBPGMASK_MASK 0x01ffe000 |
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| 249 | #endif |
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| 250 | |
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| 251 | #if defined(CPU_R3000) |
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| 252 | #define SR_CUMASK 0xf0000000 /* coproc usable bits */ |
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| 253 | #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ |
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| 254 | #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ |
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| 255 | #define SR_CU1 0x20000000 /* Coprocessor 1 usable */ |
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| 256 | #define SR_CU0 0x10000000 /* Coprocessor 0 usable */ |
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| 257 | |
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| 258 | #define SR_BEV 0x00400000 /* use boot exception vectors */ |
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| 259 | |
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| 260 | /* Cache control bits */ |
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| 261 | #define SR_TS 0x00200000 /* TLB shutdown */ |
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| 262 | #define SR_PE 0x00100000 /* cache parity error */ |
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| 263 | #define SR_CM 0x00080000 /* cache miss */ |
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| 264 | #define SR_PZ 0x00040000 /* cache parity zero */ |
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| 265 | #define SR_SWC 0x00020000 /* swap cache */ |
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| 266 | #define SR_ISC 0x00010000 /* Isolate data cache */ |
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| 267 | |
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| 268 | /* |
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| 269 | ** status register interrupt masks and bits |
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| 270 | */ |
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| 271 | |
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| 272 | #define SR_IMASK 0x0000ff00 /* Interrupt mask */ |
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| 273 | #define SR_IMASK8 0x00000000 /* mask level 8 */ |
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| 274 | #define SR_IMASK7 0x00008000 /* mask level 7 */ |
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| 275 | #define SR_IMASK6 0x0000c000 /* mask level 6 */ |
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| 276 | #define SR_IMASK5 0x0000e000 /* mask level 5 */ |
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| 277 | #define SR_IMASK4 0x0000f000 /* mask level 4 */ |
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| 278 | #define SR_IMASK3 0x0000f800 /* mask level 3 */ |
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| 279 | #define SR_IMASK2 0x0000fc00 /* mask level 2 */ |
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| 280 | #define SR_IMASK1 0x0000fe00 /* mask level 1 */ |
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| 281 | #define SR_IMASK0 0x0000ff00 /* mask level 0 */ |
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| 282 | |
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| 283 | #define SR_IMASKSHIFT 8 |
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| 284 | |
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| 285 | #define SR_IBIT8 0x00008000 /* bit level 8 */ |
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| 286 | #define SR_IBIT7 0x00004000 /* bit level 7 */ |
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| 287 | #define SR_IBIT6 0x00002000 /* bit level 6 */ |
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| 288 | #define SR_IBIT5 0x00001000 /* bit level 5 */ |
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| 289 | #define SR_IBIT4 0x00000800 /* bit level 4 */ |
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| 290 | #define SR_IBIT3 0x00000400 /* bit level 3 */ |
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| 291 | #define SR_IBIT2 0x00000200 /* bit level 2 */ |
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| 292 | #define SR_IBIT1 0x00000100 /* bit level 1 */ |
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| 293 | |
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| 294 | #define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */ |
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| 295 | #define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */ |
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| 296 | #define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */ |
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| 297 | #define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */ |
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| 298 | #define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */ |
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| 299 | #define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ |
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| 300 | #endif |
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| 301 | |
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| 302 | #if defined(CPU_R4000) |
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| 303 | #define SR_CUMASK 0xf0000000 /* coproc usable bits */ |
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| 304 | #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ |
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| 305 | #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ |
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| 306 | #define SR_CU1 0x20000000 /* Coprocessor 1 usable */ |
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| 307 | #define SR_CU0 0x10000000 /* Coprocessor 0 usable */ |
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| 308 | |
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| 309 | #define SR_RP 0x08000000 /* Reduced power operation */ |
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| 310 | #define SR_FR 0x04000000 /* Additional floating point registers */ |
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| 311 | #define SR_RE 0x02000000 /* Reverse endian in user mode */ |
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| 312 | |
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| 313 | #define SR_BEV 0x00400000 /* Use boot exception vectors */ |
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| 314 | #define SR_TS 0x00200000 /* TLB shutdown */ |
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| 315 | #define SR_SR 0x00100000 /* Soft reset */ |
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| 316 | #define SR_CH 0x00040000 /* Cache hit */ |
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| 317 | #define SR_CE 0x00020000 /* Use cache ECC */ |
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| 318 | #define SR_DE 0x00010000 /* Disable cache exceptions */ |
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| 319 | |
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| 320 | /* |
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| 321 | ** status register interrupt masks and bits |
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| 322 | */ |
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| 323 | |
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| 324 | #define SR_IMASK 0x0000ff00 /* Interrupt mask */ |
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| 325 | #define SR_IMASK8 0x00000000 /* mask level 8 */ |
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| 326 | #define SR_IMASK7 0x00008000 /* mask level 7 */ |
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| 327 | #define SR_IMASK6 0x0000c000 /* mask level 6 */ |
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| 328 | #define SR_IMASK5 0x0000e000 /* mask level 5 */ |
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| 329 | #define SR_IMASK4 0x0000f000 /* mask level 4 */ |
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| 330 | #define SR_IMASK3 0x0000f800 /* mask level 3 */ |
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| 331 | #define SR_IMASK2 0x0000fc00 /* mask level 2 */ |
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| 332 | #define SR_IMASK1 0x0000fe00 /* mask level 1 */ |
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| 333 | #define SR_IMASK0 0x0000ff00 /* mask level 0 */ |
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| 334 | |
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| 335 | #define SR_IMASKSHIFT 8 |
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| 336 | |
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| 337 | #define SR_IBIT8 0x00008000 /* bit level 8 */ |
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| 338 | #define SR_IBIT7 0x00004000 /* bit level 7 */ |
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| 339 | #define SR_IBIT6 0x00002000 /* bit level 6 */ |
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| 340 | #define SR_IBIT5 0x00001000 /* bit level 5 */ |
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| 341 | #define SR_IBIT4 0x00000800 /* bit level 4 */ |
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| 342 | #define SR_IBIT3 0x00000400 /* bit level 3 */ |
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| 343 | #define SR_IBIT2 0x00000200 /* bit level 2 */ |
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| 344 | #define SR_IBIT1 0x00000100 /* bit level 1 */ |
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| 345 | |
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| 346 | #define SR_KSMASK 0x00000018 /* Kernel mode mask */ |
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| 347 | #define SR_KSUSER 0x00000010 /* User mode */ |
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| 348 | #define SR_KSSUPER 0x00000008 /* Supervisor mode */ |
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| 349 | #define SR_KSKERNEL 0x00000000 /* Kernel mode */ |
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| 350 | #define SR_ERL 0x00000004 /* Error level */ |
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| 351 | #define SR_EXL 0x00000002 /* Exception level */ |
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| 352 | #define SR_IE 0x00000001 /* Interrupts enabled */ |
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| 353 | #endif |
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| 354 | |
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| 355 | |
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| 356 | |
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| 357 | /* |
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| 358 | * Cause Register |
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| 359 | */ |
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| 360 | #define CAUSE_BD 0x80000000 /* Branch delay slot */ |
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| 361 | #define CAUSE_CEMASK 0x30000000 /* coprocessor error */ |
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| 362 | #define CAUSE_CESHIFT 28 |
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| 363 | |
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| 364 | |
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| 365 | #define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */ |
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| 366 | #define CAUSE_IPSHIFT 8 |
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| 367 | |
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| 368 | #define CAUSE_EXCMASK 0x0000003C /* Cause code bits */ |
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| 369 | #define CAUSE_EXCSHIFT 2 |
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| 370 | |
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| 371 | #ifndef XDS |
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| 372 | /* |
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| 373 | ** Coprocessor 0 registers |
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| 374 | */ |
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| 375 | #define C0_INX $0 /* tlb index */ |
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| 376 | #define C0_RAND $1 /* tlb random */ |
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| 377 | #if defined(CPU_R3000) |
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| 378 | #define C0_TLBLO $2 /* tlb entry low */ |
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| 379 | #endif |
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| 380 | #if defined(CPU_R4000) |
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| 381 | #define C0_TLBLO0 $2 /* tlb entry low 0 */ |
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| 382 | #define C0_TLBLO1 $3 /* tlb entry low 1 */ |
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| 383 | #endif |
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| 384 | |
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| 385 | #define C0_CTXT $4 /* tlb context */ |
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| 386 | |
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| 387 | #if defined(CPU_R4000) |
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| 388 | #define C0_PAGEMASK $5 /* tlb page mask */ |
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| 389 | #define C0_WIRED $6 /* number of wired tlb entries */ |
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| 390 | #endif |
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| 391 | |
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| 392 | #define C0_BADVADDR $8 /* bad virtual address */ |
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| 393 | |
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| 394 | #if defined(CPU_R4000) |
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| 395 | #define C0_COUNT $9 /* cycle count */ |
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| 396 | #endif |
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| 397 | |
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| 398 | #define C0_TLBHI $10 /* tlb entry hi */ |
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| 399 | |
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| 400 | #if defined(CPU_R4000) |
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| 401 | #define C0_COMPARE $11 /* cyccle count comparator */ |
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| 402 | #endif |
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| 403 | |
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| 404 | #define C0_SR $12 /* status register */ |
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| 405 | #define C0_CAUSE $13 /* exception cause */ |
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| 406 | #define C0_EPC $14 /* exception pc */ |
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| 407 | #define C0_PRID $15 /* revision identifier */ |
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| 408 | |
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| 409 | #if defined(CPU_R3000) |
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| 410 | #define C0_CONFIG $3 /* configuration register R3081*/ |
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| 411 | #endif |
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| 412 | |
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| 413 | #if defined(CPU_R4000) |
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| 414 | #define C0_CONFIG $16 /* configuration register */ |
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| 415 | #define C0_LLADDR $17 /* linked load address */ |
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| 416 | #define C0_WATCHLO $18 /* watchpoint trap register */ |
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| 417 | #define C0_WATCHHI $19 /* watchpoint trap register */ |
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| 418 | #define C0_XCTXT $20 /* extended tlb context */ |
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| 419 | #define C0_ECC $26 /* secondary cache ECC control */ |
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| 420 | #define C0_CACHEERR $27 /* cache error status */ |
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| 421 | #define C0_TAGLO $28 /* cache tag lo */ |
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| 422 | #define C0_TAGHI $29 /* cache tag hi */ |
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| 423 | #define C0_ERRPC $30 /* cache error pc */ |
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| 424 | #endif |
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| 425 | |
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| 426 | #endif XDS |
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| 427 | |
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| 428 | #ifdef R4650 |
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| 429 | #define IWATCH $18 |
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| 430 | #define DWATCH $19 |
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| 431 | #define IBASE $0 |
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| 432 | #define IBOUND $1 |
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| 433 | #define DBASE $2 |
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| 434 | #define DBOUND $3 |
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| 435 | #define CALG $17 |
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| 436 | #endif |
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| 437 | |
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| 438 | #endif /* _IDTCPU_H__ */ |
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| 439 | |
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