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cpu_asm.S @ b49bcfc

4.104.114.84.95

Last change on this file since b49bcfc was b49bcfc, checked in by Ralf Corsepius <ralf.corsepius@…>, on 04/01/04 at 10:12:49

2004-04-01 Ralf Corsepius <ralf_corsepius@…>

cpu_asm.S: Include <rtems/asm.h> instead of <asm.h>.

Property mode set to 100644

File size: 28.0 KB

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1	/*
2	* This file contains the basic algorithms for all assembly code used
3	* in an specific CPU port of RTEMS. These algorithms must be implemented
4	* in assembly language
5	*
6	* History:
7	* Baseline: no_cpu
8	* 1996: Ported to MIPS64ORION by Craig Lebakken <craigl@transition.com>
9	* COPYRIGHT (c) 1996 by Transition Networks Inc.
10	* To anyone who acknowledges that the modifications to this file to
11	* port it to the MIPS64ORION are provided "AS IS" without any
12	* express or implied warranty:
13	* permission to use, copy, modify, and distribute this file
14	* for any purpose is hereby granted without fee, provided that
15	* the above copyright notice and this notice appears in all
16	* copies, and that the name of Transition Networks not be used in
17	* advertising or publicity pertaining to distribution of the
18	* software without specific, written prior permission. Transition
19	* Networks makes no representations about the suitability
20	* of this software for any purpose.
21	* 2000: Reworked by Alan Cudmore <alanc@linuxstart.com> to become
22	* the baseline of the more general MIPS port.
23	* 2001: Joel Sherrill <joel@OARcorp.com> continued this rework,
24	* rewriting as much as possible in C and added the JMR3904 BSP
25	* so testing could be performed on a simulator.
26	* 2001: Greg Menke <gregory.menke@gsfc.nasa.gov>, bench tested ISR
27	* performance, tweaking this code and the isr vectoring routines
28	* to reduce overhead & latencies. Added optional
29	* instrumentation as well.
30	* 2002: Greg Menke <gregory.menke@gsfc.nasa.gov>, overhauled cpu_asm.S,
31	* cpu.c and cpu.h to manage FP vs int only tasks, interrupt levels
32	* and deferred FP contexts.
33	* 2002: Joel Sherrill <joel@OARcorp.com> enhanced the exception processing
34	* by increasing the amount of context saved/restored.
35	*
36	* COPYRIGHT (c) 1989-2002.
37	* On-Line Applications Research Corporation (OAR).
38	*
39	* The license and distribution terms for this file may be
40	* found in the file LICENSE in this distribution or at
41	* http://www.rtems.com/license/LICENSE.
42	*
43	* $Id$
44	*/
45
46	#include <rtems/asm.h>
47	#include "iregdef.h"
48	#include "idtcpu.h"
49
50	#define ASSEMBLY_ONLY
51	#include <rtems/score/cpu.h>
52
53
54	/* enable debugging shadow writes to misc ram, this is a vestigal
55	* Mongoose-ism debug tool- but may be handy in the future so we
56	* left it in...
57	*/
58
59	/* #define INSTRUMENT_ISR_VECTORING */
60	/* #define INSTRUMENT_EXECUTING_THREAD */
61
62
63
64	/* Ifdefs prevent the duplication of code for MIPS ISA Level 3 ( R4xxx )
65	* and MIPS ISA Level 1 (R3xxx).
66	*/
67
68	#if __mips == 3
69	/* 64 bit register operations */
70	#define NOP
71	#define ADD dadd
72	#define STREG sd
73	#define LDREG ld
74	#define MFCO dmfc0
75	#define MTCO dmtc0
76	#define ADDU addu
77	#define ADDIU addiu
78	#define R_SZ 8
79	#define F_SZ 8
80	#define SZ_INT 8
81	#define SZ_INT_POW2 3
82
83	/* XXX if we don't always want 64 bit register ops, then another ifdef */
84
85	#elif __mips == 1
86	/* 32 bit register operations*/
87	#define NOP nop
88	#define ADD add
89	#define STREG sw
90	#define LDREG lw
91	#define MFCO mfc0
92	#define MTCO mtc0
93	#define ADDU add
94	#define ADDIU addi
95	#define R_SZ 4
96	#define F_SZ 4
97	#define SZ_INT 4
98	#define SZ_INT_POW2 2
99	#else
100	#error "mips assembly: what size registers do I deal with?"
101	#endif
102
103
104	#define ISR_VEC_SIZE 4
105	#define EXCP_STACK_SIZE (NREGS*R_SZ)
106
107
108	#ifdef __GNUC__
109	#define ASM_EXTERN(x,size) .extern x,size
110	#else
111	#define ASM_EXTERN(x,size)
112	#endif
113
114	/* NOTE: these constants must match the Context_Control structure in cpu.h */
115	#define S0_OFFSET 0
116	#define S1_OFFSET 1
117	#define S2_OFFSET 2
118	#define S3_OFFSET 3
119	#define S4_OFFSET 4
120	#define S5_OFFSET 5
121	#define S6_OFFSET 6
122	#define S7_OFFSET 7
123	#define SP_OFFSET 8
124	#define FP_OFFSET 9
125	#define RA_OFFSET 10
126	#define C0_SR_OFFSET 11
127	#define C0_EPC_OFFSET 12
128
129	/* NOTE: these constants must match the Context_Control_fp structure in cpu.h */
130	#define FP0_OFFSET 0
131	#define FP1_OFFSET 1
132	#define FP2_OFFSET 2
133	#define FP3_OFFSET 3
134	#define FP4_OFFSET 4
135	#define FP5_OFFSET 5
136	#define FP6_OFFSET 6
137	#define FP7_OFFSET 7
138	#define FP8_OFFSET 8
139	#define FP9_OFFSET 9
140	#define FP10_OFFSET 10
141	#define FP11_OFFSET 11
142	#define FP12_OFFSET 12
143	#define FP13_OFFSET 13
144	#define FP14_OFFSET 14
145	#define FP15_OFFSET 15
146	#define FP16_OFFSET 16
147	#define FP17_OFFSET 17
148	#define FP18_OFFSET 18
149	#define FP19_OFFSET 19
150	#define FP20_OFFSET 20
151	#define FP21_OFFSET 21
152	#define FP22_OFFSET 22
153	#define FP23_OFFSET 23
154	#define FP24_OFFSET 24
155	#define FP25_OFFSET 25
156	#define FP26_OFFSET 26
157	#define FP27_OFFSET 27
158	#define FP28_OFFSET 28
159	#define FP29_OFFSET 29
160	#define FP30_OFFSET 30
161	#define FP31_OFFSET 31
162
163
164	ASM_EXTERN(__exceptionStackFrame, SZ_INT)
165
166
167
168	/*
169	* _CPU_Context_save_fp_context
170	*
171	* This routine is responsible for saving the FP context
172	* at *fp_context_ptr. If the point to load the FP context
173	* from is changed then the pointer is modified by this routine.
174	*
175	* Sometimes a macro implementation of this is in cpu.h which dereferences
176	* the ** and a similarly named routine in this file is passed something
177	* like a (Context_Control_fp *). The general rule on making this decision
178	* is to avoid writing assembly language.
179	*/
180
181	/* void _CPU_Context_save_fp(
182	* void **fp_context_ptr
183	* );
184	*/
185
186	#if ( CPU_HARDWARE_FP == TRUE )
187	FRAME(_CPU_Context_save_fp,sp,0,ra)
188	.set noreorder
189	.set noat
190
191	/*
192	** Make sure the FPU is on before we save state. This code
193	** is here because the FPU context switch might occur when an
194	** integer task is switching out with a FP task switching in.
195	*/
196	MFC0 t0,C0_SR
197	li t2,SR_CU1
198	move t1,t0
199	or t0,t2 /* turn on the fpu */
200	#if __mips == 3
201	li t2,SR_EXL \| SR_IE
202	#elif __mips == 1
203	li t2,SR_IEC
204	#endif
205	not t2
206	and t0,t2 /* turn off interrupts */
207	MTC0 t0,C0_SR
208
209	ld a1,(a0)
210	move t0,ra
211	jal _CPU_Context_save_fp_from_exception
212	NOP
213
214	/*
215	** Reassert the task's state because we've not saved it yet.
216	*/
217	MTC0 t1,C0_SR
218	j t0
219	NOP
220
221	.globl _CPU_Context_save_fp_from_exception
222	_CPU_Context_save_fp_from_exception:
223	swc1 $f0,FP0_OFFSET*F_SZ(a1)
224	swc1 $f1,FP1_OFFSET*F_SZ(a1)
225	swc1 $f2,FP2_OFFSET*F_SZ(a1)
226	swc1 $f3,FP3_OFFSET*F_SZ(a1)
227	swc1 $f4,FP4_OFFSET*F_SZ(a1)
228	swc1 $f5,FP5_OFFSET*F_SZ(a1)
229	swc1 $f6,FP6_OFFSET*F_SZ(a1)
230	swc1 $f7,FP7_OFFSET*F_SZ(a1)
231	swc1 $f8,FP8_OFFSET*F_SZ(a1)
232	swc1 $f9,FP9_OFFSET*F_SZ(a1)
233	swc1 $f10,FP10_OFFSET*F_SZ(a1)
234	swc1 $f11,FP11_OFFSET*F_SZ(a1)
235	swc1 $f12,FP12_OFFSET*F_SZ(a1)
236	swc1 $f13,FP13_OFFSET*F_SZ(a1)
237	swc1 $f14,FP14_OFFSET*F_SZ(a1)
238	swc1 $f15,FP15_OFFSET*F_SZ(a1)
239	swc1 $f16,FP16_OFFSET*F_SZ(a1)
240	swc1 $f17,FP17_OFFSET*F_SZ(a1)
241	swc1 $f18,FP18_OFFSET*F_SZ(a1)
242	swc1 $f19,FP19_OFFSET*F_SZ(a1)
243	swc1 $f20,FP20_OFFSET*F_SZ(a1)
244	swc1 $f21,FP21_OFFSET*F_SZ(a1)
245	swc1 $f22,FP22_OFFSET*F_SZ(a1)
246	swc1 $f23,FP23_OFFSET*F_SZ(a1)
247	swc1 $f24,FP24_OFFSET*F_SZ(a1)
248	swc1 $f25,FP25_OFFSET*F_SZ(a1)
249	swc1 $f26,FP26_OFFSET*F_SZ(a1)
250	swc1 $f27,FP27_OFFSET*F_SZ(a1)
251	swc1 $f28,FP28_OFFSET*F_SZ(a1)
252	swc1 $f29,FP29_OFFSET*F_SZ(a1)
253	swc1 $f30,FP30_OFFSET*F_SZ(a1)
254	swc1 $f31,FP31_OFFSET*F_SZ(a1)
255	j ra
256	NOP
257	.set at
258	ENDFRAME(_CPU_Context_save_fp)
259	#endif
260
261	/*
262	* _CPU_Context_restore_fp_context
263	*
264	* This routine is responsible for restoring the FP context
265	* at *fp_context_ptr. If the point to load the FP context
266	* from is changed then the pointer is modified by this routine.
267	*
268	* Sometimes a macro implementation of this is in cpu.h which dereferences
269	* the ** and a similarly named routine in this file is passed something
270	* like a (Context_Control_fp *). The general rule on making this decision
271	* is to avoid writing assembly language.
272	*/
273
274	/* void _CPU_Context_restore_fp(
275	* void **fp_context_ptr
276	* )
277	*/
278
279	#if ( CPU_HARDWARE_FP == TRUE )
280	FRAME(_CPU_Context_restore_fp,sp,0,ra)
281	.set noat
282	.set noreorder
283
284	/*
285	** Make sure the FPU is on before we retrieve state. This code
286	** is here because the FPU context switch might occur when an
287	** integer task is switching out with a FP task switching in.
288	*/
289	MFC0 t0,C0_SR
290	li t2,SR_CU1
291	move t1,t0
292	or t0,t2 /* turn on the fpu */
293	#if __mips == 3
294	li t2,SR_EXL \| SR_IE
295	#elif __mips == 1
296	li t2,SR_IEC
297	#endif
298	not t2
299	and t0,t2 /* turn off interrupts */
300	MTC0 t0,C0_SR
301
302	ld a1,(a0)
303	move t0,ra
304	jal _CPU_Context_restore_fp_from_exception
305	NOP
306
307	/*
308	** Reassert the old task's state because we've not restored the
309	** new one yet.
310	*/
311	MTC0 t1,C0_SR
312	j t0
313	NOP
314
315	.globl _CPU_Context_restore_fp_from_exception
316	_CPU_Context_restore_fp_from_exception:
317	lwc1 $f0,FP0_OFFSET*4(a1)
318	lwc1 $f1,FP1_OFFSET*4(a1)
319	lwc1 $f2,FP2_OFFSET*4(a1)
320	lwc1 $f3,FP3_OFFSET*4(a1)
321	lwc1 $f4,FP4_OFFSET*4(a1)
322	lwc1 $f5,FP5_OFFSET*4(a1)
323	lwc1 $f6,FP6_OFFSET*4(a1)
324	lwc1 $f7,FP7_OFFSET*4(a1)
325	lwc1 $f8,FP8_OFFSET*4(a1)
326	lwc1 $f9,FP9_OFFSET*4(a1)
327	lwc1 $f10,FP10_OFFSET*4(a1)
328	lwc1 $f11,FP11_OFFSET*4(a1)
329	lwc1 $f12,FP12_OFFSET*4(a1)
330	lwc1 $f13,FP13_OFFSET*4(a1)
331	lwc1 $f14,FP14_OFFSET*4(a1)
332	lwc1 $f15,FP15_OFFSET*4(a1)
333	lwc1 $f16,FP16_OFFSET*4(a1)
334	lwc1 $f17,FP17_OFFSET*4(a1)
335	lwc1 $f18,FP18_OFFSET*4(a1)
336	lwc1 $f19,FP19_OFFSET*4(a1)
337	lwc1 $f20,FP20_OFFSET*4(a1)
338	lwc1 $f21,FP21_OFFSET*4(a1)
339	lwc1 $f22,FP22_OFFSET*4(a1)
340	lwc1 $f23,FP23_OFFSET*4(a1)
341	lwc1 $f24,FP24_OFFSET*4(a1)
342	lwc1 $f25,FP25_OFFSET*4(a1)
343	lwc1 $f26,FP26_OFFSET*4(a1)
344	lwc1 $f27,FP27_OFFSET*4(a1)
345	lwc1 $f28,FP28_OFFSET*4(a1)
346	lwc1 $f29,FP29_OFFSET*4(a1)
347	lwc1 $f30,FP30_OFFSET*4(a1)
348	lwc1 $f31,FP31_OFFSET*4(a1)
349	j ra
350	NOP
351	.set at
352	ENDFRAME(_CPU_Context_restore_fp)
353	#endif
354
355	/* _CPU_Context_switch
356	*
357	* This routine performs a normal non-FP context switch.
358	*/
359
360	/* void _CPU_Context_switch(
361	* Context_Control *run,
362	* Context_Control *heir
363	* )
364	*/
365
366	FRAME(_CPU_Context_switch,sp,0,ra)
367	.set noreorder
368
369	MFC0 t0,C0_SR
370	#if __mips == 3
371	li t1,SR_EXL \| SR_IE
372	#elif __mips == 1
373	li t1,SR_IEC
374	#endif
375	STREG t0,C0_SR_OFFSETR_SZ(a0) / save the task's SR */
376	not t1
377	and t0,t1 /* mask off interrupts while we context switch */
378	MTC0 t0,C0_SR
379	NOP
380
381	STREG ra,RA_OFFSETR_SZ(a0) / save current context */
382	STREG sp,SP_OFFSET*R_SZ(a0)
383	STREG fp,FP_OFFSET*R_SZ(a0)
384	STREG s0,S0_OFFSET*R_SZ(a0)
385	STREG s1,S1_OFFSET*R_SZ(a0)
386	STREG s2,S2_OFFSET*R_SZ(a0)
387	STREG s3,S3_OFFSET*R_SZ(a0)
388	STREG s4,S4_OFFSET*R_SZ(a0)
389	STREG s5,S5_OFFSET*R_SZ(a0)
390	STREG s6,S6_OFFSET*R_SZ(a0)
391	STREG s7,S7_OFFSET*R_SZ(a0)
392
393
394	/*
395	** this code grabs the userspace EPC if we're dispatching from
396	** an interrupt frame or supplies the address of the dispatch
397	** routines if not. This is entirely for the gdbstub's benefit so
398	** it can know where each task is running.
399	**
400	** Its value is only set when calling threadDispatch from
401	** the interrupt handler and is cleared immediately when this
402	** routine gets it.
403	*/
404
405	la t0,__exceptionStackFrame /* see if we're coming in from an exception */
406	LDREG t1, (t0)
407	NOP
408	beqz t1,1f
409
410	STREG zero, (t0) /* and clear it */
411	NOP
412	LDREG t0,R_EPCR_SZ(t1) / get the userspace EPC from the frame */
413	b 2f
414
415	1: la t0,_Thread_Dispatch /* if ==0, we're switched out */
416
417	2: STREG t0,C0_EPC_OFFSET*R_SZ(a0)
418
419
420	_CPU_Context_switch_restore:
421	LDREG ra,RA_OFFSETR_SZ(a1) / restore context */
422	LDREG sp,SP_OFFSET*R_SZ(a1)
423	LDREG fp,FP_OFFSET*R_SZ(a1)
424	LDREG s0,S0_OFFSET*R_SZ(a1)
425	LDREG s1,S1_OFFSET*R_SZ(a1)
426	LDREG s2,S2_OFFSET*R_SZ(a1)
427	LDREG s3,S3_OFFSET*R_SZ(a1)
428	LDREG s4,S4_OFFSET*R_SZ(a1)
429	LDREG s5,S5_OFFSET*R_SZ(a1)
430	LDREG s6,S6_OFFSET*R_SZ(a1)
431	LDREG s7,S7_OFFSET*R_SZ(a1)
432
433	LDREG t0, C0_SR_OFFSET*R_SZ(a1)
434
435	// NOP
436	//#if __mips == 3
437	// andi t0,SR_EXL
438	// bnez t0,_CPU_Context_1 /* set exception level from restore context */
439	// li t0,~SR_EXL
440	// MFC0 t1,C0_SR
441	// NOP
442	// and t1,t0
443	// MTC0 t1,C0_SR
444	//
445	//#elif __mips == 1
446	//
447	// andi t0,(SR_INTERRUPT_ENABLE_BITS) /* we know 0 disabled */
448	// beq t0,$0,_CPU_Context_1 /* set level from restore context */
449	// MFC0 t0,C0_SR
450	// NOP
451	// or t0,(SR_INTERRUPT_ENABLE_BITS) /* new_sr = old sr with enabled */
452	// MTC0 t0,C0_SR /* set with enabled */
453	// NOP
454
455
456	/*
457	** Incorporate the incoming task's FP coprocessor state and interrupt mask/enable
458	** into the status register. We jump thru the requisite hoops to ensure we
459	** maintain all other SR bits as global values.
460	**
461	** Get the task's FPU enable, int mask & int enable bits. Although we keep the
462	** software int enables on a per-task basis, the rtems_task_create
463	** Interrupt Level & int level manipulation functions cannot enable/disable them,
464	** so they are automatically enabled for all tasks. To turn them off, a task
465	** must itself manipulate the SR register.
466	**
467	** Although something of a hack on this processor, we treat the SR register
468	** int enables as the RTEMS interrupt level. We use the int level
469	** value as a bitmask, not as any sort of greater than/less than metric.
470	** Manipulation of a task's interrupt level directly corresponds to manipulation
471	** of that task's SR bits, as seen in cpu.c
472	**
473	** Note, interrupts are disabled before context is saved, though the task's
474	** interrupt enable state is recorded. The task swapping in will apply its
475	** specific SR bits, including interrupt enable. If further task-specific
476	** SR bits are arranged, it is this code, the cpu.c interrupt level stuff and
477	** cpu.h task initialization code that will be affected.
478	*/
479
480	li t2,SR_CU1
481	or t2,SR_IMASK
482
483	/* int enable bits */
484	#if __mips == 3
485	or t2,SR_EXL + SR_IE
486	#elif __mips == 1
487	/*
488	** Save current, previous & old int enables. This is key because
489	** we can dispatch from within the stack frame used by an
490	** interrupt service. The int enables nest, but not beyond
491	** previous and old because of the dispatch interlock seen
492	** in the interrupt processing code
493	*/
494	or t2,SR_IEC + SR_IEP + SR_IEO
495	#endif
496	and t0,t2 /* keep only the per-task bits */
497
498	MFC0 t1,C0_SR /* grab the current SR */
499	not t2
500	and t1,t2 /* mask off the old task's bits */
501	or t1,t0 /* or in the new task's bits */
502	MTC0 t1,C0_SR /* and load the new SR */
503	NOP
504
505	/* _CPU_Context_1: */
506	j ra
507	NOP
508	ENDFRAME(_CPU_Context_switch)
509
510
511	/*
512	* _CPU_Context_restore
513	*
514	* This routine is generally used only to restart self in an
515	* efficient manner. It may simply be a label in _CPU_Context_switch.
516	*
517	* NOTE: May be unnecessary to reload some registers.
518	*
519	* void _CPU_Context_restore(
520	* Context_Control *new_context
521	* );
522	*/
523
524	FRAME(_CPU_Context_restore,sp,0,ra)
525	.set noreorder
526	move a1,a0
527	j _CPU_Context_switch_restore
528	NOP
529
530	ENDFRAME(_CPU_Context_restore)
531
532
533	ASM_EXTERN(_ISR_Nest_level, SZ_INT)
534	ASM_EXTERN(_Thread_Dispatch_disable_level,SZ_INT)
535	ASM_EXTERN(_Context_Switch_necessary,SZ_INT)
536	ASM_EXTERN(_ISR_Signals_to_thread_executing,SZ_INT)
537	ASM_EXTERN(_Thread_Executing,SZ_INT)
538
539	.extern _Thread_Dispatch
540	.extern _ISR_Vector_table
541
542
543
544
545
546	/* void _DBG_Handler()
547	*
548	* This routine services the (at least) MIPS1 debug vector,
549	* only used the the hardware debugging features. This code,
550	* while optional, is best located here because its intrinsically
551	* associated with exceptions in general & thus tied pretty
552	* closely to _ISR_Handler.
553	*
554	*/
555
556
557	FRAME(_DBG_Handler,sp,0,ra)
558	.set noreorder
559	la k0,_ISR_Handler
560	j k0
561	NOP
562	.set reorder
563	ENDFRAME(_DBG_Handler)
564
565
566
567
568
569	/* void __ISR_Handler()
570	*
571	* This routine provides the RTEMS interrupt management.
572	*
573	* void _ISR_Handler()
574	*
575	*
576	* This discussion ignores a lot of the ugly details in a real
577	* implementation such as saving enough registers/state to be
578	* able to do something real. Keep in mind that the goal is
579	* to invoke a user's ISR handler which is written in C and
580	* uses a certain set of registers.
581	*
582	* Also note that the exact order is to a large extent flexible.
583	* Hardware will dictate a sequence for a certain subset of
584	* _ISR_Handler while requirements for setting
585	*
586	* At entry to "common" _ISR_Handler, the vector number must be
587	* available. On some CPUs the hardware puts either the vector
588	* number or the offset into the vector table for this ISR in a
589	* known place. If the hardware does not give us this information,
590	* then the assembly portion of RTEMS for this port will contain
591	* a set of distinct interrupt entry points which somehow place
592	* the vector number in a known place (which is safe if another
593	* interrupt nests this one) and branches to _ISR_Handler.
594	*
595	*/
596
597	FRAME(_ISR_Handler,sp,0,ra)
598	.set noreorder
599
600	/* Q: _ISR_Handler, not using IDT/SIM ...save extra regs? */
601
602	/* wastes a lot of stack space for context?? */
603	ADDIU sp,sp,-EXCP_STACK_SIZE
604
605	STREG ra, R_RAR_SZ(sp) / store ra on the stack */
606	STREG v0, R_V0*R_SZ(sp)
607	STREG v1, R_V1*R_SZ(sp)
608	STREG a0, R_A0*R_SZ(sp)
609	STREG a1, R_A1*R_SZ(sp)
610	STREG a2, R_A2*R_SZ(sp)
611	STREG a3, R_A3*R_SZ(sp)
612	STREG t0, R_T0*R_SZ(sp)
613	STREG t1, R_T1*R_SZ(sp)
614	STREG t2, R_T2*R_SZ(sp)
615	STREG t3, R_T3*R_SZ(sp)
616	STREG t4, R_T4*R_SZ(sp)
617	STREG t5, R_T5*R_SZ(sp)
618	STREG t6, R_T6*R_SZ(sp)
619	STREG t7, R_T7*R_SZ(sp)
620	mflo t0
621	STREG t8, R_T8*R_SZ(sp)
622	STREG t0, R_MDLO*R_SZ(sp)
623	STREG t9, R_T9*R_SZ(sp)
624	mfhi t0
625	STREG gp, R_GP*R_SZ(sp)
626	STREG t0, R_MDHI*R_SZ(sp)
627	STREG fp, R_FP*R_SZ(sp)
628
629	.set noat
630	STREG AT, R_AT*R_SZ(sp)
631	.set at
632
633	MFC0 t0,C0_SR
634	MFC0 t1,C0_EPC
635	STREG t0,R_SR*R_SZ(sp)
636	STREG t1,R_EPC*R_SZ(sp)
637
638
639	#ifdef INSTRUMENT_EXECUTING_THREAD
640	lw t2, _Thread_Executing
641	NOP
642	sw t2, 0x8001FFF0
643	#endif
644
645	/* determine if an interrupt generated this exception */
646
647	MFC0 t0,C0_CAUSE
648	NOP
649
650	and t1,t0,CAUSE_EXCMASK
651	beq t1, 0, _ISR_Handler_1
652
653	_ISR_Handler_Exception:
654
655	/* If we return from the exception, it is assumed nothing
656	* bad is going on and we can continue to run normally.
657	* But we want to save the entire CPU context so exception
658	* handlers can look at it and change it.
659	*
660	* NOTE: This is the path the debugger stub will take.
661	*/
662
663	/* already got t0 = cause in the interrupt test above */
664	STREG t0,R_CAUSE*R_SZ(sp)
665
666	STREG sp, R_SP*R_SZ(sp)
667
668	STREG s0,R_S0R_SZ(sp) / save s0 - s7 */
669	STREG s1,R_S1*R_SZ(sp)
670	STREG s2,R_S2*R_SZ(sp)
671	STREG s3,R_S3*R_SZ(sp)
672	STREG s4,R_S4*R_SZ(sp)
673	STREG s5,R_S5*R_SZ(sp)
674	STREG s6,R_S6*R_SZ(sp)
675	STREG s7,R_S7*R_SZ(sp)
676
677	/* CP0 special registers */
678
679	#if __mips == 1
680	MFC0 t0,C0_TAR
681	#endif
682	MFC0 t1,C0_BADVADDR
683
684	#if __mips == 1
685	STREG t0,R_TAR*R_SZ(sp)
686	#else
687	NOP
688	#endif
689	STREG t1,R_BADVADDR*R_SZ(sp)
690
691	#if ( CPU_HARDWARE_FP == TRUE )
692	MFC0 t0,C0_SR /* FPU is enabled, save state */
693	NOP
694	srl t0,t0,16
695	andi t0,t0,(SR_CU1 >> 16)
696	beqz t0, 1f
697	NOP
698
699	la a1,R_F0*R_SZ(sp)
700	jal _CPU_Context_save_fp_from_exception
701	NOP
702	MFC1 t0,C1_REVISION
703	MFC1 t1,C1_STATUS
704	STREG t0,R_FEIR*R_SZ(sp)
705	STREG t1,R_FCSR*R_SZ(sp)
706
707	1:
708	#endif
709
710	move a0,sp
711	jal mips_vector_exceptions
712	NOP
713
714
715	/*
716	** note, if the exception vector returns, rely on it to have
717	** adjusted EPC so we will return to some correct address. If
718	** this is not done, we might get stuck in an infinite loop because
719	** we'll return to the instruction where the exception occured and
720	** it could throw again.
721	**
722	** It is expected the only code using the exception processing is
723	** either the gdb stub or some user code which is either going to
724	** panic or do something useful. Regardless, it is up to each
725	** exception routine to properly adjust EPC, so the code below
726	** may be helpful for doing just that.
727	*/
728
729	/* *********************************************************************
730	** this code follows the R3000's exception return logic, but is not
731	** needed because the gdb stub does it for us. It might be useful
732	** for something else at some point...
733	**
734	* compute the address of the instruction we'll return to *
735
736	LDREG t1, R_CAUSE*R_SZ(sp)
737	LDREG t0, R_EPC*R_SZ(sp)
738
739	* first see if the exception happened in the delay slot *
740	li t3,CAUSE_BD
741	AND t4,t1,t3
742	beqz t4,excnodelay
743	NOP
744
745	* it did, now see if the branch occured or not *
746	li t3,CAUSE_BT
747	AND t4,t1,t3
748	beqz t4,excnobranch
749	NOP
750
751	* branch was taken, we resume at the branch target *
752	LDREG t0, R_TAR*R_SZ(sp)
753	j excreturn
754	NOP
755
756	excnobranch:
757	ADDU t0,R_SZ
758
759	excnodelay:
760	ADDU t0,R_SZ
761
762	excreturn:
763	STREG t0, R_EPC*R_SZ(sp)
764	NOP
765	********************************************************************* */
766
767
768	/* if we're returning into mips_break, move to the next instruction */
769
770	LDREG t0,R_EPC*R_SZ(sp)
771	la t1,mips_break
772	xor t2,t0,t1
773	bnez t2,3f
774
775	addu t0,R_SZ
776	STREG t0,R_EPC*R_SZ(sp)
777	NOP
778	3:
779
780
781
782
783	#if ( CPU_HARDWARE_FP == TRUE )
784	MFC0 t0,C0_SR /* FPU is enabled, restore state */
785	NOP
786	srl t0,t0,16
787	andi t0,t0,(SR_CU1 >> 16)
788	beqz t0, 2f
789	NOP
790
791	la a1,R_F0*R_SZ(sp)
792	jal _CPU_Context_restore_fp_from_exception
793	NOP
794	LDREG t0,R_FEIR*R_SZ(sp)
795	LDREG t1,R_FCSR*R_SZ(sp)
796	MTC1 t0,C1_REVISION
797	MTC1 t1,C1_STATUS
798	2:
799	#endif
800	LDREG s0,R_S0R_SZ(sp) / restore s0 - s7 */
801	LDREG s1,R_S1*R_SZ(sp)
802	LDREG s2,R_S2*R_SZ(sp)
803	LDREG s3,R_S3*R_SZ(sp)
804	LDREG s4,R_S4*R_SZ(sp)
805	LDREG s5,R_S5*R_SZ(sp)
806	LDREG s6,R_S6*R_SZ(sp)
807	LDREG s7,R_S7*R_SZ(sp)
808
809	/* do NOT restore the sp as this could mess up the world */
810	/* do NOT restore the cause as this could mess up the world */
811
812	/*
813	** Jump all the way out. If theres a pending interrupt, just
814	** let it be serviced later. Since we're probably using the
815	** gdb stub, we've already disrupted the ISR service timing
816	** anyhow. We oughtn't mix exception and interrupt processing
817	** in the same exception call in case the exception stuff
818	** might interfere with the dispatching & timer ticks.
819	*/
820	j _ISR_Handler_exit
821	NOP
822
823	_ISR_Handler_1:
824
825	MFC0 t1,C0_SR
826	and t0,CAUSE_IPMASK
827	and t0,t1
828
829	/* external interrupt not enabled, ignore */
830	/* but if it's not an exception or an interrupt, */
831	/* Then where did it come from??? */
832
833	beq t0,zero,_ISR_Handler_exit
834
835
836
837
838	/*
839	* save some or all context on stack
840	* may need to save some special interrupt information for exit
841	*
842	* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
843	* if ( _ISR_Nest_level == 0 )
844	* switch to software interrupt stack
845	* #endif
846	*/
847
848	/*
849	* _ISR_Nest_level++;
850	*/
851	LDREG t0,_ISR_Nest_level
852	NOP
853	ADD t0,t0,1
854	STREG t0,_ISR_Nest_level
855	/*
856	* _Thread_Dispatch_disable_level++;
857	*/
858	LDREG t1,_Thread_Dispatch_disable_level
859	NOP
860	ADD t1,t1,1
861	STREG t1,_Thread_Dispatch_disable_level
862
863	/*
864	* Call the CPU model or BSP specific routine to decode the
865	* interrupt source and actually vector to device ISR handlers.
866	*/
867
868	#ifdef INSTRUMENT_ISR_VECTORING
869	NOP
870	li t1, 1
871	sw t1, 0x8001e000
872	#endif
873
874	move a0,sp
875	jal mips_vector_isr_handlers
876	NOP
877
878	#ifdef INSTRUMENT_ISR_VECTORING
879	li t1, 0
880	sw t1, 0x8001e000
881	NOP
882	#endif
883
884	/*
885	* --_ISR_Nest_level;
886	*/
887	LDREG t2,_ISR_Nest_level
888	NOP
889	ADD t2,t2,-1
890	STREG t2,_ISR_Nest_level
891	/*
892	* --_Thread_Dispatch_disable_level;
893	*/
894	LDREG t1,_Thread_Dispatch_disable_level
895	NOP
896	ADD t1,t1,-1
897	STREG t1,_Thread_Dispatch_disable_level
898	/*
899	* if ( _Thread_Dispatch_disable_level \|\| _ISR_Nest_level )
900	* goto the label "exit interrupt (simple case)"
901	*/
902	or t0,t2,t1
903	bne t0,zero,_ISR_Handler_exit
904	NOP
905
906
907
908
909	/*
910	* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
911	* restore stack
912	* #endif
913	*
914	* if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
915	* goto the label "exit interrupt (simple case)"
916	*/
917	LDREG t0,_Context_Switch_necessary
918	LDREG t1,_ISR_Signals_to_thread_executing
919	NOP
920	or t0,t0,t1
921	beq t0,zero,_ISR_Handler_exit
922	NOP
923
924
925
926	#ifdef INSTRUMENT_EXECUTING_THREAD
927	lw t0,_Thread_Executing
928	NOP
929	sw t0,0x8001FFF4
930	#endif
931
932	/*
933	** Turn on interrupts before entering Thread_Dispatch which
934	** will run for a while, thus allowing new interrupts to
935	** be serviced. Observe the Thread_Dispatch_disable_level interlock
936	** that prevents recursive entry into Thread_Dispatch.
937	*/
938
939	MFC0 t0, C0_SR
940	#if __mips == 3
941	li t1,SR_EXL \| SR_IE
942	#elif __mips == 1
943	li t1,SR_IEC
944	#endif
945	or t0, t1
946	MTC0 t0, C0_SR
947	NOP
948
949	/* save off our stack frame so the context switcher can get to it */
950	la t0,__exceptionStackFrame
951	STREG sp,(t0)
952
953	jal _Thread_Dispatch
954	NOP
955
956	/* and make sure its clear in case we didn't dispatch. if we did, its
957	** already cleared */
958	la t0,__exceptionStackFrame
959	STREG zero,(t0)
960	NOP
961
962	/*
963	** turn interrupts back off while we restore context so
964	** a badly timed interrupt won't accidentally mess things up
965	*/
966	MFC0 t0, C0_SR
967	#if __mips == 3
968	li t1,SR_EXL \| SR_IE
969	#elif __mips == 1
970	/* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */
971	li t1,SR_IEC \| SR_KUP \| SR_KUC
972	#endif
973	not t1
974	and t0, t1
975
976	#if __mips == 1
977	/* disabled 7/29, gregm, this tasks context was saved previously in an interrupt,
978	** so we'll just restore the task's previous interrupt enables.
979
980	**
981	** make sure previous int enable is on because we're returning from an interrupt
982	** which means interrupts have to be enabled
983
984	li t1,SR_IEP
985	or t0,t1
986	*/
987	#endif
988	MTC0 t0, C0_SR
989	NOP
990
991	#ifdef INSTRUMENT_EXECUTING_THREAD
992	lw t0,_Thread_Executing
993	NOP
994	sw t0,0x8001FFF8
995	#endif
996
997
998	/*
999	* prepare to get out of interrupt
1000	* return from interrupt (maybe to _ISR_Dispatch)
1001	*
1002	* LABEL "exit interrupt (simple case):"
1003	* prepare to get out of interrupt
1004	* return from interrupt
1005	*/
1006
1007	_ISR_Handler_exit:
1008	/*
1009	** Skip the SR restore because its a global register. _CPU_Context_switch_restore
1010	** adjusts it according to each task's configuration. If we didn't dispatch, the
1011	** SR value isn't changed, so all we need to do is return.
1012	**
1013	*/
1014	/* restore context from stack */
1015
1016	#ifdef INSTRUMENT_EXECUTING_THREAD
1017	lw t0,_Thread_Executing
1018	NOP
1019	sw t0, 0x8001FFFC
1020	#endif
1021
1022	LDREG t8, R_MDLO*R_SZ(sp)
1023	LDREG t0, R_T0*R_SZ(sp)
1024	mtlo t8
1025	LDREG t8, R_MDHI*R_SZ(sp)
1026	LDREG t1, R_T1*R_SZ(sp)
1027	mthi t8
1028	LDREG t2, R_T2*R_SZ(sp)
1029	LDREG t3, R_T3*R_SZ(sp)
1030	LDREG t4, R_T4*R_SZ(sp)
1031	LDREG t5, R_T5*R_SZ(sp)
1032	LDREG t6, R_T6*R_SZ(sp)
1033	LDREG t7, R_T7*R_SZ(sp)
1034	LDREG t8, R_T8*R_SZ(sp)
1035	LDREG t9, R_T9*R_SZ(sp)
1036	LDREG gp, R_GP*R_SZ(sp)
1037	LDREG fp, R_FP*R_SZ(sp)
1038	LDREG ra, R_RA*R_SZ(sp)
1039	LDREG a0, R_A0*R_SZ(sp)
1040	LDREG a1, R_A1*R_SZ(sp)
1041	LDREG a2, R_A2*R_SZ(sp)
1042	LDREG a3, R_A3*R_SZ(sp)
1043	LDREG v1, R_V1*R_SZ(sp)
1044	LDREG v0, R_V0*R_SZ(sp)
1045
1046	LDREG k1, R_EPC*R_SZ(sp)
1047
1048	.set noat
1049	LDREG AT, R_AT*R_SZ(sp)
1050	.set at
1051
1052	ADDIU sp,sp,EXCP_STACK_SIZE
1053	j k1
1054	rfe
1055	NOP
1056
1057	.set reorder
1058	ENDFRAME(_ISR_Handler)
1059
1060
1061
1062
1063	FRAME(mips_break,sp,0,ra)
1064	.set noreorder
1065	break 0x0 /* this statement must be first in this function, assumed so by mips-stub.c */
1066	NOP
1067	j ra
1068	NOP
1069	.set reorder
1070	ENDFRAME(mips_break)
1071

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