[32f415d] | 1 | /* |
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[f198c63] | 2 | * This file contains the basic algorithms for all assembly code used |
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| 3 | * in an specific CPU port of RTEMS. These algorithms must be implemented |
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| 4 | * in assembly language |
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| 5 | * |
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[32f415d] | 6 | * History: |
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| 7 | * Baseline: no_cpu |
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| 8 | * 1996: Ported to MIPS64ORION by Craig Lebakken <craigl@transition.com> |
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| 9 | * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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| 10 | * To anyone who acknowledges that the modifications to this file to |
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| 11 | * port it to the MIPS64ORION are provided "AS IS" without any |
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| 12 | * express or implied warranty: |
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| 13 | * permission to use, copy, modify, and distribute this file |
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| 14 | * for any purpose is hereby granted without fee, provided that |
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| 15 | * the above copyright notice and this notice appears in all |
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| 16 | * copies, and that the name of Transition Networks not be used in |
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| 17 | * advertising or publicity pertaining to distribution of the |
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| 18 | * software without specific, written prior permission. Transition |
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| 19 | * Networks makes no representations about the suitability |
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| 20 | * of this software for any purpose. |
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| 21 | * 2000: Reworked by Alan Cudmore <alanc@linuxstart.com> to become |
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[2e549dad] | 22 | * the baseline of the more general MIPS port. |
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| 23 | * 2001: Joel Sherrill <joel@OARcorp.com> continued this rework, |
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| 24 | * rewriting as much as possible in C and added the JMR3904 BSP |
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| 25 | * so testing could be performed on a simulator. |
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[32f415d] | 26 | * |
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| 27 | * COPYRIGHT (c) 1989-2000. |
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[f198c63] | 28 | * On-Line Applications Research Corporation (OAR). |
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| 29 | * |
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[98e4ebf5] | 30 | * The license and distribution terms for this file may be |
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| 31 | * found in the file LICENSE in this distribution or at |
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[03f2154e] | 32 | * http://www.OARcorp.com/rtems/license.html. |
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[f198c63] | 33 | * |
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[cda277f] | 34 | * $Id$ |
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[f198c63] | 35 | */ |
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| 36 | |
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[32f415d] | 37 | #include <asm.h> |
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[f198c63] | 38 | #include "iregdef.h" |
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| 39 | #include "idtcpu.h" |
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| 40 | |
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| 41 | #define EXCP_STACK_SIZE (NREGS*R_SZ) |
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[fda47cd] | 42 | #define ISR_VEC_SIZE 4 |
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[f198c63] | 43 | |
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[2e549dad] | 44 | /* Ifdefs prevent the duplication of code for MIPS ISA Level 3 ( R4xxx ) |
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| 45 | * and MIPS ISA Level 1 (R3xxx). |
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| 46 | */ |
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| 47 | |
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| 48 | #if __mips == 3 |
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| 49 | /* 64 bit register operations */ |
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| 50 | #define ADD dadd |
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| 51 | #define STREG sd |
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| 52 | #define LDREG ld |
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| 53 | #define MFCO dmfc0 |
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| 54 | #define MTCO dmtc0 |
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| 55 | #define ADDU addu |
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| 56 | #define ADDIU addiu |
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| 57 | #define R_SZ 8 |
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| 58 | #define F_SZ 8 |
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[f198c63] | 59 | #define SZ_INT 8 |
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| 60 | #define SZ_INT_POW2 3 |
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[2e549dad] | 61 | |
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| 62 | /* XXX if we don't always want 64 bit register ops, then another ifdef */ |
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| 63 | |
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| 64 | #elif __mips == 1 |
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| 65 | /* 32 bit register operations*/ |
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| 66 | #define ADD add |
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| 67 | #define STREG sw |
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| 68 | #define LDREG lw |
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| 69 | #define MFCO mfc0 |
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| 70 | #define MTCO mtc0 |
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| 71 | #define ADDU add |
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| 72 | #define ADDIU addi |
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| 73 | #define R_SZ 4 |
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| 74 | #define F_SZ 4 |
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| 75 | #define SZ_INT 4 |
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| 76 | #define SZ_INT_POW2 2 |
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| 77 | |
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| 78 | #else |
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| 79 | #error "mips assembly: what size registers do I deal with?" |
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[f198c63] | 80 | #endif |
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| 81 | |
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[2e549dad] | 82 | |
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[f198c63] | 83 | #ifdef __GNUC__ |
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[9fd4f5c5] | 84 | #define ASM_EXTERN(x,size) .extern x,size |
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[f198c63] | 85 | #else |
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[9fd4f5c5] | 86 | #define ASM_EXTERN(x,size) |
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[f198c63] | 87 | #endif |
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| 88 | |
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| 89 | /* NOTE: these constants must match the Context_Control structure in cpu.h */ |
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| 90 | #define S0_OFFSET 0 |
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| 91 | #define S1_OFFSET 1 |
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| 92 | #define S2_OFFSET 2 |
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| 93 | #define S3_OFFSET 3 |
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| 94 | #define S4_OFFSET 4 |
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| 95 | #define S5_OFFSET 5 |
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| 96 | #define S6_OFFSET 6 |
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| 97 | #define S7_OFFSET 7 |
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| 98 | #define SP_OFFSET 8 |
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| 99 | #define FP_OFFSET 9 |
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| 100 | #define RA_OFFSET 10 |
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| 101 | #define C0_SR_OFFSET 11 |
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| 102 | #define C0_EPC_OFFSET 12 |
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| 103 | |
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| 104 | /* NOTE: these constants must match the Context_Control_fp structure in cpu.h */ |
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| 105 | #define FP0_OFFSET 0 |
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| 106 | #define FP1_OFFSET 1 |
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| 107 | #define FP2_OFFSET 2 |
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| 108 | #define FP3_OFFSET 3 |
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| 109 | #define FP4_OFFSET 4 |
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| 110 | #define FP5_OFFSET 5 |
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| 111 | #define FP6_OFFSET 6 |
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| 112 | #define FP7_OFFSET 7 |
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| 113 | #define FP8_OFFSET 8 |
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| 114 | #define FP9_OFFSET 9 |
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| 115 | #define FP10_OFFSET 10 |
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| 116 | #define FP11_OFFSET 11 |
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| 117 | #define FP12_OFFSET 12 |
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| 118 | #define FP13_OFFSET 13 |
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| 119 | #define FP14_OFFSET 14 |
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| 120 | #define FP15_OFFSET 15 |
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| 121 | #define FP16_OFFSET 16 |
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| 122 | #define FP17_OFFSET 17 |
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| 123 | #define FP18_OFFSET 18 |
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| 124 | #define FP19_OFFSET 19 |
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| 125 | #define FP20_OFFSET 20 |
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| 126 | #define FP21_OFFSET 21 |
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| 127 | #define FP22_OFFSET 22 |
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| 128 | #define FP23_OFFSET 23 |
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| 129 | #define FP24_OFFSET 24 |
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| 130 | #define FP25_OFFSET 25 |
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| 131 | #define FP26_OFFSET 26 |
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| 132 | #define FP27_OFFSET 27 |
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| 133 | #define FP28_OFFSET 28 |
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| 134 | #define FP29_OFFSET 29 |
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| 135 | #define FP30_OFFSET 30 |
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| 136 | #define FP31_OFFSET 31 |
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| 137 | |
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| 138 | |
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| 139 | /* |
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| 140 | * _CPU_Context_save_fp_context |
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| 141 | * |
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| 142 | * This routine is responsible for saving the FP context |
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| 143 | * at *fp_context_ptr. If the point to load the FP context |
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| 144 | * from is changed then the pointer is modified by this routine. |
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| 145 | * |
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| 146 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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| 147 | * the ** and a similarly named routine in this file is passed something |
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| 148 | * like a (Context_Control_fp *). The general rule on making this decision |
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| 149 | * is to avoid writing assembly language. |
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| 150 | */ |
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| 151 | |
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| 152 | /* void _CPU_Context_save_fp( |
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[32f415d] | 153 | * void **fp_context_ptr |
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| 154 | * ); |
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[f198c63] | 155 | */ |
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| 156 | |
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[2e549dad] | 157 | #if ( CPU_HARDWARE_FP == FALSE ) |
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[f198c63] | 158 | FRAME(_CPU_Context_save_fp,sp,0,ra) |
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[2e549dad] | 159 | .set noat |
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| 160 | ld a1,(a0) |
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| 161 | swc1 $f0,FP0_OFFSET*F_SZ(a1) |
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| 162 | swc1 $f1,FP1_OFFSET*F_SZ(a1) |
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| 163 | swc1 $f2,FP2_OFFSET*F_SZ(a1) |
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| 164 | swc1 $f3,FP3_OFFSET*F_SZ(a1) |
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| 165 | swc1 $f4,FP4_OFFSET*F_SZ(a1) |
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| 166 | swc1 $f5,FP5_OFFSET*F_SZ(a1) |
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| 167 | swc1 $f6,FP6_OFFSET*F_SZ(a1) |
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| 168 | swc1 $f7,FP7_OFFSET*F_SZ(a1) |
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| 169 | swc1 $f8,FP8_OFFSET*F_SZ(a1) |
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| 170 | swc1 $f9,FP9_OFFSET*F_SZ(a1) |
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| 171 | swc1 $f10,FP10_OFFSET*F_SZ(a1) |
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| 172 | swc1 $f11,FP11_OFFSET*F_SZ(a1) |
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| 173 | swc1 $f12,FP12_OFFSET*F_SZ(a1) |
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| 174 | swc1 $f13,FP13_OFFSET*F_SZ(a1) |
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| 175 | swc1 $f14,FP14_OFFSET*F_SZ(a1) |
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| 176 | swc1 $f15,FP15_OFFSET*F_SZ(a1) |
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| 177 | swc1 $f16,FP16_OFFSET*F_SZ(a1) |
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| 178 | swc1 $f17,FP17_OFFSET*F_SZ(a1) |
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| 179 | swc1 $f18,FP18_OFFSET*F_SZ(a1) |
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| 180 | swc1 $f19,FP19_OFFSET*F_SZ(a1) |
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| 181 | swc1 $f20,FP20_OFFSET*F_SZ(a1) |
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| 182 | swc1 $f21,FP21_OFFSET*F_SZ(a1) |
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| 183 | swc1 $f22,FP22_OFFSET*F_SZ(a1) |
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| 184 | swc1 $f23,FP23_OFFSET*F_SZ(a1) |
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| 185 | swc1 $f24,FP24_OFFSET*F_SZ(a1) |
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| 186 | swc1 $f25,FP25_OFFSET*F_SZ(a1) |
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| 187 | swc1 $f26,FP26_OFFSET*F_SZ(a1) |
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| 188 | swc1 $f27,FP27_OFFSET*F_SZ(a1) |
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| 189 | swc1 $f28,FP28_OFFSET*F_SZ(a1) |
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| 190 | swc1 $f29,FP29_OFFSET*F_SZ(a1) |
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| 191 | swc1 $f30,FP30_OFFSET*F_SZ(a1) |
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| 192 | swc1 $f31,FP31_OFFSET*F_SZ(a1) |
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| 193 | j ra |
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| 194 | nop |
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| 195 | .set at |
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[f198c63] | 196 | ENDFRAME(_CPU_Context_save_fp) |
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[2e549dad] | 197 | #endif |
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[f198c63] | 198 | |
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| 199 | /* |
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| 200 | * _CPU_Context_restore_fp_context |
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| 201 | * |
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| 202 | * This routine is responsible for restoring the FP context |
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| 203 | * at *fp_context_ptr. If the point to load the FP context |
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| 204 | * from is changed then the pointer is modified by this routine. |
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| 205 | * |
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| 206 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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| 207 | * the ** and a similarly named routine in this file is passed something |
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| 208 | * like a (Context_Control_fp *). The general rule on making this decision |
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| 209 | * is to avoid writing assembly language. |
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| 210 | */ |
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| 211 | |
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| 212 | /* void _CPU_Context_restore_fp( |
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[32f415d] | 213 | * void **fp_context_ptr |
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[f198c63] | 214 | * ) |
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| 215 | */ |
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| 216 | |
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[2e549dad] | 217 | #if ( CPU_HARDWARE_FP == FALSE ) |
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[f198c63] | 218 | FRAME(_CPU_Context_restore_fp,sp,0,ra) |
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[2e549dad] | 219 | .set noat |
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| 220 | ld a1,(a0) |
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| 221 | lwc1 $f0,FP0_OFFSET*4(a1) |
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| 222 | lwc1 $f1,FP1_OFFSET*4(a1) |
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| 223 | lwc1 $f2,FP2_OFFSET*4(a1) |
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| 224 | lwc1 $f3,FP3_OFFSET*4(a1) |
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| 225 | lwc1 $f4,FP4_OFFSET*4(a1) |
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| 226 | lwc1 $f5,FP5_OFFSET*4(a1) |
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| 227 | lwc1 $f6,FP6_OFFSET*4(a1) |
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| 228 | lwc1 $f7,FP7_OFFSET*4(a1) |
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| 229 | lwc1 $f8,FP8_OFFSET*4(a1) |
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| 230 | lwc1 $f9,FP9_OFFSET*4(a1) |
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| 231 | lwc1 $f10,FP10_OFFSET*4(a1) |
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| 232 | lwc1 $f11,FP11_OFFSET*4(a1) |
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| 233 | lwc1 $f12,FP12_OFFSET*4(a1) |
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| 234 | lwc1 $f13,FP13_OFFSET*4(a1) |
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| 235 | lwc1 $f14,FP14_OFFSET*4(a1) |
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| 236 | lwc1 $f15,FP15_OFFSET*4(a1) |
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| 237 | lwc1 $f16,FP16_OFFSET*4(a1) |
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| 238 | lwc1 $f17,FP17_OFFSET*4(a1) |
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| 239 | lwc1 $f18,FP18_OFFSET*4(a1) |
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| 240 | lwc1 $f19,FP19_OFFSET*4(a1) |
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| 241 | lwc1 $f20,FP20_OFFSET*4(a1) |
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| 242 | lwc1 $f21,FP21_OFFSET*4(a1) |
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| 243 | lwc1 $f22,FP22_OFFSET*4(a1) |
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| 244 | lwc1 $f23,FP23_OFFSET*4(a1) |
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| 245 | lwc1 $f24,FP24_OFFSET*4(a1) |
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| 246 | lwc1 $f25,FP25_OFFSET*4(a1) |
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| 247 | lwc1 $f26,FP26_OFFSET*4(a1) |
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| 248 | lwc1 $f27,FP27_OFFSET*4(a1) |
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| 249 | lwc1 $f28,FP28_OFFSET*4(a1) |
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| 250 | lwc1 $f29,FP29_OFFSET*4(a1) |
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| 251 | lwc1 $f30,FP30_OFFSET*4(a1) |
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| 252 | lwc1 $f31,FP31_OFFSET*4(a1) |
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| 253 | j ra |
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| 254 | nop |
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| 255 | .set at |
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[f198c63] | 256 | ENDFRAME(_CPU_Context_restore_fp) |
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[2e549dad] | 257 | #endif |
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[f198c63] | 258 | |
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| 259 | /* _CPU_Context_switch |
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| 260 | * |
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| 261 | * This routine performs a normal non-FP context switch. |
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| 262 | */ |
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| 263 | |
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| 264 | /* void _CPU_Context_switch( |
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[32f415d] | 265 | * Context_Control *run, |
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| 266 | * Context_Control *heir |
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[f198c63] | 267 | * ) |
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| 268 | */ |
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| 269 | |
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| 270 | FRAME(_CPU_Context_switch,sp,0,ra) |
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| 271 | |
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[2e549dad] | 272 | mfc0 t0,C0_SR |
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| 273 | li t1,~(SR_INTERRUPT_ENABLE_BITS) |
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| 274 | STREG t0,C0_SR_OFFSET*4(a0) /* save status register */ |
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| 275 | and t0,t1 |
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| 276 | mtc0 t0,C0_SR /* first disable ie bit (recommended) */ |
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| 277 | #if __mips == 3 |
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| 278 | ori t0,SR_EXL|SR_IE /* enable exception level to disable interrupts */ |
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| 279 | mtc0 t0,C0_SR |
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| 280 | #endif |
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[f198c63] | 281 | |
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[2e549dad] | 282 | STREG ra,RA_OFFSET*R_SZ(a0) /* save current context */ |
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| 283 | STREG sp,SP_OFFSET*R_SZ(a0) |
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| 284 | STREG fp,FP_OFFSET*R_SZ(a0) |
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| 285 | STREG s0,S0_OFFSET*R_SZ(a0) |
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| 286 | STREG s1,S1_OFFSET*R_SZ(a0) |
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| 287 | STREG s2,S2_OFFSET*R_SZ(a0) |
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| 288 | STREG s3,S3_OFFSET*R_SZ(a0) |
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| 289 | STREG s4,S4_OFFSET*R_SZ(a0) |
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| 290 | STREG s5,S5_OFFSET*R_SZ(a0) |
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| 291 | STREG s6,S6_OFFSET*R_SZ(a0) |
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| 292 | STREG s7,S7_OFFSET*R_SZ(a0) |
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| 293 | |
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| 294 | MFC0 t0,C0_EPC |
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| 295 | STREG t0,C0_EPC_OFFSET*R_SZ(a0) |
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[f198c63] | 296 | |
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[2e549dad] | 297 | _CPU_Context_switch_restore: |
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| 298 | LDREG s0,S0_OFFSET*R_SZ(a1) /* restore context */ |
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| 299 | LDREG s1,S1_OFFSET*R_SZ(a1) |
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| 300 | LDREG s2,S2_OFFSET*R_SZ(a1) |
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| 301 | LDREG s3,S3_OFFSET*R_SZ(a1) |
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| 302 | LDREG s4,S4_OFFSET*R_SZ(a1) |
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| 303 | LDREG s5,S5_OFFSET*R_SZ(a1) |
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| 304 | LDREG s6,S6_OFFSET*R_SZ(a1) |
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| 305 | LDREG s7,S7_OFFSET*R_SZ(a1) |
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| 306 | LDREG fp,FP_OFFSET*R_SZ(a1) |
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| 307 | LDREG sp,SP_OFFSET*R_SZ(a1) |
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| 308 | LDREG ra,RA_OFFSET*R_SZ(a1) |
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| 309 | LDREG t0,C0_EPC_OFFSET*R_SZ(a1) |
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| 310 | MTC0 t0,C0_EPC |
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| 311 | LDREG t0, C0_SR_OFFSET*R_SZ(a1) |
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[fda47cd] | 312 | |
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[2e549dad] | 313 | #if __mips == 3 |
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| 314 | andi t0,SR_EXL |
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| 315 | bnez t0,_CPU_Context_1 /* set exception level from restore context */ |
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| 316 | li t0,~SR_EXL |
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| 317 | mfc0 t1,C0_SR |
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| 318 | nop |
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| 319 | and t1,t0 |
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| 320 | mtc0 t1,C0_SR |
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[fda47cd] | 321 | |
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[2e549dad] | 322 | #elif __mips == 1 |
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| 323 | andi t0,(SR_INTERRUPT_ENABLE_BITS) /* we know 0 disabled */ |
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| 324 | beq t0,$0,_CPU_Context_1 /* set level from restore context */ |
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| 325 | mfc0 t0,C0_SR |
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[32f415d] | 326 | nop |
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[2e549dad] | 327 | or t0,(SR_INTERRUPT_ENABLE_BITS) /* new_sr = old sr with enabled */ |
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| 328 | mtc0 t0,C0_SR /* set with enabled */ |
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| 329 | #endif |
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[fda47cd] | 330 | |
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| 331 | _CPU_Context_1: |
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| 332 | j ra |
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| 333 | nop |
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| 334 | ENDFRAME(_CPU_Context_switch) |
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| 335 | |
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[f198c63] | 336 | /* |
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| 337 | * _CPU_Context_restore |
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| 338 | * |
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| 339 | * This routine is generally used only to restart self in an |
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| 340 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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| 341 | * |
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| 342 | * NOTE: May be unnecessary to reload some registers. |
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[32f415d] | 343 | * |
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| 344 | * void _CPU_Context_restore( |
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| 345 | * Context_Control *new_context |
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| 346 | * ); |
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[f198c63] | 347 | */ |
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| 348 | |
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| 349 | FRAME(_CPU_Context_restore,sp,0,ra) |
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[2e549dad] | 350 | ADD a1,a0,zero |
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| 351 | j _CPU_Context_switch_restore |
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| 352 | nop |
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[fda47cd] | 353 | ENDFRAME(_CPU_Context_restore) |
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| 354 | |
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[9fd4f5c5] | 355 | ASM_EXTERN(_ISR_Nest_level, SZ_INT) |
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| 356 | ASM_EXTERN(_Thread_Dispatch_disable_level,SZ_INT) |
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| 357 | ASM_EXTERN(_Context_Switch_necessary,SZ_INT) |
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| 358 | ASM_EXTERN(_ISR_Signals_to_thread_executing,SZ_INT) |
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[f198c63] | 359 | .extern _Thread_Dispatch |
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| 360 | .extern _ISR_Vector_table |
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| 361 | |
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| 362 | /* void __ISR_Handler() |
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| 363 | * |
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| 364 | * This routine provides the RTEMS interrupt management. |
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| 365 | * |
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[32f415d] | 366 | * void _ISR_Handler() |
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| 367 | * |
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| 368 | * |
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| 369 | * This discussion ignores a lot of the ugly details in a real |
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| 370 | * implementation such as saving enough registers/state to be |
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| 371 | * able to do something real. Keep in mind that the goal is |
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| 372 | * to invoke a user's ISR handler which is written in C and |
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| 373 | * uses a certain set of registers. |
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| 374 | * |
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| 375 | * Also note that the exact order is to a large extent flexible. |
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| 376 | * Hardware will dictate a sequence for a certain subset of |
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| 377 | * _ISR_Handler while requirements for setting |
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| 378 | * |
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| 379 | * At entry to "common" _ISR_Handler, the vector number must be |
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| 380 | * available. On some CPUs the hardware puts either the vector |
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| 381 | * number or the offset into the vector table for this ISR in a |
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| 382 | * known place. If the hardware does not give us this information, |
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| 383 | * then the assembly portion of RTEMS for this port will contain |
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| 384 | * a set of distinct interrupt entry points which somehow place |
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| 385 | * the vector number in a known place (which is safe if another |
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| 386 | * interrupt nests this one) and branches to _ISR_Handler. |
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| 387 | * |
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[f198c63] | 388 | */ |
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| 389 | |
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| 390 | FRAME(_ISR_Handler,sp,0,ra) |
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[2e549dad] | 391 | .set noreorder |
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| 392 | |
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| 393 | /* Q: _ISR_Handler, not using IDT/SIM ...save extra regs? */ |
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| 394 | |
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| 395 | /* wastes a lot of stack space for context?? */ |
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| 396 | ADDIU sp,sp,-EXCP_STACK_SIZE |
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| 397 | |
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| 398 | STREG ra, R_RA*R_SZ(sp) /* store ra on the stack */ |
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| 399 | STREG v0, R_V0*R_SZ(sp) |
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| 400 | STREG v1, R_V1*R_SZ(sp) |
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| 401 | STREG a0, R_A0*R_SZ(sp) |
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| 402 | STREG a1, R_A1*R_SZ(sp) |
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| 403 | STREG a2, R_A2*R_SZ(sp) |
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| 404 | STREG a3, R_A3*R_SZ(sp) |
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| 405 | STREG t0, R_T0*R_SZ(sp) |
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| 406 | STREG t1, R_T1*R_SZ(sp) |
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| 407 | STREG t2, R_T2*R_SZ(sp) |
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| 408 | STREG t3, R_T3*R_SZ(sp) |
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| 409 | STREG t4, R_T4*R_SZ(sp) |
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| 410 | STREG t5, R_T5*R_SZ(sp) |
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| 411 | STREG t6, R_T6*R_SZ(sp) |
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| 412 | STREG t7, R_T7*R_SZ(sp) |
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| 413 | mflo k0 |
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| 414 | STREG t8, R_T8*R_SZ(sp) |
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| 415 | STREG k0, R_MDLO*R_SZ(sp) |
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| 416 | STREG t9, R_T9*R_SZ(sp) |
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| 417 | mfhi k0 |
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| 418 | STREG gp, R_GP*R_SZ(sp) |
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| 419 | STREG fp, R_FP*R_SZ(sp) |
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| 420 | STREG k0, R_MDHI*R_SZ(sp) |
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| 421 | .set noat |
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| 422 | STREG AT, R_AT*R_SZ(sp) |
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| 423 | .set at |
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[fda47cd] | 424 | |
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| 425 | /* Q: Why hardcode -40 for stack add??? */ |
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| 426 | /* This needs to be figured out.........*/ |
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[2e549dad] | 427 | ADDIU sp,sp,-40 |
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| 428 | STREG ra,32(sp) /* store ra on the stack */ |
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[176e1ed8] | 429 | MFC0 t0, C0_EPC /* XXX */ |
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| 430 | STREG t0,16(sp) /* XXX store EPC on the stack */ |
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| 431 | mfc0 t0,C0_SR |
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| 432 | STREG t0,24(sp) /* XXX store SR on the stack */ |
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[fda47cd] | 433 | |
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| 434 | /* determine if an interrupt generated this exception */ |
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| 435 | |
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[2e549dad] | 436 | mfc0 k0,C0_CAUSE |
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| 437 | and k1,k0,CAUSE_EXCMASK |
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| 438 | beq k1, 0, _ISR_Handler_1 |
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[fda47cd] | 439 | nop |
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| 440 | |
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| 441 | _ISR_Handler_Exception: |
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| 442 | nop |
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[2e549dad] | 443 | b _ISR_Handler_Exception /* Jump to the exception code */ |
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[fda47cd] | 444 | nop |
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| 445 | |
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| 446 | _ISR_Handler_1: |
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| 447 | |
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[2e549dad] | 448 | mfc0 k1,C0_SR |
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| 449 | and k0,k1 |
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| 450 | and k0,CAUSE_IPMASK |
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| 451 | beq k0,zero,_ISR_Handler_exit |
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| 452 | /* external interrupt not enabled, ignore */ |
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[797d88ba] | 453 | /* but if it's not an exception or an interrupt, */ |
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[2e549dad] | 454 | /* Then where did it come from??? */ |
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| 455 | nop |
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[fda47cd] | 456 | |
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| 457 | /* |
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| 458 | * save some or all context on stack |
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| 459 | * may need to save some special interrupt information for exit |
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| 460 | * |
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| 461 | * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
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| 462 | * if ( _ISR_Nest_level == 0 ) |
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| 463 | * switch to software interrupt stack |
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| 464 | * #endif |
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| 465 | */ |
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| 466 | |
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| 467 | /* |
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| 468 | * _ISR_Nest_level++; |
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| 469 | */ |
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[2e549dad] | 470 | LDREG t0,_ISR_Nest_level |
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| 471 | ADD t0,t0,1 |
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| 472 | STREG t0,_ISR_Nest_level |
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[fda47cd] | 473 | /* |
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| 474 | * _Thread_Dispatch_disable_level++; |
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| 475 | */ |
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[2e549dad] | 476 | LDREG t1,_Thread_Dispatch_disable_level |
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| 477 | ADD t1,t1,1 |
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| 478 | STREG t1,_Thread_Dispatch_disable_level |
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[fda47cd] | 479 | |
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| 480 | /* |
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[797d88ba] | 481 | * Call the CPU model or BSP specific routine to decode the |
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| 482 | * interrupt source and actually vector to device ISR handlers. |
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[fda47cd] | 483 | */ |
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| 484 | |
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[2e549dad] | 485 | jal mips_vector_isr_handlers |
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[fda47cd] | 486 | nop |
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| 487 | |
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| 488 | /* |
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| 489 | * --_ISR_Nest_level; |
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| 490 | */ |
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[2e549dad] | 491 | LDREG t2,_ISR_Nest_level |
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| 492 | ADD t2,t2,-1 |
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| 493 | STREG t2,_ISR_Nest_level |
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[fda47cd] | 494 | /* |
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| 495 | * --_Thread_Dispatch_disable_level; |
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| 496 | */ |
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[2e549dad] | 497 | LDREG t1,_Thread_Dispatch_disable_level |
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| 498 | ADD t1,t1,-1 |
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| 499 | STREG t1,_Thread_Dispatch_disable_level |
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[fda47cd] | 500 | /* |
---|
| 501 | * if ( _Thread_Dispatch_disable_level || _ISR_Nest_level ) |
---|
| 502 | * goto the label "exit interrupt (simple case)" |
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| 503 | */ |
---|
[2e549dad] | 504 | or t0,t2,t1 |
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| 505 | bne t0,zero,_ISR_Handler_exit |
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| 506 | nop |
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[fda47cd] | 507 | /* |
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| 508 | * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
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| 509 | * restore stack |
---|
| 510 | * #endif |
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| 511 | * |
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| 512 | * if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing ) |
---|
| 513 | * goto the label "exit interrupt (simple case)" |
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| 514 | */ |
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[2e549dad] | 515 | LDREG t0,_Context_Switch_necessary |
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| 516 | LDREG t1,_ISR_Signals_to_thread_executing |
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| 517 | or t0,t0,t1 |
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| 518 | beq t0,zero,_ISR_Handler_exit |
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| 519 | nop |
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[fda47cd] | 520 | /* |
---|
| 521 | * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch |
---|
| 522 | */ |
---|
[2e549dad] | 523 | jal _Thread_Dispatch |
---|
| 524 | nop |
---|
[fda47cd] | 525 | /* |
---|
| 526 | * prepare to get out of interrupt |
---|
| 527 | * return from interrupt (maybe to _ISR_Dispatch) |
---|
| 528 | * |
---|
| 529 | * LABEL "exit interrupt (simple case): |
---|
| 530 | * prepare to get out of interrupt |
---|
| 531 | * return from interrupt |
---|
| 532 | */ |
---|
| 533 | |
---|
| 534 | _ISR_Handler_exit: |
---|
[2e549dad] | 535 | LDREG ra,32(sp) |
---|
[176e1ed8] | 536 | LDREG t0,16(sp) /* XXX restore EPC on the stack */ |
---|
| 537 | MTC0 t0, C0_EPC /* XXX */ |
---|
| 538 | LDREG t0,24(sp) /* XXX restore SR on the stack */ |
---|
| 539 | mtc0 t0,C0_SR |
---|
[2e549dad] | 540 | ADDIU sp,sp,40 /* Q: Again with the 40...Is this needed? */ |
---|
[fda47cd] | 541 | |
---|
| 542 | /* restore interrupt context from stack */ |
---|
| 543 | |
---|
[2e549dad] | 544 | LDREG k0, R_MDLO*R_SZ(sp) |
---|
| 545 | mtlo k0 |
---|
| 546 | LDREG k0, R_MDHI*R_SZ(sp) |
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| 547 | LDREG a2, R_A2*R_SZ(sp) |
---|
| 548 | mthi k0 |
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| 549 | LDREG a3, R_A3*R_SZ(sp) |
---|
| 550 | LDREG t0, R_T0*R_SZ(sp) |
---|
| 551 | LDREG t1, R_T1*R_SZ(sp) |
---|
| 552 | LDREG t2, R_T2*R_SZ(sp) |
---|
| 553 | LDREG t3, R_T3*R_SZ(sp) |
---|
| 554 | LDREG t4, R_T4*R_SZ(sp) |
---|
| 555 | LDREG t5, R_T5*R_SZ(sp) |
---|
| 556 | LDREG t6, R_T6*R_SZ(sp) |
---|
| 557 | LDREG t7, R_T7*R_SZ(sp) |
---|
| 558 | LDREG t8, R_T8*R_SZ(sp) |
---|
| 559 | LDREG t9, R_T9*R_SZ(sp) |
---|
| 560 | LDREG gp, R_GP*R_SZ(sp) |
---|
| 561 | LDREG fp, R_FP*R_SZ(sp) |
---|
| 562 | LDREG ra, R_RA*R_SZ(sp) |
---|
| 563 | LDREG a0, R_A0*R_SZ(sp) |
---|
| 564 | LDREG a1, R_A1*R_SZ(sp) |
---|
| 565 | LDREG v1, R_V1*R_SZ(sp) |
---|
| 566 | LDREG v0, R_V0*R_SZ(sp) |
---|
| 567 | .set noat |
---|
| 568 | LDREG AT, R_AT*R_SZ(sp) |
---|
| 569 | .set at |
---|
| 570 | |
---|
| 571 | ADDIU sp,sp,EXCP_STACK_SIZE |
---|
| 572 | |
---|
| 573 | MFC0 k0, C0_EPC |
---|
[176e1ed8] | 574 | nop |
---|
[2e549dad] | 575 | |
---|
[fda47cd] | 576 | rfe /* Might not need to do RFE here... */ |
---|
[2e549dad] | 577 | j k0 |
---|
| 578 | nop |
---|
[fda47cd] | 579 | |
---|
| 580 | .set reorder |
---|
| 581 | ENDFRAME(_ISR_Handler) |
---|
| 582 | |
---|
[f198c63] | 583 | FRAME(mips_break,sp,0,ra) |
---|
| 584 | #if 1 |
---|
[2e549dad] | 585 | break 0x0 |
---|
| 586 | j mips_break |
---|
[f198c63] | 587 | #else |
---|
[2e549dad] | 588 | j ra |
---|
[f198c63] | 589 | #endif |
---|
[2e549dad] | 590 | nop |
---|
[f198c63] | 591 | ENDFRAME(mips_break) |
---|
| 592 | |
---|