source: rtems/cpukit/score/cpu/mips/cpu.c @ febaa8a

4.104.11
Last change on this file since febaa8a was febaa8a, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 27, 2010 at 3:03:09 PM

2010-03-27 Joel Sherrill <joel.sherrill@…>

  • cpu.c, cpu_asm.S: Add include of config.h
  • Property mode set to 100644
File size: 7.6 KB
Line 
1/*
2 *  Mips CPU Dependent Source
3 *
4 *  2002:       Greg Menke (gregory.menke@gsfc.nasa.gov)
5 *      Overhauled interrupt level and interrupt enable/disable code
6 *      to more exactly support MIPS.  Our mods were for MIPS1 processors
7 *      MIPS3 ports are affected, though apps written to the old behavior
8 *      should still work OK.
9 *
10 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
11 *           Joel Sherrill <joel@OARcorp.com>.
12 *
13 *    These changes made the code conditional on standard cpp predefines,
14 *    merged the mips1 and mips3 code sequences as much as possible,
15 *    and moved some of the assembly code to C.  Alan did much of the
16 *    initial analysis and rework.  Joel took over from there and
17 *    wrote the JMR3904 BSP so this could be tested.  Joel also
18 *    added the new interrupt vectoring support in libcpu and
19 *    tried to better support the various interrupt controllers.
20 *
21 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
22 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
23 *
24 *         To anyone who acknowledges that this file is provided "AS IS"
25 *         without any express or implied warranty:
26 *             permission to use, copy, modify, and distribute this file
27 *             for any purpose is hereby granted without fee, provided that
28 *             the above copyright notice and this notice appears in all
29 *             copies, and that the name of Transition Networks not be used in
30 *             advertising or publicity pertaining to distribution of the
31 *             software without specific, written prior permission.
32 *             Transition Networks makes no representations about the
33 *             suitability of this software for any purpose.
34 *
35 *  COPYRIGHT (c) 1989-2001.
36 *  On-Line Applications Research Corporation (OAR).
37 *
38 *  The license and distribution terms for this file may be
39 *  found in the file LICENSE in this distribution or at
40 *  http://www.rtems.com/license/LICENSE.
41 *
42 *  $Id$
43 */
44
45#ifdef HAVE_CONFIG_H
46#include "config.h"
47#endif
48
49#include <rtems/system.h>
50#include <rtems/score/isr.h>
51#include <rtems/score/wkspace.h>
52
53/*
54** Exception stack frame pointer used in cpu_asm to pass the exception stack frame
55** address to the context switch code.
56*/
57#if (__mips == 1) || (__mips == 32)
58typedef uint32_t ESF_PTR_TYPE;
59#elif (__mips == 3)
60typedef uint64_t ESF_PTR_TYPE;
61#else
62#error "unknown MIPS ISA"
63#endif
64
65ESF_PTR_TYPE __exceptionStackFrame = 0;
66
67
68
69
70/*  _CPU_Initialize
71 *
72 *  This routine performs processor dependent initialization.
73 *
74 *    thread_dispatch - address of dispatching routine
75 */
76
77void _CPU_Initialize(void)
78{
79  /*
80   *  If there is not an easy way to initialize the FP context
81   *  during Context_Initialize, then it is usually easier to
82   *  save an "uninitialized" FP context here and copy it to
83   *  the task's during Context_Initialize.
84   */
85
86#if CPU_HARDWARE_FP
87  /* FP context initialization support goes here */
88  _CPU_Null_fp_context.fpcs = 0x1000000;        /* Set FS flag in floating point coprocessor
89                                                   control register to prevent underflow and
90                                                   inexact exceptions */
91#endif
92}
93
94/*PAGE
95 *
96 *  _CPU_ISR_Get_level
97 *
98 *  This routine returns the current interrupt level.
99 */
100
101uint32_t   _CPU_ISR_Get_level( void )
102{
103  unsigned int sr;
104
105  mips_get_sr(sr);
106
107  /* printf("current sr=%08X, ",sr); */
108
109#if (__mips == 3) || (__mips == 32)
110/* IE bit and shift down hardware ints into bits 1 thru 6 */
111  sr = (sr & SR_IE) | ((sr & mips_interrupt_mask()) >> 9);
112
113#elif __mips == 1
114/* IEC bit and shift down hardware ints into bits 1 thru 6 */
115  sr = (sr & SR_IEC) | ((sr & mips_interrupt_mask()) >> 9);
116
117#else
118#error "CPU ISR level: unknown MIPS level for SR handling"
119#endif
120  return sr;
121}
122
123
124void _CPU_ISR_Set_level( uint32_t   new_level )
125{
126  unsigned int sr, srbits;
127
128  /*
129  ** mask off the int level bits only so we can
130  ** preserve software int settings and FP enable
131  ** for this thread.  Note we don't force software ints
132  ** enabled when changing level, they were turned on
133  ** when this task was created, but may have been turned
134  ** off since, so we'll just leave them alone.
135  */
136
137  new_level &= 0xff;
138
139  mips_get_sr(sr);
140
141#if (__mips == 3) || (__mips == 32)
142  mips_set_sr( (sr & ~SR_IE) );                 /* first disable ie bit (recommended) */
143
144   srbits = sr & ~(0xfc00 | SR_IE);
145
146   sr = srbits | ((new_level==0)? (mips_interrupt_mask() | SR_IE): \
147                 (((new_level<<9) & mips_interrupt_mask()) | \
148                   ((new_level & 1)?SR_IE:0)));
149/*
150  if ( (new_level & SR_EXL) == (sr & SR_EXL) )
151    return;
152
153  if ( (new_level & SR_EXL) == 0 ) {
154    sr &= ~SR_EXL;                    * clear the EXL bit *
155    mips_set_sr(sr);
156  } else {
157
158    sr |= SR_EXL|SR_IE;              * enable exception level *
159    mips_set_sr(sr);                 * first disable ie bit (recommended) *
160  }
161*/
162
163#elif __mips == 1
164  mips_set_sr( (sr & ~SR_IEC) );
165  srbits = sr & ~(0xfc00 | SR_IEC);
166  sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc00) | \
167                                         (new_level & SR_IEC)));
168#else
169#error "CPU ISR level: unknown MIPS level for SR handling"
170#endif
171  mips_set_sr( sr );
172}
173
174
175
176/*PAGE
177 *
178 *  _CPU_ISR_install_raw_handler
179 *
180 *  Input parameters:
181 *    vector      - interrupt vector number
182 *    old_handler - former ISR for this vector number
183 *    new_handler - replacement ISR for this vector number
184 *
185 *  Output parameters:  NONE
186 *
187 */
188
189void _CPU_ISR_install_raw_handler(
190  uint32_t    vector,
191  proc_ptr    new_handler,
192  proc_ptr   *old_handler
193)
194{
195  /*
196   *  This is where we install the interrupt handler into the "raw" interrupt
197   *  table used by the CPU to dispatch interrupt handlers.
198   *
199   *  Because all interrupts are vectored through the same exception handler
200   *  this is not necessary on thi sport.
201   */
202}
203
204/*PAGE
205 *
206 *  _CPU_ISR_install_vector
207 *
208 *  This kernel routine installs the RTEMS handler for the
209 *  specified vector.
210 *
211 *  Input parameters:
212 *    vector      - interrupt vector number
213 *    old_handler - former ISR for this vector number
214 *    new_handler - replacement ISR for this vector number
215 *
216 *  Output parameters:  NONE
217 *
218 */
219
220void _CPU_ISR_install_vector(
221  uint32_t    vector,
222  proc_ptr    new_handler,
223  proc_ptr   *old_handler
224)
225{
226   *old_handler = _ISR_Vector_table[ vector ];
227
228   /*
229    *  If the interrupt vector table is a table of pointer to isr entry
230    *  points, then we need to install the appropriate RTEMS interrupt
231    *  handler for this vector number.
232    */
233
234   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
235
236   /*
237    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
238    *  be used by the _ISR_Handler so the user gets control.
239    */
240
241    _ISR_Vector_table[ vector ] = new_handler;
242}
243
244/*PAGE
245 *
246 *  _CPU_Install_interrupt_stack
247 */
248
249void _CPU_Install_interrupt_stack( void )
250{
251/* we don't support this yet */
252}
253
254/*PAGE
255 *
256 *  _CPU_Internal_threads_Idle_thread_body
257 *
258 *  NOTES:
259 *
260 *  1. This is the same as the regular CPU independent algorithm.
261 *
262 *  2. If you implement this using a "halt", "idle", or "shutdown"
263 *     instruction, then don't forget to put it in an infinite loop.
264 *
265 *  3. Be warned. Some processors with onboard DMA have been known
266 *     to stop the DMA if the CPU were put in IDLE mode.  This might
267 *     also be a problem with other on-chip peripherals.  So use this
268 *     hook with caution.
269 */
270
271void *_CPU_Thread_Idle_body( uintptr_t ignored )
272{
273#if (__mips == 3) || (__mips == 32)
274   for( ; ; )
275     asm volatile("wait"); /* use wait to enter low power mode */
276#elif __mips == 1
277   for( ; ; )
278     ;
279#else
280#error "IDLE: __mips not set to 1 or 3"
281#endif
282}
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