source: rtems/cpukit/score/cpu/mips/cpu.c @ f26145b

4.104.114.84.95
Last change on this file since f26145b was 5194a28, checked in by Greg Menke <gregory.menke@…>, on 12/06/04 at 20:29:51

PR 730

  • cpu_asm.S: Collected PR 601 changes for commit to cvshead for rtems-4.7
  • Property mode set to 100644
File size: 7.3 KB
Line 
1/*
2 *  Mips CPU Dependent Source
3 *
4 *  2002:       Greg Menke (gregory.menke@gsfc.nasa.gov)
5 *      Overhauled interrupt level and interrupt enable/disable code
6 *      to more exactly support MIPS.  Our mods were for MIPS1 processors
7 *      MIPS3 ports are affected, though apps written to the old behavior
8 *      should still work OK.
9 *
10 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
11 *           Joel Sherrill <joel@OARcorp.com>.
12 *
13 *    These changes made the code conditional on standard cpp predefines,
14 *    merged the mips1 and mips3 code sequences as much as possible,
15 *    and moved some of the assembly code to C.  Alan did much of the
16 *    initial analysis and rework.  Joel took over from there and
17 *    wrote the JMR3904 BSP so this could be tested.  Joel also
18 *    added the new interrupt vectoring support in libcpu and
19 *    tried to better support the various interrupt controllers.
20 *
21 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
22 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
23 *
24 *         To anyone who acknowledges that this file is provided "AS IS"
25 *         without any express or implied warranty:
26 *             permission to use, copy, modify, and distribute this file
27 *             for any purpose is hereby granted without fee, provided that
28 *             the above copyright notice and this notice appears in all
29 *             copies, and that the name of Transition Networks not be used in
30 *             advertising or publicity pertaining to distribution of the
31 *             software without specific, written prior permission.
32 *             Transition Networks makes no representations about the
33 *             suitability of this software for any purpose.
34 *
35 *  COPYRIGHT (c) 1989-2001.
36 *  On-Line Applications Research Corporation (OAR).
37 *
38 *  The license and distribution terms for this file may be
39 *  found in the file LICENSE in this distribution or at
40 *  http://www.rtems.com/license/LICENSE.
41 *
42 *  $Id$
43 */
44
45#include <rtems/system.h>
46#include <rtems/score/isr.h>
47#include <rtems/score/wkspace.h>
48
49
50
51
52/*
53** local dword used in cpu_asm to pass the exception stack frame to the
54** context switch code.
55*/
56unsigned __exceptionStackFrame = 0;
57
58
59
60
61
62/*  _CPU_Initialize
63 *
64 *  This routine performs processor dependent initialization.
65 *
66 *  INPUT PARAMETERS:
67 *    cpu_table       - CPU table to initialize
68 *    thread_dispatch - address of disptaching routine
69 */
70
71
72void _CPU_Initialize(
73  rtems_cpu_table  *cpu_table,
74  void      (*thread_dispatch)      /* ignored on this CPU */
75)
76{
77  /*
78   *  If there is not an easy way to initialize the FP context
79   *  during Context_Initialize, then it is usually easier to
80   *  save an "uninitialized" FP context here and copy it to
81   *  the task's during Context_Initialize.
82   */
83
84  /* FP context initialization support goes here */
85
86  _CPU_Table = *cpu_table;
87}
88
89/*PAGE
90 *
91 *  _CPU_ISR_Get_level
92 *
93 *  This routine returns the current interrupt level.
94 */
95
96uint32_t   _CPU_ISR_Get_level( void )
97{
98  unsigned int sr;
99
100  mips_get_sr(sr);
101
102  /* printf("current sr=%08X, ",sr); */
103
104#if (__mips == 3) || (__mips == 32)
105/* IE bit and shift down hardware ints into bits 1 thru 6 */
106  sr = (sr & SR_IE) | ((sr & 0xfc00) >> 9);
107
108#elif __mips == 1
109/* IEC bit and shift down hardware ints into bits 1 thru 6 */
110  sr = (sr & SR_IEC) | ((sr & 0xfc00) >> 9);
111
112#else
113#error "CPU ISR level: unknown MIPS level for SR handling"
114#endif
115  return sr;
116}
117
118
119void _CPU_ISR_Set_level( uint32_t   new_level )
120{
121  unsigned int sr, srbits;
122
123  /*
124  ** mask off the int level bits only so we can
125  ** preserve software int settings and FP enable
126  ** for this thread.  Note we don't force software ints
127  ** enabled when changing level, they were turned on
128  ** when this task was created, but may have been turned
129  ** off since, so we'll just leave them alone.
130  */
131
132  new_level &= 0xff;
133
134  mips_get_sr(sr);
135
136#if (__mips == 3) || (__mips == 32)
137  mips_set_sr( (sr & ~SR_IE) );                 /* first disable ie bit (recommended) */
138
139   srbits = sr & ~(0xfc00 | SR_IE);
140
141   sr = srbits | ((new_level==0)? (0xfc00 | SR_IE): \
142                 (((new_level<<9) & 0xfc00) | \
143                   ((new_level & 1)?SR_IE:0)));
144/*
145  if ( (new_level & SR_EXL) == (sr & SR_EXL) )
146    return;
147
148  if ( (new_level & SR_EXL) == 0 ) {
149    sr &= ~SR_EXL;                    * clear the EXL bit *
150    mips_set_sr(sr);
151  } else {
152
153    sr |= SR_EXL|SR_IE;              * enable exception level *
154    mips_set_sr(sr);                 * first disable ie bit (recommended) *
155  }
156*/
157 
158#elif __mips == 1
159  mips_set_sr( (sr & ~SR_IEC) );
160  srbits = sr & ~(0xfc00 | SR_IEC);
161  sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc00) | \
162                                         (new_level & SR_IEC)));
163#else
164#error "CPU ISR level: unknown MIPS level for SR handling"
165#endif
166  mips_set_sr( sr );
167}
168
169
170
171/*PAGE
172 *
173 *  _CPU_ISR_install_raw_handler
174 *
175 *  Input parameters:
176 *    vector      - interrupt vector number
177 *    old_handler - former ISR for this vector number
178 *    new_handler - replacement ISR for this vector number
179 *
180 *  Output parameters:  NONE
181 *
182 */
183 
184void _CPU_ISR_install_raw_handler(
185  uint32_t    vector,
186  proc_ptr    new_handler,
187  proc_ptr   *old_handler
188)
189{
190  /*
191   *  This is where we install the interrupt handler into the "raw" interrupt
192   *  table used by the CPU to dispatch interrupt handlers.
193   *
194   *  Because all interrupts are vectored through the same exception handler
195   *  this is not necessary on thi sport.
196   */
197}
198
199/*PAGE
200 *
201 *  _CPU_ISR_install_vector
202 *
203 *  This kernel routine installs the RTEMS handler for the
204 *  specified vector.
205 *
206 *  Input parameters:
207 *    vector      - interrupt vector number
208 *    old_handler - former ISR for this vector number
209 *    new_handler - replacement ISR for this vector number
210 *
211 *  Output parameters:  NONE
212 *
213 */
214
215void _CPU_ISR_install_vector(
216  uint32_t    vector,
217  proc_ptr    new_handler,
218  proc_ptr   *old_handler
219)
220{
221   *old_handler = _ISR_Vector_table[ vector ];
222
223   /*
224    *  If the interrupt vector table is a table of pointer to isr entry
225    *  points, then we need to install the appropriate RTEMS interrupt
226    *  handler for this vector number.
227    */
228
229   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
230
231   /*
232    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
233    *  be used by the _ISR_Handler so the user gets control.
234    */
235
236    _ISR_Vector_table[ vector ] = new_handler;
237}
238
239/*PAGE
240 *
241 *  _CPU_Install_interrupt_stack
242 */
243
244void _CPU_Install_interrupt_stack( void )
245{
246/* we don't support this yet */
247}
248
249/*PAGE
250 *
251 *  _CPU_Internal_threads_Idle_thread_body
252 *
253 *  NOTES:
254 *
255 *  1. This is the same as the regular CPU independent algorithm.
256 *
257 *  2. If you implement this using a "halt", "idle", or "shutdown"
258 *     instruction, then don't forget to put it in an infinite loop.
259 *
260 *  3. Be warned. Some processors with onboard DMA have been known
261 *     to stop the DMA if the CPU were put in IDLE mode.  This might
262 *     also be a problem with other on-chip peripherals.  So use this
263 *     hook with caution.
264 */
265
266void _CPU_Thread_Idle_body( void )
267{
268#if (__mips == 3) || (__mips == 32)
269   for( ; ; )
270     asm volatile("wait"); /* use wait to enter low power mode */
271#elif __mips == 1
272   for( ; ; )
273     ;
274#else
275#error "IDLE: __mips not set to 1 or 3"
276#endif
277}
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