source: rtems/cpukit/score/cpu/mips/cpu.c @ d7a48e1

Last change on this file since d7a48e1 was 3fe2155, checked in by Sebastian Huber <sebastian.huber@…>, on 02/01/19 at 09:00:36

Remove superfluous <rtems/system.h> includes

  • Property mode set to 100644
File size: 6.8 KB
Line 
1/**
2 *  @file
3 *
4 *  @brief MIPS CPU Dependent Source
5 */
6
7/*
8 * MIPS CPU Dependent Source
9 *
10 *  2002:       Greg Menke (gregory.menke@gsfc.nasa.gov)
11 *      Overhauled interrupt level and interrupt enable/disable code
12 *      to more exactly support MIPS.  Our mods were for MIPS1 processors
13 *      MIPS3 ports are affected, though apps written to the old behavior
14 *      should still work OK.
15 *
16 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
17 *           Joel Sherrill <joel@OARcorp.com>.
18 *
19 *    These changes made the code conditional on standard cpp predefines,
20 *    merged the mips1 and mips3 code sequences as much as possible,
21 *    and moved some of the assembly code to C.  Alan did much of the
22 *    initial analysis and rework.  Joel took over from there and
23 *    wrote the JMR3904 BSP so this could be tested.  Joel also
24 *    added the new interrupt vectoring support in libcpu and
25 *    tried to better support the various interrupt controllers.
26 *
27 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
28 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
29 *
30 *         To anyone who acknowledges that this file is provided "AS IS"
31 *         without any express or implied warranty:
32 *             permission to use, copy, modify, and distribute this file
33 *             for any purpose is hereby granted without fee, provided that
34 *             the above copyright notice and this notice appears in all
35 *             copies, and that the name of Transition Networks not be used in
36 *             advertising or publicity pertaining to distribution of the
37 *             software without specific, written prior permission.
38 *             Transition Networks makes no representations about the
39 *             suitability of this software for any purpose.
40 *
41 *  COPYRIGHT (c) 1989-2012.
42 *  On-Line Applications Research Corporation (OAR).
43 *
44 *  The license and distribution terms for this file may be
45 *  found in the file LICENSE in this distribution or at
46 *  http://www.rtems.org/license/LICENSE.
47 */
48
49#ifdef HAVE_CONFIG_H
50#include "config.h"
51#endif
52
53#include <rtems/score/isr.h>
54#include <rtems/score/wkspace.h>
55
56#if CPU_HARDWARE_FP
57Context_Control_fp _CPU_Null_fp_context;
58#endif
59
60/*
61** Exception stack frame pointer used in cpu_asm to pass the exception stack frame
62** address to the context switch code.
63*/
64#if (__mips == 1) || (__mips == 32)
65typedef uint32_t ESF_PTR_TYPE;
66#elif (__mips == 3)
67typedef uint64_t ESF_PTR_TYPE;
68#else
69#error "unknown MIPS ISA"
70#endif
71
72ESF_PTR_TYPE __exceptionStackFrame = 0;
73/*  _CPU_Initialize
74 *
75 *  This routine performs processor dependent initialization.
76 *
77 *    thread_dispatch - address of dispatching routine
78 */
79
80void _CPU_Initialize(void)
81{
82  /*
83   *  If there is not an easy way to initialize the FP context
84   *  during Context_Initialize, then it is usually easier to
85   *  save an "uninitialized" FP context here and copy it to
86   *  the task's during Context_Initialize.
87   */
88
89#if CPU_HARDWARE_FP
90  /* FP context initialization support goes here */
91  _CPU_Null_fp_context.fpcs = 0x1000000;        /* Set FS flag in floating point coprocessor
92                                                   control register to prevent underflow and
93                                                   inexact exceptions */
94#endif
95}
96
97uint32_t   _CPU_ISR_Get_level( void )
98{
99  unsigned int sr;
100
101  mips_get_sr(sr);
102
103  /* printf("current sr=%08X, ",sr); */
104
105#if (__mips == 3) || (__mips == 32)
106/* IE bit and shift down hardware ints into bits 1 thru 6 */
107  sr = (sr & SR_IE) | ((sr & mips_interrupt_mask()) >> 9);
108
109#elif __mips == 1
110/* IEC bit and shift down hardware ints into bits 1 thru 6 */
111  sr = (sr & SR_IEC) | ((sr & mips_interrupt_mask()) >> 9);
112
113#else
114#error "CPU ISR level: unknown MIPS level for SR handling"
115#endif
116  return sr;
117}
118void _CPU_ISR_Set_level( uint32_t   new_level )
119{
120  unsigned int sr, srbits;
121
122  /*
123  ** mask off the int level bits only so we can
124  ** preserve software int settings and FP enable
125  ** for this thread.  Note we don't force software ints
126  ** enabled when changing level, they were turned on
127  ** when this task was created, but may have been turned
128  ** off since, so we'll just leave them alone.
129  */
130
131  new_level &= 0xff;
132
133  mips_get_sr(sr);
134
135#if (__mips == 3) || (__mips == 32)
136  mips_set_sr( (sr & ~SR_IE) );                 /* first disable ie bit (recommended) */
137
138   srbits = sr & ~(0xfc00 | SR_IE);
139
140   sr = srbits | ((new_level==0)? (mips_interrupt_mask() | SR_IE): \
141                 (((new_level<<9) & mips_interrupt_mask()) | \
142                   ((new_level & 1)?SR_IE:0)));
143/*
144  if ( (new_level & SR_EXL) == (sr & SR_EXL) )
145    return;
146
147  if ( (new_level & SR_EXL) == 0 ) {
148    sr &= ~SR_EXL;                    * clear the EXL bit *
149    mips_set_sr(sr);
150  } else {
151
152    sr |= SR_EXL|SR_IE;              * enable exception level *
153    mips_set_sr(sr);                 * first disable ie bit (recommended) *
154  }
155*/
156
157#elif __mips == 1
158  mips_set_sr( (sr & ~SR_IEC) );
159  srbits = sr & ~(0xfc00 | SR_IEC);
160  sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc00) | \
161                                         (new_level & SR_IEC)));
162#else
163#error "CPU ISR level: unknown MIPS level for SR handling"
164#endif
165  mips_set_sr( sr );
166}
167
168void _CPU_Context_Initialize(
169  Context_Control  *the_context,
170  uintptr_t        *stack_base,
171  uint32_t          size,
172  uint32_t          new_level,
173  void             *entry_point,
174  bool              is_fp,
175  void             *tls_area
176)
177{
178  uintptr_t             stack_tmp;
179  __MIPS_REGISTER_TYPE  intlvl = new_level & 0xff;
180  __MIPS_REGISTER_TYPE  c0_sr;
181
182  stack_tmp  = (uintptr_t)stack_base;
183  stack_tmp += ((size) - CPU_STACK_ALIGNMENT);
184  stack_tmp &= (__MIPS_REGISTER_TYPE) ~(CPU_STACK_ALIGNMENT - 1);
185
186  the_context->sp = (__MIPS_REGISTER_TYPE) stack_tmp;
187  the_context->fp = (__MIPS_REGISTER_TYPE) stack_tmp;
188  the_context->ra = (__MIPS_REGISTER_TYPE) (uintptr_t)entry_point;
189
190  c0_sr =
191    ((intlvl==0)? (mips_interrupt_mask() | 0x300 | _INTON):
192      ( ((intlvl<<9) & mips_interrupt_mask()) | 0x300 |
193      ((intlvl & 1)?_INTON:0)) ) |
194      SR_CU0 | _EXTRABITS;
195#if MIPS_HAS_FPU == 1
196  if ( is_fp ) {
197    c0_sr |= SR_CU1;
198  }
199#endif
200  the_context->c0_sr = c0_sr;
201}
202/*
203 *  _CPU_Internal_threads_Idle_thread_body
204 *
205 *  NOTES:
206 *
207 *  1. This is the same as the regular CPU independent algorithm.
208 *
209 *  2. If you implement this using a "halt", "idle", or "shutdown"
210 *     instruction, then don't forget to put it in an infinite loop.
211 *
212 *  3. Be warned. Some processors with onboard DMA have been known
213 *     to stop the DMA if the CPU were put in IDLE mode.  This might
214 *     also be a problem with other on-chip peripherals.  So use this
215 *     hook with caution.
216 */
217
218void *_CPU_Thread_Idle_body( uintptr_t ignored )
219{
220#if (__mips == 3) || (__mips == 32)
221   for( ; ; )
222     __asm__ volatile("wait"); /* use wait to enter low power mode */
223#elif __mips == 1
224   for( ; ; )
225     ;
226#else
227#error "IDLE: __mips not set to 1 or 3"
228#endif
229}
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