source: rtems/cpukit/score/cpu/mips/cpu.c @ c346f33d

4.104.114.84.95
Last change on this file since c346f33d was c346f33d, checked in by Ralf Corsepius <ralf.corsepius@…>, on Mar 30, 2004 at 11:49:14 AM

2004-03-30 Ralf Corsepius <ralf_corsepius@…>

  • cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
  • Property mode set to 100644
File size: 7.4 KB
Line 
1/*
2 *  Mips CPU Dependent Source
3 *
4 *  2002:       Greg Menke (gregory.menke@gsfc.nasa.gov)
5 *      Overhauled interrupt level and interrupt enable/disable code
6 *      to more exactly support MIPS.  Our mods were for MIPS1 processors
7 *      MIPS3 ports are affected, though apps written to the old behavior
8 *      should still work OK.
9 *
10 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
11 *           Joel Sherrill <joel@OARcorp.com>.
12 *
13 *    These changes made the code conditional on standard cpp predefines,
14 *    merged the mips1 and mips3 code sequences as much as possible,
15 *    and moved some of the assembly code to C.  Alan did much of the
16 *    initial analysis and rework.  Joel took over from there and
17 *    wrote the JMR3904 BSP so this could be tested.  Joel also
18 *    added the new interrupt vectoring support in libcpu and
19 *    tried to better support the various interrupt controllers.
20 *
21 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
22 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
23 *
24 *         To anyone who acknowledges that this file is provided "AS IS"
25 *         without any express or implied warranty:
26 *             permission to use, copy, modify, and distribute this file
27 *             for any purpose is hereby granted without fee, provided that
28 *             the above copyright notice and this notice appears in all
29 *             copies, and that the name of Transition Networks not be used in
30 *             advertising or publicity pertaining to distribution of the
31 *             software without specific, written prior permission.
32 *             Transition Networks makes no representations about the
33 *             suitability of this software for any purpose.
34 *
35 *  COPYRIGHT (c) 1989-2001.
36 *  On-Line Applications Research Corporation (OAR).
37 *
38 *  The license and distribution terms for this file may be
39 *  found in the file LICENSE in this distribution or at
40 *  http://www.rtems.com/license/LICENSE.
41 *
42 *  $Id$
43 */
44
45#include <rtems/system.h>
46#include <rtems/score/isr.h>
47#include <rtems/score/wkspace.h>
48
49
50
51
52/*
53** local dword used in cpu_asm to pass the exception stack frame to the
54** context switch code.
55*/
56unsigned __exceptionStackFrame = 0; 
57
58
59
60
61
62/*  _CPU_Initialize
63 *
64 *  This routine performs processor dependent initialization.
65 *
66 *  INPUT PARAMETERS:
67 *    cpu_table       - CPU table to initialize
68 *    thread_dispatch - address of disptaching routine
69 */
70
71
72void _CPU_Initialize(
73  rtems_cpu_table  *cpu_table,
74  void      (*thread_dispatch)      /* ignored on this CPU */
75)
76{
77  /*
78   *  If there is not an easy way to initialize the FP context
79   *  during Context_Initialize, then it is usually easier to
80   *  save an "uninitialized" FP context here and copy it to
81   *  the task's during Context_Initialize.
82   */
83
84  /* FP context initialization support goes here */
85
86  _CPU_Table = *cpu_table;
87}
88
89/*PAGE
90 *
91 *  _CPU_ISR_Get_level
92 *
93 *  This routine returns the current interrupt level.
94 */
95
96uint32_t   _CPU_ISR_Get_level( void )
97{
98  unsigned int sr;
99
100  mips_get_sr(sr);
101
102  //printf("current sr=%08X, ",sr);
103
104#if __mips == 3
105/* EXL bit and shift down hardware ints into bits 1 thru 6 */
106  sr = ((sr & SR_EXL) >> 1) | ((sr & 0xfc00) >> 9);
107
108#elif __mips == 1
109/* IEC bit and shift down hardware ints into bits 1 thru 6 */
110  sr = (sr & SR_IEC) | ((sr & 0xfc00) >> 9);
111
112#else
113#error "CPU ISR level: unknown MIPS level for SR handling"
114#endif
115  //printf("intlevel=%02X\n",sr);
116  return sr;
117}
118
119
120void _CPU_ISR_Set_level( uint32_t   new_level )
121{
122  unsigned int sr, srbits;
123
124  /*
125  ** mask off the int level bits only so we can
126  ** preserve software int settings and FP enable
127  ** for this thread.  Note we don't force software ints
128  ** enabled when changing level, they were turned on
129  ** when this task was created, but may have been turned
130  ** off since, so we'll just leave them alone.
131  */
132
133  new_level &= 0xff;
134
135  mips_get_sr(sr);
136
137#if __mips == 3
138  mips_set_sr( (sr & ~SR_IE) );                 /* first disable ie bit (recommended) */
139
140  srbits = sr & ~(0xfc00 | SR_EXL | SR_IE);
141
142  sr = srbits | ((new_level==0)? (0xfc00 | SR_EXL | SR_IE): \
143                 (((new_level<<9) & 0xfc00) | \
144                  (new_level & 1)?(SR_EXL | SR_IE):0));
145/*
146  if ( (new_level & SR_EXL) == (sr & SR_EXL) )
147    return;
148
149  if ( (new_level & SR_EXL) == 0 ) {
150    sr &= ~SR_EXL;                    * clear the EXL bit *
151    mips_set_sr(sr);
152  } else {
153
154    sr |= SR_EXL|SR_IE;              * enable exception level *
155    mips_set_sr(sr);                 * first disable ie bit (recommended) *
156  }
157*/
158 
159#elif __mips == 1
160  mips_set_sr( (sr & ~SR_IEC) );
161  srbits = sr & ~(0xfc00 | SR_IEC);
162  //printf("current sr=%08X, newlevel=%02X, srbits=%08X, ",sr,new_level,srbits);
163  sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc00) | \
164                                         (new_level & SR_IEC)));
165  //printf("new sr=%08X\n",sr);
166#else
167#error "CPU ISR level: unknown MIPS level for SR handling"
168#endif
169  mips_set_sr( sr );
170}
171
172
173
174/*PAGE
175 *
176 *  _CPU_ISR_install_raw_handler
177 *
178 *  Input parameters:
179 *    vector      - interrupt vector number
180 *    old_handler - former ISR for this vector number
181 *    new_handler - replacement ISR for this vector number
182 *
183 *  Output parameters:  NONE
184 *
185 */
186 
187void _CPU_ISR_install_raw_handler(
188  uint32_t    vector,
189  proc_ptr    new_handler,
190  proc_ptr   *old_handler
191)
192{
193  /*
194   *  This is where we install the interrupt handler into the "raw" interrupt
195   *  table used by the CPU to dispatch interrupt handlers.
196   *
197   *  Because all interrupts are vectored through the same exception handler
198   *  this is not necessary on thi sport.
199   */
200}
201
202/*PAGE
203 *
204 *  _CPU_ISR_install_vector
205 *
206 *  This kernel routine installs the RTEMS handler for the
207 *  specified vector.
208 *
209 *  Input parameters:
210 *    vector      - interrupt vector number
211 *    old_handler - former ISR for this vector number
212 *    new_handler - replacement ISR for this vector number
213 *
214 *  Output parameters:  NONE
215 *
216 */
217
218void _CPU_ISR_install_vector(
219  uint32_t    vector,
220  proc_ptr    new_handler,
221  proc_ptr   *old_handler
222)
223{
224   *old_handler = _ISR_Vector_table[ vector ];
225
226   /*
227    *  If the interrupt vector table is a table of pointer to isr entry
228    *  points, then we need to install the appropriate RTEMS interrupt
229    *  handler for this vector number.
230    */
231
232   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
233
234   /*
235    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
236    *  be used by the _ISR_Handler so the user gets control.
237    */
238
239    _ISR_Vector_table[ vector ] = new_handler;
240}
241
242/*PAGE
243 *
244 *  _CPU_Install_interrupt_stack
245 */
246
247void _CPU_Install_interrupt_stack( void )
248{
249/* we don't support this yet */
250}
251
252/*PAGE
253 *
254 *  _CPU_Internal_threads_Idle_thread_body
255 *
256 *  NOTES:
257 *
258 *  1. This is the same as the regular CPU independent algorithm.
259 *
260 *  2. If you implement this using a "halt", "idle", or "shutdown"
261 *     instruction, then don't forget to put it in an infinite loop.
262 *
263 *  3. Be warned. Some processors with onboard DMA have been known
264 *     to stop the DMA if the CPU were put in IDLE mode.  This might
265 *     also be a problem with other on-chip peripherals.  So use this
266 *     hook with caution.
267 */
268
269void _CPU_Thread_Idle_body( void )
270{
271#if __mips == 3
272   for( ; ; )
273     asm volatile("wait"); /* use wait to enter low power mode */
274#elif __mips == 1
275   for( ; ; )
276     ;
277#else
278#error "IDLE: __mips not set to 1 or 3"
279#endif
280}
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