source: rtems/cpukit/score/cpu/mips/cpu.c @ b72e847b

4.8
Last change on this file since b72e847b was 60f016f, checked in by Joel Sherrill <joel.sherrill@…>, on May 22, 2007 at 8:57:34 PM

2007-05-22 Joel Sherrill <joel.sherrill@…>

  • score/cpu/arm/cpu.c, score/cpu/avr/cpu.c, score/cpu/bfin/cpu.c, score/cpu/c4x/cpu.c, score/cpu/h8300/cpu.c, score/cpu/i386/cpu.c, score/cpu/m68k/cpu.c, score/cpu/mips/cpu.c, score/cpu/nios2/cpu.c, score/cpu/no_cpu/cpu.c, score/cpu/sh/cpu.c, score/cpu/sparc/cpu.c, cpukit/sapi/src/exinit.c: Move copying of CPU Table to shared executive initialization.
  • Property mode set to 100644
File size: 7.7 KB
Line 
1/*
2 *  Mips CPU Dependent Source
3 *
4 *  2002:       Greg Menke (gregory.menke@gsfc.nasa.gov)
5 *      Overhauled interrupt level and interrupt enable/disable code
6 *      to more exactly support MIPS.  Our mods were for MIPS1 processors
7 *      MIPS3 ports are affected, though apps written to the old behavior
8 *      should still work OK.
9 *
10 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
11 *           Joel Sherrill <joel@OARcorp.com>.
12 *
13 *    These changes made the code conditional on standard cpp predefines,
14 *    merged the mips1 and mips3 code sequences as much as possible,
15 *    and moved some of the assembly code to C.  Alan did much of the
16 *    initial analysis and rework.  Joel took over from there and
17 *    wrote the JMR3904 BSP so this could be tested.  Joel also
18 *    added the new interrupt vectoring support in libcpu and
19 *    tried to better support the various interrupt controllers.
20 *
21 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
22 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
23 *
24 *         To anyone who acknowledges that this file is provided "AS IS"
25 *         without any express or implied warranty:
26 *             permission to use, copy, modify, and distribute this file
27 *             for any purpose is hereby granted without fee, provided that
28 *             the above copyright notice and this notice appears in all
29 *             copies, and that the name of Transition Networks not be used in
30 *             advertising or publicity pertaining to distribution of the
31 *             software without specific, written prior permission.
32 *             Transition Networks makes no representations about the
33 *             suitability of this software for any purpose.
34 *
35 *  COPYRIGHT (c) 1989-2001.
36 *  On-Line Applications Research Corporation (OAR).
37 *
38 *  The license and distribution terms for this file may be
39 *  found in the file LICENSE in this distribution or at
40 *  http://www.rtems.com/license/LICENSE.
41 *
42 *  $Id$
43 */
44
45#include <rtems/system.h>
46#include <rtems/score/isr.h>
47#include <rtems/score/wkspace.h>
48
49
50
51
52/*
53** Exception stack frame pointer used in cpu_asm to pass the exception stack frame
54** address to the context switch code.
55*/
56#if (__mips == 1) || (__mips == 32)
57typedef uint32_t ESF_PTR_TYPE;
58#elif (__mips == 3)
59typedef uint64_t ESF_PTR_TYPE;
60#else
61#error "unknown MIPS ISA"
62#endif
63
64ESF_PTR_TYPE __exceptionStackFrame = 0; 
65
66
67
68
69/*  _CPU_Initialize
70 *
71 *  This routine performs processor dependent initialization.
72 *
73 *  INPUT PARAMETERS:
74 *    cpu_table       - CPU table to initialize
75 *    thread_dispatch - address of disptaching routine
76 */
77
78
79void _CPU_Initialize(
80  rtems_cpu_table  *cpu_table,
81  void      (*thread_dispatch)      /* ignored on this CPU */
82)
83{
84  /*
85   *  If there is not an easy way to initialize the FP context
86   *  during Context_Initialize, then it is usually easier to
87   *  save an "uninitialized" FP context here and copy it to
88   *  the task's during Context_Initialize.
89   */
90
91#if CPU_HARDWARE_FP
92  /* FP context initialization support goes here */
93  _CPU_Null_fp_context.fpcs = 0x1000000;        /* Set FS flag in floating point coprocessor
94                                                   control register to prevent underflow and
95                                                   inexact exceptions */
96#endif
97}
98
99/*PAGE
100 *
101 *  _CPU_ISR_Get_level
102 *
103 *  This routine returns the current interrupt level.
104 */
105
106uint32_t   _CPU_ISR_Get_level( void )
107{
108  unsigned int sr;
109
110  mips_get_sr(sr);
111
112  /* printf("current sr=%08X, ",sr); */
113
114#if (__mips == 3) || (__mips == 32)
115/* IE bit and shift down hardware ints into bits 1 thru 6 */
116  sr = (sr & SR_IE) | ((sr & mips_interrupt_mask()) >> 9);
117
118#elif __mips == 1
119/* IEC bit and shift down hardware ints into bits 1 thru 6 */
120  sr = (sr & SR_IEC) | ((sr & mips_interrupt_mask()) >> 9);
121
122#else
123#error "CPU ISR level: unknown MIPS level for SR handling"
124#endif
125  return sr;
126}
127
128
129void _CPU_ISR_Set_level( uint32_t   new_level )
130{
131  unsigned int sr, srbits;
132
133  /*
134  ** mask off the int level bits only so we can
135  ** preserve software int settings and FP enable
136  ** for this thread.  Note we don't force software ints
137  ** enabled when changing level, they were turned on
138  ** when this task was created, but may have been turned
139  ** off since, so we'll just leave them alone.
140  */
141
142  new_level &= 0xff;
143
144  mips_get_sr(sr);
145
146#if (__mips == 3) || (__mips == 32)
147  mips_set_sr( (sr & ~SR_IE) );                 /* first disable ie bit (recommended) */
148
149   srbits = sr & ~(0xfc00 | SR_IE);
150
151   sr = srbits | ((new_level==0)? (mips_interrupt_mask() | SR_IE): \
152                 (((new_level<<9) & mips_interrupt_mask()) | \
153                   ((new_level & 1)?SR_IE:0)));
154/*
155  if ( (new_level & SR_EXL) == (sr & SR_EXL) )
156    return;
157
158  if ( (new_level & SR_EXL) == 0 ) {
159    sr &= ~SR_EXL;                    * clear the EXL bit *
160    mips_set_sr(sr);
161  } else {
162
163    sr |= SR_EXL|SR_IE;              * enable exception level *
164    mips_set_sr(sr);                 * first disable ie bit (recommended) *
165  }
166*/
167 
168#elif __mips == 1
169  mips_set_sr( (sr & ~SR_IEC) );
170  srbits = sr & ~(0xfc00 | SR_IEC);
171  sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc00) | \
172                                         (new_level & SR_IEC)));
173#else
174#error "CPU ISR level: unknown MIPS level for SR handling"
175#endif
176  mips_set_sr( sr );
177}
178
179
180
181/*PAGE
182 *
183 *  _CPU_ISR_install_raw_handler
184 *
185 *  Input parameters:
186 *    vector      - interrupt vector number
187 *    old_handler - former ISR for this vector number
188 *    new_handler - replacement ISR for this vector number
189 *
190 *  Output parameters:  NONE
191 *
192 */
193 
194void _CPU_ISR_install_raw_handler(
195  uint32_t    vector,
196  proc_ptr    new_handler,
197  proc_ptr   *old_handler
198)
199{
200  /*
201   *  This is where we install the interrupt handler into the "raw" interrupt
202   *  table used by the CPU to dispatch interrupt handlers.
203   *
204   *  Because all interrupts are vectored through the same exception handler
205   *  this is not necessary on thi sport.
206   */
207}
208
209/*PAGE
210 *
211 *  _CPU_ISR_install_vector
212 *
213 *  This kernel routine installs the RTEMS handler for the
214 *  specified vector.
215 *
216 *  Input parameters:
217 *    vector      - interrupt vector number
218 *    old_handler - former ISR for this vector number
219 *    new_handler - replacement ISR for this vector number
220 *
221 *  Output parameters:  NONE
222 *
223 */
224
225void _CPU_ISR_install_vector(
226  uint32_t    vector,
227  proc_ptr    new_handler,
228  proc_ptr   *old_handler
229)
230{
231   *old_handler = _ISR_Vector_table[ vector ];
232
233   /*
234    *  If the interrupt vector table is a table of pointer to isr entry
235    *  points, then we need to install the appropriate RTEMS interrupt
236    *  handler for this vector number.
237    */
238
239   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
240
241   /*
242    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
243    *  be used by the _ISR_Handler so the user gets control.
244    */
245
246    _ISR_Vector_table[ vector ] = new_handler;
247}
248
249/*PAGE
250 *
251 *  _CPU_Install_interrupt_stack
252 */
253
254void _CPU_Install_interrupt_stack( void )
255{
256/* we don't support this yet */
257}
258
259/*PAGE
260 *
261 *  _CPU_Internal_threads_Idle_thread_body
262 *
263 *  NOTES:
264 *
265 *  1. This is the same as the regular CPU independent algorithm.
266 *
267 *  2. If you implement this using a "halt", "idle", or "shutdown"
268 *     instruction, then don't forget to put it in an infinite loop.
269 *
270 *  3. Be warned. Some processors with onboard DMA have been known
271 *     to stop the DMA if the CPU were put in IDLE mode.  This might
272 *     also be a problem with other on-chip peripherals.  So use this
273 *     hook with caution.
274 */
275
276void _CPU_Thread_Idle_body( void )
277{
278#if (__mips == 3) || (__mips == 32)
279   for( ; ; )
280     asm volatile("wait"); /* use wait to enter low power mode */
281#elif __mips == 1
282   for( ; ; )
283     ;
284#else
285#error "IDLE: __mips not set to 1 or 3"
286#endif
287}
Note: See TracBrowser for help on using the repository browser.