1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief MIPS CPU Dependent Source |
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5 | */ |
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6 | |
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7 | /* |
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8 | * MIPS CPU Dependent Source |
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9 | * |
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10 | * 2002: Greg Menke (gregory.menke@gsfc.nasa.gov) |
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11 | * Overhauled interrupt level and interrupt enable/disable code |
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12 | * to more exactly support MIPS. Our mods were for MIPS1 processors |
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13 | * MIPS3 ports are affected, though apps written to the old behavior |
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14 | * should still work OK. |
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15 | * |
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16 | * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and |
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17 | * Joel Sherrill <joel@OARcorp.com>. |
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18 | * |
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19 | * These changes made the code conditional on standard cpp predefines, |
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20 | * merged the mips1 and mips3 code sequences as much as possible, |
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21 | * and moved some of the assembly code to C. Alan did much of the |
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22 | * initial analysis and rework. Joel took over from there and |
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23 | * wrote the JMR3904 BSP so this could be tested. Joel also |
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24 | * added the new interrupt vectoring support in libcpu and |
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25 | * tried to better support the various interrupt controllers. |
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26 | * |
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27 | * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> |
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28 | * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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29 | * |
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30 | * To anyone who acknowledges that this file is provided "AS IS" |
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31 | * without any express or implied warranty: |
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32 | * permission to use, copy, modify, and distribute this file |
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33 | * for any purpose is hereby granted without fee, provided that |
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34 | * the above copyright notice and this notice appears in all |
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35 | * copies, and that the name of Transition Networks not be used in |
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36 | * advertising or publicity pertaining to distribution of the |
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37 | * software without specific, written prior permission. |
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38 | * Transition Networks makes no representations about the |
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39 | * suitability of this software for any purpose. |
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40 | * |
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41 | * COPYRIGHT (c) 1989-2012. |
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42 | * On-Line Applications Research Corporation (OAR). |
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43 | * |
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44 | * The license and distribution terms for this file may be |
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45 | * found in the file LICENSE in this distribution or at |
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46 | * http://www.rtems.org/license/LICENSE. |
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47 | */ |
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48 | |
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49 | #ifdef HAVE_CONFIG_H |
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50 | #include "config.h" |
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51 | #endif |
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52 | |
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53 | #include <rtems/score/isr.h> |
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54 | #include <rtems/score/wkspace.h> |
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55 | |
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56 | #if CPU_HARDWARE_FP |
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57 | Context_Control_fp _CPU_Null_fp_context; |
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58 | #endif |
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59 | |
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60 | /* |
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61 | ** Exception stack frame pointer used in cpu_asm to pass the exception stack frame |
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62 | ** address to the context switch code. |
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63 | */ |
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64 | #if (__mips == 1) || (__mips == 32) |
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65 | typedef uint32_t ESF_PTR_TYPE; |
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66 | #elif (__mips == 3) |
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67 | typedef uint64_t ESF_PTR_TYPE; |
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68 | #else |
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69 | #error "unknown MIPS ISA" |
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70 | #endif |
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71 | |
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72 | ESF_PTR_TYPE __exceptionStackFrame = 0; |
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73 | /* _CPU_Initialize |
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74 | * |
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75 | * This routine performs processor dependent initialization. |
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76 | * |
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77 | * thread_dispatch - address of dispatching routine |
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78 | */ |
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79 | |
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80 | void _CPU_Initialize(void) |
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81 | { |
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82 | /* |
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83 | * If there is not an easy way to initialize the FP context |
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84 | * during Context_Initialize, then it is usually easier to |
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85 | * save an "uninitialized" FP context here and copy it to |
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86 | * the task's during Context_Initialize. |
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87 | */ |
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88 | |
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89 | #if CPU_HARDWARE_FP |
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90 | /* FP context initialization support goes here */ |
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91 | _CPU_Null_fp_context.fpcs = 0x1000000; /* Set FS flag in floating point coprocessor |
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92 | control register to prevent underflow and |
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93 | inexact exceptions */ |
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94 | #endif |
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95 | } |
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96 | |
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97 | uint32_t _CPU_ISR_Get_level( void ) |
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98 | { |
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99 | unsigned int sr; |
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100 | |
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101 | mips_get_sr(sr); |
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102 | |
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103 | /* printf("current sr=%08X, ",sr); */ |
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104 | |
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105 | #if (__mips == 3) || (__mips == 32) |
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106 | /* IE bit and shift down hardware ints into bits 1 thru 6 */ |
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107 | sr = (sr & SR_IE) | ((sr & mips_interrupt_mask()) >> 9); |
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108 | |
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109 | #elif __mips == 1 |
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110 | /* IEC bit and shift down hardware ints into bits 1 thru 6 */ |
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111 | sr = (sr & SR_IEC) | ((sr & mips_interrupt_mask()) >> 9); |
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112 | |
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113 | #else |
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114 | #error "CPU ISR level: unknown MIPS level for SR handling" |
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115 | #endif |
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116 | return sr; |
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117 | } |
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118 | void _CPU_ISR_Set_level( uint32_t new_level ) |
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119 | { |
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120 | unsigned int sr, srbits; |
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121 | |
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122 | /* |
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123 | ** mask off the int level bits only so we can |
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124 | ** preserve software int settings and FP enable |
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125 | ** for this thread. Note we don't force software ints |
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126 | ** enabled when changing level, they were turned on |
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127 | ** when this task was created, but may have been turned |
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128 | ** off since, so we'll just leave them alone. |
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129 | */ |
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130 | |
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131 | new_level &= 0xff; |
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132 | |
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133 | mips_get_sr(sr); |
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134 | |
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135 | #if (__mips == 3) || (__mips == 32) |
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136 | mips_set_sr( (sr & ~SR_IE) ); /* first disable ie bit (recommended) */ |
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137 | |
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138 | srbits = sr & ~(0xfc00 | SR_IE); |
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139 | |
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140 | sr = srbits | ((new_level==0)? (mips_interrupt_mask() | SR_IE): \ |
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141 | (((new_level<<9) & mips_interrupt_mask()) | \ |
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142 | ((new_level & 1)?SR_IE:0))); |
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143 | /* |
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144 | if ( (new_level & SR_EXL) == (sr & SR_EXL) ) |
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145 | return; |
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146 | |
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147 | if ( (new_level & SR_EXL) == 0 ) { |
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148 | sr &= ~SR_EXL; * clear the EXL bit * |
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149 | mips_set_sr(sr); |
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150 | } else { |
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151 | |
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152 | sr |= SR_EXL|SR_IE; * enable exception level * |
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153 | mips_set_sr(sr); * first disable ie bit (recommended) * |
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154 | } |
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155 | */ |
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156 | |
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157 | #elif __mips == 1 |
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158 | mips_set_sr( (sr & ~SR_IEC) ); |
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159 | srbits = sr & ~(0xfc00 | SR_IEC); |
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160 | sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc00) | \ |
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161 | (new_level & SR_IEC))); |
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162 | #else |
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163 | #error "CPU ISR level: unknown MIPS level for SR handling" |
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164 | #endif |
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165 | mips_set_sr( sr ); |
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166 | } |
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167 | |
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168 | void _CPU_Context_Initialize( |
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169 | Context_Control *the_context, |
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170 | uintptr_t *stack_base, |
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171 | uint32_t size, |
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172 | uint32_t new_level, |
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173 | void *entry_point, |
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174 | bool is_fp, |
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175 | void *tls_area |
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176 | ) |
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177 | { |
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178 | uintptr_t stack_tmp; |
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179 | __MIPS_REGISTER_TYPE intlvl = new_level & 0xff; |
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180 | __MIPS_REGISTER_TYPE c0_sr; |
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181 | |
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182 | stack_tmp = (uintptr_t)stack_base; |
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183 | stack_tmp += ((size) - CPU_STACK_ALIGNMENT); |
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184 | stack_tmp &= (__MIPS_REGISTER_TYPE) ~(CPU_STACK_ALIGNMENT - 1); |
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185 | |
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186 | the_context->sp = (__MIPS_REGISTER_TYPE) stack_tmp; |
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187 | the_context->fp = (__MIPS_REGISTER_TYPE) stack_tmp; |
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188 | the_context->ra = (__MIPS_REGISTER_TYPE) (uintptr_t)entry_point; |
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189 | |
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190 | c0_sr = |
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191 | ((intlvl==0)? (mips_interrupt_mask() | 0x300 | _INTON): |
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192 | ( ((intlvl<<9) & mips_interrupt_mask()) | 0x300 | |
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193 | ((intlvl & 1)?_INTON:0)) ) | |
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194 | SR_CU0 | _EXTRABITS; |
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195 | #if MIPS_HAS_FPU == 1 |
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196 | if ( is_fp ) { |
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197 | c0_sr |= SR_CU1; |
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198 | } |
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199 | #endif |
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200 | the_context->c0_sr = c0_sr; |
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201 | } |
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202 | /* |
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203 | * _CPU_Internal_threads_Idle_thread_body |
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204 | * |
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205 | * NOTES: |
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206 | * |
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207 | * 1. This is the same as the regular CPU independent algorithm. |
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208 | * |
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209 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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210 | * instruction, then don't forget to put it in an infinite loop. |
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211 | * |
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212 | * 3. Be warned. Some processors with onboard DMA have been known |
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213 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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214 | * also be a problem with other on-chip peripherals. So use this |
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215 | * hook with caution. |
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216 | */ |
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217 | |
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218 | void *_CPU_Thread_Idle_body( uintptr_t ignored ) |
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219 | { |
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220 | #if (__mips == 3) || (__mips == 32) |
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221 | for( ; ; ) |
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222 | __asm__ volatile("wait"); /* use wait to enter low power mode */ |
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223 | #elif __mips == 1 |
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224 | for( ; ; ) |
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225 | ; |
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226 | #else |
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227 | #error "IDLE: __mips not set to 1 or 3" |
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228 | #endif |
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229 | } |
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