source: rtems/cpukit/score/cpu/mips/cpu.c @ 3c87adba

4.104.114.95
Last change on this file since 3c87adba was 3c87adba, checked in by Joel Sherrill <joel.sherrill@…>, on 07/31/08 at 14:55:56

2008-07-31 Joel Sherrill <joel.sherrill@…>

  • cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads.
  • Property mode set to 100644
File size: 7.6 KB
Line 
1/*
2 *  Mips CPU Dependent Source
3 *
4 *  2002:       Greg Menke (gregory.menke@gsfc.nasa.gov)
5 *      Overhauled interrupt level and interrupt enable/disable code
6 *      to more exactly support MIPS.  Our mods were for MIPS1 processors
7 *      MIPS3 ports are affected, though apps written to the old behavior
8 *      should still work OK.
9 *
10 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
11 *           Joel Sherrill <joel@OARcorp.com>.
12 *
13 *    These changes made the code conditional on standard cpp predefines,
14 *    merged the mips1 and mips3 code sequences as much as possible,
15 *    and moved some of the assembly code to C.  Alan did much of the
16 *    initial analysis and rework.  Joel took over from there and
17 *    wrote the JMR3904 BSP so this could be tested.  Joel also
18 *    added the new interrupt vectoring support in libcpu and
19 *    tried to better support the various interrupt controllers.
20 *
21 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
22 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
23 *
24 *         To anyone who acknowledges that this file is provided "AS IS"
25 *         without any express or implied warranty:
26 *             permission to use, copy, modify, and distribute this file
27 *             for any purpose is hereby granted without fee, provided that
28 *             the above copyright notice and this notice appears in all
29 *             copies, and that the name of Transition Networks not be used in
30 *             advertising or publicity pertaining to distribution of the
31 *             software without specific, written prior permission.
32 *             Transition Networks makes no representations about the
33 *             suitability of this software for any purpose.
34 *
35 *  COPYRIGHT (c) 1989-2001.
36 *  On-Line Applications Research Corporation (OAR).
37 *
38 *  The license and distribution terms for this file may be
39 *  found in the file LICENSE in this distribution or at
40 *  http://www.rtems.com/license/LICENSE.
41 *
42 *  $Id$
43 */
44
45#include <rtems/system.h>
46#include <rtems/score/isr.h>
47#include <rtems/score/wkspace.h>
48
49
50
51
52/*
53** Exception stack frame pointer used in cpu_asm to pass the exception stack frame
54** address to the context switch code.
55*/
56#if (__mips == 1) || (__mips == 32)
57typedef uint32_t ESF_PTR_TYPE;
58#elif (__mips == 3)
59typedef uint64_t ESF_PTR_TYPE;
60#else
61#error "unknown MIPS ISA"
62#endif
63
64ESF_PTR_TYPE __exceptionStackFrame = 0;
65
66
67
68
69/*  _CPU_Initialize
70 *
71 *  This routine performs processor dependent initialization.
72 *
73 *  INPUT PARAMETERS:
74 *    thread_dispatch - address of disptaching routine
75 */
76void _CPU_Initialize(
77  void      (*thread_dispatch)      /* ignored on this CPU */
78)
79{
80  /*
81   *  If there is not an easy way to initialize the FP context
82   *  during Context_Initialize, then it is usually easier to
83   *  save an "uninitialized" FP context here and copy it to
84   *  the task's during Context_Initialize.
85   */
86
87#if CPU_HARDWARE_FP
88  /* FP context initialization support goes here */
89  _CPU_Null_fp_context.fpcs = 0x1000000;        /* Set FS flag in floating point coprocessor
90                                                   control register to prevent underflow and
91                                                   inexact exceptions */
92#endif
93}
94
95/*PAGE
96 *
97 *  _CPU_ISR_Get_level
98 *
99 *  This routine returns the current interrupt level.
100 */
101
102uint32_t   _CPU_ISR_Get_level( void )
103{
104  unsigned int sr;
105
106  mips_get_sr(sr);
107
108  /* printf("current sr=%08X, ",sr); */
109
110#if (__mips == 3) || (__mips == 32)
111/* IE bit and shift down hardware ints into bits 1 thru 6 */
112  sr = (sr & SR_IE) | ((sr & mips_interrupt_mask()) >> 9);
113
114#elif __mips == 1
115/* IEC bit and shift down hardware ints into bits 1 thru 6 */
116  sr = (sr & SR_IEC) | ((sr & mips_interrupt_mask()) >> 9);
117
118#else
119#error "CPU ISR level: unknown MIPS level for SR handling"
120#endif
121  return sr;
122}
123
124
125void _CPU_ISR_Set_level( uint32_t   new_level )
126{
127  unsigned int sr, srbits;
128
129  /*
130  ** mask off the int level bits only so we can
131  ** preserve software int settings and FP enable
132  ** for this thread.  Note we don't force software ints
133  ** enabled when changing level, they were turned on
134  ** when this task was created, but may have been turned
135  ** off since, so we'll just leave them alone.
136  */
137
138  new_level &= 0xff;
139
140  mips_get_sr(sr);
141
142#if (__mips == 3) || (__mips == 32)
143  mips_set_sr( (sr & ~SR_IE) );                 /* first disable ie bit (recommended) */
144
145   srbits = sr & ~(0xfc00 | SR_IE);
146
147   sr = srbits | ((new_level==0)? (mips_interrupt_mask() | SR_IE): \
148                 (((new_level<<9) & mips_interrupt_mask()) | \
149                   ((new_level & 1)?SR_IE:0)));
150/*
151  if ( (new_level & SR_EXL) == (sr & SR_EXL) )
152    return;
153
154  if ( (new_level & SR_EXL) == 0 ) {
155    sr &= ~SR_EXL;                    * clear the EXL bit *
156    mips_set_sr(sr);
157  } else {
158
159    sr |= SR_EXL|SR_IE;              * enable exception level *
160    mips_set_sr(sr);                 * first disable ie bit (recommended) *
161  }
162*/
163 
164#elif __mips == 1
165  mips_set_sr( (sr & ~SR_IEC) );
166  srbits = sr & ~(0xfc00 | SR_IEC);
167  sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc00) | \
168                                         (new_level & SR_IEC)));
169#else
170#error "CPU ISR level: unknown MIPS level for SR handling"
171#endif
172  mips_set_sr( sr );
173}
174
175
176
177/*PAGE
178 *
179 *  _CPU_ISR_install_raw_handler
180 *
181 *  Input parameters:
182 *    vector      - interrupt vector number
183 *    old_handler - former ISR for this vector number
184 *    new_handler - replacement ISR for this vector number
185 *
186 *  Output parameters:  NONE
187 *
188 */
189 
190void _CPU_ISR_install_raw_handler(
191  uint32_t    vector,
192  proc_ptr    new_handler,
193  proc_ptr   *old_handler
194)
195{
196  /*
197   *  This is where we install the interrupt handler into the "raw" interrupt
198   *  table used by the CPU to dispatch interrupt handlers.
199   *
200   *  Because all interrupts are vectored through the same exception handler
201   *  this is not necessary on thi sport.
202   */
203}
204
205/*PAGE
206 *
207 *  _CPU_ISR_install_vector
208 *
209 *  This kernel routine installs the RTEMS handler for the
210 *  specified vector.
211 *
212 *  Input parameters:
213 *    vector      - interrupt vector number
214 *    old_handler - former ISR for this vector number
215 *    new_handler - replacement ISR for this vector number
216 *
217 *  Output parameters:  NONE
218 *
219 */
220
221void _CPU_ISR_install_vector(
222  uint32_t    vector,
223  proc_ptr    new_handler,
224  proc_ptr   *old_handler
225)
226{
227   *old_handler = _ISR_Vector_table[ vector ];
228
229   /*
230    *  If the interrupt vector table is a table of pointer to isr entry
231    *  points, then we need to install the appropriate RTEMS interrupt
232    *  handler for this vector number.
233    */
234
235   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
236
237   /*
238    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
239    *  be used by the _ISR_Handler so the user gets control.
240    */
241
242    _ISR_Vector_table[ vector ] = new_handler;
243}
244
245/*PAGE
246 *
247 *  _CPU_Install_interrupt_stack
248 */
249
250void _CPU_Install_interrupt_stack( void )
251{
252/* we don't support this yet */
253}
254
255/*PAGE
256 *
257 *  _CPU_Internal_threads_Idle_thread_body
258 *
259 *  NOTES:
260 *
261 *  1. This is the same as the regular CPU independent algorithm.
262 *
263 *  2. If you implement this using a "halt", "idle", or "shutdown"
264 *     instruction, then don't forget to put it in an infinite loop.
265 *
266 *  3. Be warned. Some processors with onboard DMA have been known
267 *     to stop the DMA if the CPU were put in IDLE mode.  This might
268 *     also be a problem with other on-chip peripherals.  So use this
269 *     hook with caution.
270 */
271
272void *_CPU_Thread_Idle_body( uint32_t ignored )
273{
274#if (__mips == 3) || (__mips == 32)
275   for( ; ; )
276     asm volatile("wait"); /* use wait to enter low power mode */
277#elif __mips == 1
278   for( ; ; )
279     ;
280#else
281#error "IDLE: __mips not set to 1 or 3"
282#endif
283}
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