source: rtems/cpukit/score/cpu/mips/cpu.c

Last change on this file was 8b65b574, checked in by Sebastian Huber <sebastian.huber@…>, on Jul 28, 2021 at 12:41:32 PM

score: Canonicalize _CPU_Fatal_halt()

Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it
is a proper declaration of a function which does not return. Fix the type of
the error code. If necessary, add the implementation to cpu.c. Implementing
_CPU_Fatal_halt() as a function makes it possible to wrap this function for
example to fully test _Terminate().

  • Property mode set to 100644
File size: 7.0 KB
Line 
1/**
2 *  @file
3 *
4 *  @brief MIPS CPU Dependent Source
5 */
6
7/*
8 * MIPS CPU Dependent Source
9 *
10 *  2002:       Greg Menke (gregory.menke@gsfc.nasa.gov)
11 *      Overhauled interrupt level and interrupt enable/disable code
12 *      to more exactly support MIPS.  Our mods were for MIPS1 processors
13 *      MIPS3 ports are affected, though apps written to the old behavior
14 *      should still work OK.
15 *
16 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
17 *           Joel Sherrill <joel@OARcorp.com>.
18 *
19 *    These changes made the code conditional on standard cpp predefines,
20 *    merged the mips1 and mips3 code sequences as much as possible,
21 *    and moved some of the assembly code to C.  Alan did much of the
22 *    initial analysis and rework.  Joel took over from there and
23 *    wrote the JMR3904 BSP so this could be tested.  Joel also
24 *    added the new interrupt vectoring support in libcpu and
25 *    tried to better support the various interrupt controllers.
26 *
27 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
28 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
29 *
30 *         To anyone who acknowledges that this file is provided "AS IS"
31 *         without any express or implied warranty:
32 *             permission to use, copy, modify, and distribute this file
33 *             for any purpose is hereby granted without fee, provided that
34 *             the above copyright notice and this notice appears in all
35 *             copies, and that the name of Transition Networks not be used in
36 *             advertising or publicity pertaining to distribution of the
37 *             software without specific, written prior permission.
38 *             Transition Networks makes no representations about the
39 *             suitability of this software for any purpose.
40 *
41 *  COPYRIGHT (c) 1989-2012.
42 *  On-Line Applications Research Corporation (OAR).
43 *
44 *  The license and distribution terms for this file may be
45 *  found in the file LICENSE in this distribution or at
46 *  http://www.rtems.org/license/LICENSE.
47 */
48
49#ifdef HAVE_CONFIG_H
50#include "config.h"
51#endif
52
53#include <rtems/score/cpuimpl.h>
54#include <rtems/score/isr.h>
55
56#if CPU_HARDWARE_FP
57Context_Control_fp _CPU_Null_fp_context;
58#endif
59
60/*
61** Exception stack frame pointer used in cpu_asm to pass the exception stack frame
62** address to the context switch code.
63*/
64#if (__mips == 1) || (__mips == 32)
65typedef uint32_t ESF_PTR_TYPE;
66#elif (__mips == 3)
67typedef uint64_t ESF_PTR_TYPE;
68#else
69#error "unknown MIPS ISA"
70#endif
71
72ESF_PTR_TYPE __exceptionStackFrame = 0;
73/*  _CPU_Initialize
74 *
75 *  This routine performs processor dependent initialization.
76 *
77 *    thread_dispatch - address of dispatching routine
78 */
79
80void _CPU_Initialize(void)
81{
82  /*
83   *  If there is not an easy way to initialize the FP context
84   *  during Context_Initialize, then it is usually easier to
85   *  save an "uninitialized" FP context here and copy it to
86   *  the task's during Context_Initialize.
87   */
88
89#if CPU_HARDWARE_FP
90  /* FP context initialization support goes here */
91  _CPU_Null_fp_context.fpcs = 0x1000000;        /* Set FS flag in floating point coprocessor
92                                                   control register to prevent underflow and
93                                                   inexact exceptions */
94#endif
95}
96
97void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
98{
99  ISR_Level level;
100
101  _CPU_ISR_Disable( level );
102  (void) level;
103
104  while ( true ) {
105    /* Do nothing */
106  }
107}
108
109uint32_t   _CPU_ISR_Get_level( void )
110{
111  unsigned int sr;
112
113  mips_get_sr(sr);
114
115  /* printf("current sr=%08X, ",sr); */
116
117#if (__mips == 3) || (__mips == 32)
118/* IE bit and shift down hardware ints into bits 1 thru 6 */
119  sr = (sr & SR_IE) | ((sr & mips_interrupt_mask()) >> 9);
120
121#elif __mips == 1
122/* IEC bit and shift down hardware ints into bits 1 thru 6 */
123  sr = (sr & SR_IEC) | ((sr & mips_interrupt_mask()) >> 9);
124
125#else
126#error "CPU ISR level: unknown MIPS level for SR handling"
127#endif
128  return sr;
129}
130void _CPU_ISR_Set_level( uint32_t   new_level )
131{
132  unsigned int sr, srbits;
133
134  /*
135  ** mask off the int level bits only so we can
136  ** preserve software int settings and FP enable
137  ** for this thread.  Note we don't force software ints
138  ** enabled when changing level, they were turned on
139  ** when this task was created, but may have been turned
140  ** off since, so we'll just leave them alone.
141  */
142
143  new_level &= 0xff;
144
145  mips_get_sr(sr);
146
147#if (__mips == 3) || (__mips == 32)
148  mips_set_sr( (sr & ~SR_IE) );                 /* first disable ie bit (recommended) */
149
150   srbits = sr & ~(0xfc00 | SR_IE);
151
152   sr = srbits | ((new_level==0)? (mips_interrupt_mask() | SR_IE): \
153                 (((new_level<<9) & mips_interrupt_mask()) | \
154                   ((new_level & 1)?SR_IE:0)));
155/*
156  if ( (new_level & SR_EXL) == (sr & SR_EXL) )
157    return;
158
159  if ( (new_level & SR_EXL) == 0 ) {
160    sr &= ~SR_EXL;                    * clear the EXL bit *
161    mips_set_sr(sr);
162  } else {
163
164    sr |= SR_EXL|SR_IE;              * enable exception level *
165    mips_set_sr(sr);                 * first disable ie bit (recommended) *
166  }
167*/
168
169#elif __mips == 1
170  mips_set_sr( (sr & ~SR_IEC) );
171  srbits = sr & ~(0xfc00 | SR_IEC);
172  sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc00) | \
173                                         (new_level & SR_IEC)));
174#else
175#error "CPU ISR level: unknown MIPS level for SR handling"
176#endif
177  mips_set_sr( sr );
178}
179
180void _CPU_Context_Initialize(
181  Context_Control  *the_context,
182  uintptr_t        *stack_base,
183  uint32_t          size,
184  uint32_t          new_level,
185  void             *entry_point,
186  bool              is_fp,
187  void             *tls_area
188)
189{
190  uintptr_t             stack_tmp;
191  __MIPS_REGISTER_TYPE  intlvl = new_level & 0xff;
192  __MIPS_REGISTER_TYPE  c0_sr;
193
194  stack_tmp  = (uintptr_t)stack_base;
195  stack_tmp += ((size) - CPU_STACK_ALIGNMENT);
196  stack_tmp &= (__MIPS_REGISTER_TYPE) ~(CPU_STACK_ALIGNMENT - 1);
197
198  the_context->sp = (__MIPS_REGISTER_TYPE) stack_tmp;
199  the_context->fp = (__MIPS_REGISTER_TYPE) stack_tmp;
200  the_context->ra = (__MIPS_REGISTER_TYPE) (uintptr_t)entry_point;
201
202  c0_sr =
203    ((intlvl==0)? (mips_interrupt_mask() | 0x300 | _INTON):
204      ( ((intlvl<<9) & mips_interrupt_mask()) | 0x300 |
205      ((intlvl & 1)?_INTON:0)) ) |
206      SR_CU0 | _EXTRABITS;
207#if MIPS_HAS_FPU == 1
208  if ( is_fp ) {
209    c0_sr |= SR_CU1;
210  }
211#endif
212  the_context->c0_sr = c0_sr;
213}
214/*
215 *  _CPU_Internal_threads_Idle_thread_body
216 *
217 *  NOTES:
218 *
219 *  1. This is the same as the regular CPU independent algorithm.
220 *
221 *  2. If you implement this using a "halt", "idle", or "shutdown"
222 *     instruction, then don't forget to put it in an infinite loop.
223 *
224 *  3. Be warned. Some processors with onboard DMA have been known
225 *     to stop the DMA if the CPU were put in IDLE mode.  This might
226 *     also be a problem with other on-chip peripherals.  So use this
227 *     hook with caution.
228 */
229
230void *_CPU_Thread_Idle_body( uintptr_t ignored )
231{
232#if (__mips == 3) || (__mips == 32)
233   for( ; ; )
234     __asm__ volatile("wait"); /* use wait to enter low power mode */
235#elif __mips == 1
236   for( ; ; )
237     ;
238#else
239#error "IDLE: __mips not set to 1 or 3"
240#endif
241}
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