[f198c63] | 1 | /* |
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| 2 | * Mips CPU Dependent Source |
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| 3 | * |
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[bd1ecb0] | 4 | * 2002: Greg Menke (gregory.menke@gsfc.nasa.gov) |
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| 5 | * Overhauled interrupt level and interrupt enable/disable code |
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| 6 | * to more exactly support MIPS. Our mods were for MIPS1 processors |
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| 7 | * MIPS3 ports are affected, though apps written to the old behavior |
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| 8 | * should still work OK. |
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| 9 | * |
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[fda47cd] | 10 | * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and |
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[aa7f8a1f] | 11 | * Joel Sherrill <joel@OARcorp.com>. |
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| 12 | * |
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| 13 | * These changes made the code conditional on standard cpp predefines, |
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| 14 | * merged the mips1 and mips3 code sequences as much as possible, |
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| 15 | * and moved some of the assembly code to C. Alan did much of the |
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| 16 | * initial analysis and rework. Joel took over from there and |
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| 17 | * wrote the JMR3904 BSP so this could be tested. Joel also |
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| 18 | * added the new interrupt vectoring support in libcpu and |
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| 19 | * tried to better support the various interrupt controllers. |
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[f198c63] | 20 | * |
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[fda47cd] | 21 | * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> |
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| 22 | * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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[f198c63] | 23 | * |
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[fda47cd] | 24 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 25 | * without any express or implied warranty: |
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| 26 | * permission to use, copy, modify, and distribute this file |
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| 27 | * for any purpose is hereby granted without fee, provided that |
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| 28 | * the above copyright notice and this notice appears in all |
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| 29 | * copies, and that the name of Transition Networks not be used in |
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| 30 | * advertising or publicity pertaining to distribution of the |
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| 31 | * software without specific, written prior permission. |
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| 32 | * Transition Networks makes no representations about the |
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| 33 | * suitability of this software for any purpose. |
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[f198c63] | 34 | * |
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[aa7f8a1f] | 35 | * COPYRIGHT (c) 1989-2001. |
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[f198c63] | 36 | * On-Line Applications Research Corporation (OAR). |
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| 37 | * |
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[98e4ebf5] | 38 | * The license and distribution terms for this file may be |
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| 39 | * found in the file LICENSE in this distribution or at |
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[5356c03] | 40 | * http://www.rtems.com/license/LICENSE. |
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[f198c63] | 41 | * |
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[cda277f] | 42 | * $Id$ |
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[f198c63] | 43 | */ |
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| 44 | |
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| 45 | #include <rtems/system.h> |
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| 46 | #include <rtems/score/isr.h> |
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| 47 | #include <rtems/score/wkspace.h> |
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| 48 | |
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| 49 | |
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[8264d23] | 50 | |
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| 51 | |
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| 52 | /* |
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| 53 | ** local dword used in cpu_asm to pass the exception stack frame to the |
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| 54 | ** context switch code. |
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| 55 | */ |
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| 56 | unsigned __exceptionStackFrame = 0; |
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| 57 | |
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| 58 | |
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| 59 | |
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| 60 | |
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| 61 | |
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[f198c63] | 62 | /* _CPU_Initialize |
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| 63 | * |
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| 64 | * This routine performs processor dependent initialization. |
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| 65 | * |
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| 66 | * INPUT PARAMETERS: |
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| 67 | * cpu_table - CPU table to initialize |
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| 68 | * thread_dispatch - address of disptaching routine |
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| 69 | */ |
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| 70 | |
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| 71 | |
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| 72 | void _CPU_Initialize( |
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| 73 | rtems_cpu_table *cpu_table, |
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| 74 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 75 | ) |
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| 76 | { |
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| 77 | /* |
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| 78 | * If there is not an easy way to initialize the FP context |
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| 79 | * during Context_Initialize, then it is usually easier to |
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| 80 | * save an "uninitialized" FP context here and copy it to |
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| 81 | * the task's during Context_Initialize. |
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| 82 | */ |
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| 83 | |
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| 84 | /* FP context initialization support goes here */ |
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| 85 | |
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| 86 | _CPU_Table = *cpu_table; |
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| 87 | } |
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| 88 | |
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| 89 | /*PAGE |
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| 90 | * |
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| 91 | * _CPU_ISR_Get_level |
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[32f415d] | 92 | * |
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| 93 | * This routine returns the current interrupt level. |
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[f198c63] | 94 | */ |
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[bd1ecb0] | 95 | |
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[c346f33d] | 96 | uint32_t _CPU_ISR_Get_level( void ) |
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[f198c63] | 97 | { |
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[32f415d] | 98 | unsigned int sr; |
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| 99 | |
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| 100 | mips_get_sr(sr); |
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| 101 | |
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[c181345] | 102 | /* printf("current sr=%08X, ",sr); */ |
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[bd1ecb0] | 103 | |
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[2e549dad] | 104 | #if __mips == 3 |
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[e6dec71c] | 105 | /* EXL bit and shift down hardware ints into bits 1 thru 6 */ |
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[bd1ecb0] | 106 | sr = ((sr & SR_EXL) >> 1) | ((sr & 0xfc00) >> 9); |
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[2e549dad] | 107 | |
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| 108 | #elif __mips == 1 |
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[e6dec71c] | 109 | /* IEC bit and shift down hardware ints into bits 1 thru 6 */ |
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[bd1ecb0] | 110 | sr = (sr & SR_IEC) | ((sr & 0xfc00) >> 9); |
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[2e549dad] | 111 | |
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| 112 | #else |
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| 113 | #error "CPU ISR level: unknown MIPS level for SR handling" |
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| 114 | #endif |
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[c181345] | 115 | /* printf("intlevel=%02X\n",sr); */ |
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[bd1ecb0] | 116 | return sr; |
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[f198c63] | 117 | } |
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[2e549dad] | 118 | |
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[e6dec71c] | 119 | |
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[c346f33d] | 120 | void _CPU_ISR_Set_level( uint32_t new_level ) |
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[2e549dad] | 121 | { |
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[e6dec71c] | 122 | unsigned int sr, srbits; |
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| 123 | |
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| 124 | /* |
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| 125 | ** mask off the int level bits only so we can |
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| 126 | ** preserve software int settings and FP enable |
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| 127 | ** for this thread. Note we don't force software ints |
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| 128 | ** enabled when changing level, they were turned on |
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| 129 | ** when this task was created, but may have been turned |
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| 130 | ** off since, so we'll just leave them alone. |
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| 131 | */ |
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| 132 | |
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[bd1ecb0] | 133 | new_level &= 0xff; |
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[2e549dad] | 134 | |
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| 135 | mips_get_sr(sr); |
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| 136 | |
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| 137 | #if __mips == 3 |
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[bd1ecb0] | 138 | mips_set_sr( (sr & ~SR_IE) ); /* first disable ie bit (recommended) */ |
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[e6dec71c] | 139 | |
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| 140 | srbits = sr & ~(0xfc00 | SR_EXL | SR_IE); |
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| 141 | |
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| 142 | sr = srbits | ((new_level==0)? (0xfc00 | SR_EXL | SR_IE): \ |
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[bd1ecb0] | 143 | (((new_level<<9) & 0xfc00) | \ |
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[e6dec71c] | 144 | (new_level & 1)?(SR_EXL | SR_IE):0)); |
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| 145 | /* |
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[2e549dad] | 146 | if ( (new_level & SR_EXL) == (sr & SR_EXL) ) |
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| 147 | return; |
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| 148 | |
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| 149 | if ( (new_level & SR_EXL) == 0 ) { |
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[e6dec71c] | 150 | sr &= ~SR_EXL; * clear the EXL bit * |
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[2e549dad] | 151 | mips_set_sr(sr); |
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| 152 | } else { |
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| 153 | |
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[e6dec71c] | 154 | sr |= SR_EXL|SR_IE; * enable exception level * |
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| 155 | mips_set_sr(sr); * first disable ie bit (recommended) * |
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[2e549dad] | 156 | } |
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[e6dec71c] | 157 | */ |
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[2e549dad] | 158 | |
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| 159 | #elif __mips == 1 |
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[bd1ecb0] | 160 | mips_set_sr( (sr & ~SR_IEC) ); |
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[e6dec71c] | 161 | srbits = sr & ~(0xfc00 | SR_IEC); |
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[bd1ecb0] | 162 | //printf("current sr=%08X, newlevel=%02X, srbits=%08X, ",sr,new_level,srbits); |
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| 163 | sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc00) | \ |
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| 164 | (new_level & SR_IEC))); |
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| 165 | //printf("new sr=%08X\n",sr); |
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[32f415d] | 166 | #else |
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| 167 | #error "CPU ISR level: unknown MIPS level for SR handling" |
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[f198c63] | 168 | #endif |
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[e6dec71c] | 169 | mips_set_sr( sr ); |
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[2e549dad] | 170 | } |
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| 171 | |
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[bd1ecb0] | 172 | |
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| 173 | |
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[f198c63] | 174 | /*PAGE |
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| 175 | * |
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| 176 | * _CPU_ISR_install_raw_handler |
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[aa7f8a1f] | 177 | * |
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| 178 | * Input parameters: |
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| 179 | * vector - interrupt vector number |
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| 180 | * old_handler - former ISR for this vector number |
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| 181 | * new_handler - replacement ISR for this vector number |
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| 182 | * |
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| 183 | * Output parameters: NONE |
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| 184 | * |
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[f198c63] | 185 | */ |
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| 186 | |
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| 187 | void _CPU_ISR_install_raw_handler( |
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[c346f33d] | 188 | uint32_t vector, |
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[f198c63] | 189 | proc_ptr new_handler, |
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| 190 | proc_ptr *old_handler |
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| 191 | ) |
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| 192 | { |
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| 193 | /* |
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| 194 | * This is where we install the interrupt handler into the "raw" interrupt |
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| 195 | * table used by the CPU to dispatch interrupt handlers. |
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[aa7f8a1f] | 196 | * |
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| 197 | * Because all interrupts are vectored through the same exception handler |
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[e6dec71c] | 198 | * this is not necessary on thi sport. |
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[f198c63] | 199 | */ |
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| 200 | } |
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| 201 | |
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| 202 | /*PAGE |
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| 203 | * |
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| 204 | * _CPU_ISR_install_vector |
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| 205 | * |
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| 206 | * This kernel routine installs the RTEMS handler for the |
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| 207 | * specified vector. |
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| 208 | * |
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| 209 | * Input parameters: |
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| 210 | * vector - interrupt vector number |
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| 211 | * old_handler - former ISR for this vector number |
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| 212 | * new_handler - replacement ISR for this vector number |
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| 213 | * |
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| 214 | * Output parameters: NONE |
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| 215 | * |
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| 216 | */ |
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| 217 | |
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| 218 | void _CPU_ISR_install_vector( |
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[c346f33d] | 219 | uint32_t vector, |
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[f198c63] | 220 | proc_ptr new_handler, |
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| 221 | proc_ptr *old_handler |
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| 222 | ) |
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| 223 | { |
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| 224 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 225 | |
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| 226 | /* |
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| 227 | * If the interrupt vector table is a table of pointer to isr entry |
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| 228 | * points, then we need to install the appropriate RTEMS interrupt |
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| 229 | * handler for this vector number. |
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| 230 | */ |
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| 231 | |
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| 232 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler ); |
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| 233 | |
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| 234 | /* |
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| 235 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 236 | * be used by the _ISR_Handler so the user gets control. |
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| 237 | */ |
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| 238 | |
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| 239 | _ISR_Vector_table[ vector ] = new_handler; |
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| 240 | } |
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| 241 | |
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| 242 | /*PAGE |
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| 243 | * |
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| 244 | * _CPU_Install_interrupt_stack |
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| 245 | */ |
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| 246 | |
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| 247 | void _CPU_Install_interrupt_stack( void ) |
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| 248 | { |
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| 249 | /* we don't support this yet */ |
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| 250 | } |
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| 251 | |
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| 252 | /*PAGE |
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| 253 | * |
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| 254 | * _CPU_Internal_threads_Idle_thread_body |
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| 255 | * |
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| 256 | * NOTES: |
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| 257 | * |
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| 258 | * 1. This is the same as the regular CPU independent algorithm. |
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| 259 | * |
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| 260 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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| 261 | * instruction, then don't forget to put it in an infinite loop. |
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| 262 | * |
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| 263 | * 3. Be warned. Some processors with onboard DMA have been known |
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| 264 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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| 265 | * also be a problem with other on-chip peripherals. So use this |
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| 266 | * hook with caution. |
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| 267 | */ |
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| 268 | |
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| 269 | void _CPU_Thread_Idle_body( void ) |
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| 270 | { |
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[32f415d] | 271 | #if __mips == 3 |
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| 272 | for( ; ; ) |
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| 273 | asm volatile("wait"); /* use wait to enter low power mode */ |
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| 274 | #elif __mips == 1 |
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| 275 | for( ; ; ) |
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| 276 | ; |
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| 277 | #else |
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| 278 | #error "IDLE: __mips not set to 1 or 3" |
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[f198c63] | 279 | #endif |
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[32f415d] | 280 | } |
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