source: rtems/cpukit/score/cpu/mips/ChangeLog @ febaa8a

4.104.115
Last change on this file since febaa8a was febaa8a, checked in by Joel Sherrill <joel.sherrill@…>, on 03/27/10 at 15:03:09

2010-03-27 Joel Sherrill <joel.sherrill@…>

  • cpu.c, cpu_asm.S: Add include of config.h
  • Property mode set to 100644
File size: 21.1 KB
Line 
12010-03-27      Joel Sherrill <joel.sherrill@oarcorp.com>
2
3        * cpu.c, cpu_asm.S: Add include of config.h
4
52009-03-12      Joel Sherrill <joel.sherrill@OARcorp.com>
6
7        PR 1385/cpukit
8        * cpu_asm.S: When the type rtems_boolean was switched to the C99 bool,
9        the size changed from 4 bytes to 1 byte. The interrupt dispatching
10        code accesses two boolean variables for scheduling purposes and the
11        assembly implementations of this code did not get updated.
12
132009-02-12      Joel Sherrill <joel.sherrill@oarcorp.com>
14
15        * cpu.c, rtems/score/cpu.h: Change prototype of IDLE thread to
16        consistently return void * and take a uintptr_t argument.
17
182009-02-11      Joel Sherrill <joel.sherrill@oarcorp.com>
19
20        * cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and
21        passing address of _Thread_Dispatch to _CPU_Initialize. Clean up
22        comments.
23
242008-09-11      Ralf Corsépius <ralf.corsepius@rtems.org>
25
26        * rtems/score/types.h: Do not define boolean, single_precision,
27        double_precision unless RTEMS_DEPRECATED_TYPES is given.
28
292008-08-21      Ralf Corsépius <ralf.corsepius@rtems.org>
30
31        * rtems/score/types.h: Include stdbool.h.
32        Use bool as base-type for boolean.
33
342008-07-31      Joel Sherrill <joel.sherrill@OARcorp.com>
35
36        * cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads.
37
382008-06-05      Joel Sherrill <joel.sherrill@OARcorp.com>
39
40        * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
41        parameter to indicate that the port uses the Simple Vectored
42        Interrupt model or the Programmable Interrupt Controller Model. The
43        PIC model is implemented primarily in the BSP and it is responsible
44        for all memory allocation.
45
462008-06-04      Joel Sherrill <joel.sherrill@OARcorp.com>
47
48        * rtems/score/cpu.h: Use a constant for CPU_STACK_MINIMUM_SIZE so it
49        can be used in cpp expressions. Using sizeof() requires actually
50        compiling the file.
51
522007-12-17      Joel Sherrill <joel.sherrill@oarcorp.com>
53
54        * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.
55
562007-12-04      Joel Sherrill <joel.sherrill@OARcorp.com>
57
58        * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU
59        Table to Configuration Table. Eliminate CPU Table from all ports.
60        Delete references to CPU Table in all forms.
61
622007-12-03      Joel Sherrill <joel.sherrill@OARcorp.com>
63
64        * rtems/score/cpu.h: Moved most of the remaining CPU Table fields to
65        the Configuration Table. This included pretasking_hook,
66        predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace,
67        extra_mpci_receive_server_stack, stack_allocate_hook, and
68        stack_free_hook. As a side-effect of this effort some multiprocessing
69        code was made conditional and some style clean up occurred.
70
712007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
72
73        * rtems/score/cpu.h: Eliminate the clicks_per_microsecond field in the
74        MIPS CPU Table and define another mechanism for drivers to obtain
75        this information.
76
772007-08-04      Ralf Corsépius <ralf.corsepius@rtems.org>
78
79        * rtems/score/cpu.h: Use uintptr_t instead of uint32_t.
80
812007-05-09      Ralf Corsépius <ralf.corsepius@rtems.org>
82
83        * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
84
852007-04-17      Ralf Corsépius <ralf.corsepius@rtems.org>
86
87        * rtems/score/cpu.h:
88          Use Context_Control_fp* instead of void* for fp_contexts.
89          Eliminate evil casts.
90
912006-11-17      Ralf Corsépius <ralf.corsepius@rtems.org>
92
93        * rtems/score/types.h: Remove unsigned64, signed64.
94
952006-06-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
96
97        * cpu.c: Added __mips==32 to fix build problems on those targets
98        caused by the Bruce Robinson.
99
1002006-06-08 Bruce Robinson <brucer@pmccorp.com>
101
102        * cpu.c: Add int64 types for __mips==3 cpus, incorporate
103           mips_interrupt_mask() into mask computations
104        * cpu_asm.S: Add int64 register save/restores for __mips==3 cpus.  Adjustment
105           of mips1 vs mips3 macros.
106        * cpu.h: Add int64 types for __mips==3 cpus.
107       
1082006-03-17      Ralf Corsepius <ralf.corsepius@rtems.org>
109
110        * cpu.c (_CPU_Initialize): Add fpu initialization.
111        * rtems/score/cpu.h: Setup CPU_*_ENDIAN from GCC's__MIPS{EL|EB}__.
112        (Partial merger of submission by Bruce Robinson <brucer@pmccorp.com>).
113
1142006-01-16      Joel Sherrill <joel@OARcorp.com>
115
116        * rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
117        As a side-effect, grammar and spelling errors were corrected, spacing
118        errors were address, and some variable names were improved.
119
1202005-11-18      Joel Sherrill <joel@OARcorp.com>
121
122        * rtems/score/cpu.h: Eliminate use of unsigned32.
123
1242005-11-08      Ralf Corsepius <ralf.corsepius@rtems.org>
125
126        * rtems/score/types.h: Eliminate unsigned16, unsigned32.
127
1282005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
129
130        * rtems/asm.h: Remove private version of CONCAT macros.
131        Include <rtems/concat.h> instead.
132
1332005-04-26      Joel Sherrill <joel@OARcorp.com>
134
135        * rtems/asm.h: Eliminate warnings.
136
1372005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
138
139        * Makefile.am: Split out preinstallation rules.
140        * preinstall.am: New (Split out from Makefile.am).
141
1422005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
143
144        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
145        Header guards cleanup.
146
1472005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
148
149        PR 754/rtems
150        * rtems/asm.h: New (relocated from .).
151        * asm.h: Remove (moved to rtems/asm.h).
152        * Makefile.am: Reflect changes above.
153
1542005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
155
156        PR rtems/752
157        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
158        New header guards.
159        * idtcpu.h, iregdef.h: Remove.
160        * Makefile.am: Reflect changes above.
161
1622004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
163
164        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
165        New header guards.
166
1672005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
168
169        * rtems/score/types.h: Remove signed8, signed16, signed32,
170        unsigned8, unsigned16, unsigned32.
171
1722005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
173
174        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
175
1762005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
177
178        * rtems/score/types.h: #include <rtems/stdint.h>.
179
1802005-01-07      Joel Sherrill <joel@OARcorp.com>
181
182        * rtems/score/cpu.h: Remove warnings.
183
1842005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
185
186        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
187
1882005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
189
190        PR 739
191        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
192        when compiling cpu_asm.S.  Problem was a #define sneaked in in
193        version 1.11, no ill effects would have only affected R4000
194        builds.
195
1962005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
197
198        PR 737
199        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
200        slot when compiling cpu_asm.S
201
2022005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
203
204        * Makefile.am: Remove build-variant support.
205
2062004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
207
208        PR 730
209        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
210        for rtems-4.7.
211
2122004-04-09      Joel Sherrill <joel@OARcorp.com>
213
214        PR 605/bsps
215        * cpu.c: Do not use C++ style comments.
216
2172004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
218        PR 601
219        * cpu_asm.S: Added __mips==32 support for R4000 processors running
220        32 bit code.  Fixed #define problems that caused fpu code to
221        always be included even when no fpu is present.
222
2232004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
224
225        PR 598/bsps
226        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
227        status/control register on context switches. Missing this register
228        was causing intermittent floating point errors.
229
2302003-09-04      Joel Sherrill <joel@OARcorp.com>
231
232        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
233        rtems/score/types.h: URL for license changed.
234
2352003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
236
237        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
238
2392003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
240
241        * configure.ac: Remove AC_CONFIG_AUX_DIR.
242
2432002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
244
245        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
246        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
247
2482002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
249
250        * configure.ac: Fix package name.
251
2522002-11-04      Joel Sherrill <joel@OARcorp.com>
253
254        * idtcpu.h: Removed warning.
255
2562002-11-01      Joel Sherrill <joel@OARcorp.com>
257
258        * idtcpu.h: Removed warnings.
259
2602002-10-28      Joel Sherrill <joel@OARcorp.com>
261
262        * idtcpu.h: Removed warning by turning extra token at the end of
263        an endif into a comment.
264
2652002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
266
267        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
268
2692002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
270
271        * .cvsignore: Reformat.
272        Add autom4te*cache.
273        Remove autom4te.cache.
274
2752002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
276
277        * cpu_asm.S: Clarified some comments, removed code that forced
278        SR_IEP on when returning from an interrupt.
279
2802002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
281
282        * configure.ac: Add RTEMS_PROG_CCAS
283
2842002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
285
286        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
287        Add AC_PROG_RANLIB.
288
2892002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
290        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
291        deadlock caused by interrupt arriving while dispatching.
292       
2932002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
294
295        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
296        Use ../../../aclocal.
297
2982001-04-03      Joel Sherrill <joel@OARcorp.com>
299
300        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
301        * rtems/score/mipstypes.h: Removed.
302        * rtems/score/types.h: New file via CVS magic.
303        * Makefile.am, rtems/score/cpu.h: Account for name change.
304
3052002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
306
307        * configure.ac:
308        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
309        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
310        * Makefile.am: Remove AUTOMAKE_OPTIONS.
311
3122002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
313
314        * cpu_asm.S: Now compiles on 4600 and 4650.
315
3162002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
317
318        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
319        * rtems/score/cpu.h: Fixed register numbering in comments and made
320        interrupt enable/disable more robust.
321       
3222002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
323        * cpu_asm.S: Added support for the debug exception vector, cleaned
324        up the exception processing & exception return stuff.  Re-added
325        EPC in the task context structure so the gdb stub will know where
326        a thread is executing.  Should've left it there in the first place...
327        * idtcpu.h: Added support for the debug exception vector.
328        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
329        stack frame in an interrupt so context switch code can get the
330        userspace EPC when scheduling.
331        * rtems/score/cpu.h: Re-added EPC to the task context.
332
3332002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
334
335        * cpu_asm.S: Fixed exception return address, modified FP context
336        switch so FPU is properly enabled and also doesn't screw up the
337        exception FP handling.
338        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
339        returning from exceptions.
340        * iregdef.h: Added R_TAR to the stack frame so the target address
341        can be saved on a per-exception basis.  The new entry is past the
342        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
343        stuff.
344        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
345        to obtain FPU defines without syntax errors generated by the C
346        defintions.
347        * cpu.c: Improved interrupt level saves & restores.
348       
3492002-02-08      Joel Sherrill <joel@OARcorp.com>
350
351        * iregdef.h, rtems/score/cpu.h: Reordered register in the
352        exception stack frame to better match gdb's expectations.
353
3542001-02-05      Joel Sherrill <joel@OARcorp.com>
355
356        * cpu_asm.S: Enhanced to save/restore more registers on
357        exceptions.
358        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
359        register individually and document when it is saved.
360        * idtcpu.h: Added constants for the coprocessor 1 registers
361        revision and status.
362
3632001-02-05      Joel Sherrill <joel@OARcorp.com>
364
365        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
366
3672001-02-04      Joel Sherrill <joel@OARcorp.com>
368
369        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
370        in the previous patch that has now been confirmed.
371
3722001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
373
374        * cpu.c: Enhancements and fixes for modifying the SR when changing
375        the interrupt level.
376        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
377        managed on a per-task basis, improved handling of interrupt levels,
378        and made deferred FP contexts work on the MIPS.
379        * rtems/score/cpu.h: Modified to support above changes.
380
3812002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
382
383        * rtems/Makefile.am: Removed.
384        * rtems/score/Makefile.am: Removed.
385        * configure.ac: Reflect changes above.
386        * Makefile.am: Reflect changes above.
387
3882002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
389
390        * asm.h: Remove #include <rtems/score/targopts.h>.
391        Add #include <rtems/score/cpuopts.h>.
392        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
393
394
3952001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
396
397        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
398
3992001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
400
401        * Makefile.am: Add multilib support.
402
4032001-11-28      Joel Sherrill <joel@OARcorp.com>,
404
405        This was tracked as PR91.
406        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
407        is used to specify if the port uses the standard macro for this (FALSE).
408        A TRUE setting indicates the port provides its own implementation.
409
4102001-10-12      Joel Sherrill <joel@OARcorp.com>
411
412        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
413        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
414        Wayne Bullaughey <wayne@wmi.com>.
415
4162001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
417
418        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
419        * configure.in: Remove.
420        * configure.ac: New file, generated from configure.in by autoupdate.
421
4222001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
423
424        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
425        * Makefile.am: Use 'PREINSTALL_FILES ='.
426
4272001-07-03      Joel Sherrill <joel@OARcorp.com>
428
429        * cpu.c: Fixed typo.
430
4312000-05-24      Joel Sherrill <joel@OARcorp.com>
432
433        * rtems/score/mips.h: Added constants for MIPS exception numbers.
434        All exceptions should be given low numbers and thus can be installed
435        and processed in a uniform manner.  Variances between various MIPS
436        ISA levels were not accounted for.
437
4382001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
439
440        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
441        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
442
4432001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
444
445        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
446        the context initialization to account for floating point tasks. 
447        * rtems/score/mips.h: Added the routines mips_set_cause(),
448        mips_get_fcr31(), and mips_set_fcr31().
449        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
450
4512001-05-07      Joel Sherrill <joel@OARcorp.com>
452
453        * cpu_asm.S: Merged patches from Gregory Menke
454        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
455        stack usage and include nops in the delay slots.
456
4572001-04-20      Joel Sherrill <joel@OARcorp.com>
458
459        * cpu_asm.S: Added code to save and restore SR and EPC to
460        properly support nested interrupts.  Note that the ISR
461        (not RTEMS) enables interrupts allowing the nesting to occur.
462
4632001-03-14      Joel Sherrill <joel@OARcorp.com>
464
465        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
466        Removed unused variable _CPU_Thread_dispatch_pointer
467        and cleaned numerous comments.
468       
4692001-03-13      Joel Sherrill <joel@OARcorp.com>
470
471        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
472        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
473        Also reimplemented some assembly routines in C further reducing
474        the amount of assembly and increasing maintainability.
475
4762001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
477
478        * Makefile.am, rtems/score/Makefile.am:
479        Apply include_*HEADERS instead of H_FILES.
480
4812001-01-12      Joel Sherrill <joel@OARcorp.com>
482
483        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
484        register constraints from "general" to "register".
485
4862001-01-09      Joel Sherrill <joel@OARcorp.com>
487
488        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
489        to make it easier to conditionalize the code for various ISA levels.
490
4912001-01-08      Joel Sherrill <joel@OARcorp.com>
492
493        * idtcpu.h: Commented out definition of "wait".  It was stupid to
494        use such a common word as a macro.
495        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
496        * rtems/score/mips.h: Added include of <idtcpu.h>.
497        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
498
4992001-01-03      Joel Sherrill <joel@OARcorp.com>
500
501        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
502        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
503
5042000-12-19      Joel Sherrill <joel@OARcorp.com>
505
506        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
507        Previous code resulting in the interrupted immediately returning
508        to the caller of the routine it was inside.
509
5102000-12-19      Joel Sherrill <joel@OARcorp.com>
511
512        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
513        because it has not been allocated yet.
514
5152000-12-13      Joel Sherrill <joel@OARcorp.com>
516
517        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
518        * cpu_asm.S: Removed assembly language to vector ISR handler
519        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
520        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
521        longer a constant -- get the real value from libcpu.
522
5232000-12-13      Joel Sherrill <joel@OARcorp.com>
524
525        * cpu_asm.h: Removed.
526        * Makefile.am: Remove cpu_asm.h.
527        * rtems/score/mips64orion.h: Renamed mips.h.
528        * rtems/score/mips.h: New file, formerly mips64orion.h.
529        Header rewritten.
530        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
531        mips_disable_in_interrupt_mask): New macros.
532        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
533        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
534        few defines that were in <cpu_asm.h>.
535        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
536        MIPS ISA 3 is still in assembly for now.
537        (_CPU_Thread_Idle_body): Rewrote in C.
538        * cpu_asm.S: Rewrote file header.
539        (FRAME,ENDFRAME) now in asm.h.
540        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
541        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
542        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
543        leaves other bits in SR alone on task switch.
544        (mips_enable_interrupts,mips_disable_interrupts,
545        mips_enable_global_interrupts,mips_disable_global_interrupts,
546        disable_int, enable_int): Removed.
547        (mips_get_sr): Rewritten as C macro.
548        (_CPU_Thread_Idle_body): Rewritten in C.
549        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
550        placed in libcpu.
551        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
552        to libcpu/mips/shared/interrupts.
553        (general): Cleaned up comment blocks and #if 0 areas.
554        * idtcpu.h: Made ifdef report an error.
555        * iregdef.h: Removed warning.
556        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
557        number defined by libcpu.
558        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
559        to access SR.
560        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
561        (_CPU_Context_Initialize): Honor ISR level in task initialization.
562        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
563
5642000-12-06      Joel Sherrill <joel@OARcorp.com>
565
566        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
567        context should be 32 not 64 bits.
568
5692000-11-30      Joel Sherrill <joel@OARcorp.com>
570
571        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
572        correct name of _CPU_Context_switch_restore.  Added dummy
573        version of exc_utlb_code() so applications would link.
574
5752000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
576
577        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
578
5792000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
580
581        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
582
5832000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
584
585        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
586        Switch to GNU canonicalization.
587
5882000-10-24      Alan Cudmore <alanc@linuxstart.com> and
589        Joel Sherrill <joel@OARcorp.com>
590
591        * This is a major reworking of the mips64orion port to use
592        gcc predefines as much as possible and a big push to multilib
593        the mips port.  The mips64orion port was copied/renamed to mips
594        to be more like other GNU tools.  Alan did most of the technical
595        work of determining how to map old macro names used by the mips64orion
596        port to standard compiler macro definitions.  Joel did the merge
597        with CVS magic to keep individual file history and did the BSP
598        modifications. Details follow:
599        * Makefile.am: idtmon.h in mips64orion port not present.
600        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
601        * cpu.c: Comments added.
602        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
603        First attempt at exception/interrupt processing for ISA level 1
604        and minus any use of IDT/MON added.
605        * idtcpu.h: Conditionals changed to use gcc predefines.
606        * iregdef.h: Ditto.
607        * cpu_asm.h: No real change.  Merger required commit.
608        * rtems/Makefile.am: Ditto.
609        * rtems/score/Makefile.am: Ditto.
610        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
611        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
612        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
613
6142000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
615
616        * Makefile.am: Include compile.am.
617
6182000-08-10      Joel Sherrill <joel@OARcorp.com>
619
620        * ChangeLog: New file.
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